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1d5d0ae9 | 1 | /** @file\r |
5a5440d0 PG |
2 | \r |
3 | Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r | |
4 | \r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
1d5d0ae9 | 7 | **/\r |
8 | \r | |
55a0d64b | 9 | #include <Library/ArmGicLib.h>\r |
44788bae | 10 | \r |
11 | #include <Ppi/ArmMpCoreInfo.h>\r | |
12 | \r | |
f598bf12 | 13 | #include "PrePeiCore.h"\r |
14 | \r | |
1d5d0ae9 | 15 | /*\r |
16 | * This is the main function for secondary cores. They loop around until a non Null value is written to\r | |
17 | * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r | |
18 | * Note:The secondary cores, while executing secondary_main, assumes that:\r | |
19 | * : SGI 0 is configured as Non-secure interrupt\r | |
20 | * : Priority Mask is configured to allow SGI 0\r | |
21 | * : Interrupt Distributor and CPU interfaces are enabled\r | |
22 | *\r | |
23 | */\r | |
24 | VOID\r | |
25 | EFIAPI\r | |
f598bf12 | 26 | SecondaryMain (\r |
40b0b23e | 27 | IN UINTN MpId\r |
f598bf12 | 28 | )\r |
1d5d0ae9 | 29 | {\r |
44788bae | 30 | EFI_STATUS Status;\r |
31 | UINTN PpiListSize;\r | |
32 | UINTN PpiListCount;\r | |
33 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
34 | ARM_MP_CORE_INFO_PPI *ArmMpCoreInfoPpi;\r | |
35 | UINTN Index;\r | |
36 | UINTN ArmCoreCount;\r | |
37 | ARM_CORE_INFO *ArmCoreInfoTable;\r | |
38 | UINT32 ClusterId;\r | |
39 | UINT32 CoreId;\r | |
44788bae | 40 | \r |
40b0b23e MK |
41 | VOID (*SecondaryStart)(\r |
42 | VOID\r | |
43 | );\r | |
44 | UINTN SecondaryEntryAddr;\r | |
45 | UINTN AcknowledgeInterrupt;\r | |
46 | UINTN InterruptId;\r | |
47 | \r | |
48 | ClusterId = GET_CLUSTER_ID (MpId);\r | |
49 | CoreId = GET_CORE_ID (MpId);\r | |
44788bae | 50 | \r |
51 | // Get the gArmMpCoreInfoPpiGuid\r | |
52 | PpiListSize = 0;\r | |
53 | ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r | |
40b0b23e | 54 | PpiListCount = PpiListSize / sizeof (EFI_PEI_PPI_DESCRIPTOR);\r |
44788bae | 55 | for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r |
56 | if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {\r | |
57 | break;\r | |
58 | }\r | |
59 | }\r | |
60 | \r | |
61 | // On MP Core Platform we must implement the ARM MP Core Info PPI\r | |
62 | ASSERT (Index != PpiListCount);\r | |
63 | \r | |
64 | ArmMpCoreInfoPpi = PpiList->Ppi;\r | |
40b0b23e MK |
65 | ArmCoreCount = 0;\r |
66 | Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r | |
44788bae | 67 | ASSERT_EFI_ERROR (Status);\r |
68 | \r | |
69 | // Find the core in the ArmCoreTable\r | |
70 | for (Index = 0; Index < ArmCoreCount; Index++) {\r | |
103fa647 RC |
71 | if ((GET_MPIDR_AFF1 (ArmCoreInfoTable[Index].Mpidr) == ClusterId) &&\r |
72 | (GET_MPIDR_AFF0 (ArmCoreInfoTable[Index].Mpidr) == CoreId))\r | |
73 | {\r | |
44788bae | 74 | break;\r |
75 | }\r | |
76 | }\r | |
77 | \r | |
78 | // The ARM Core Info Table must define every core\r | |
79 | ASSERT (Index != ArmCoreCount);\r | |
1d5d0ae9 | 80 | \r |
f598bf12 | 81 | // Clear Secondary cores MailBox\r |
44788bae | 82 | MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r |
1d5d0ae9 | 83 | \r |
315649cd | 84 | do {\r |
44788bae | 85 | ArmCallWFI ();\r |
315649cd | 86 | \r |
87 | // Read the Mailbox\r | |
88 | SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r | |
89 | \r | |
f598bf12 | 90 | // Acknowledge the interrupt and send End of Interrupt signal.\r |
8a1f2378 | 91 | AcknowledgeInterrupt = ArmGicAcknowledgeInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), &InterruptId);\r |
2ca815a4 | 92 | // Check if it is a valid interrupt ID\r |
8a1f2378 | 93 | if (InterruptId < ArmGicGetMaxNumInterrupts (PcdGet64 (PcdGicDistributorBase))) {\r |
2ca815a4 | 94 | // Got a valid SGI number hence signal End of Interrupt\r |
8a1f2378 | 95 | ArmGicEndOfInterrupt (PcdGet64 (PcdGicInterruptInterfaceBase), AcknowledgeInterrupt);\r |
2ca815a4 | 96 | }\r |
f93f248a | 97 | } while (SecondaryEntryAddr == 0);\r |
1d5d0ae9 | 98 | \r |
f598bf12 | 99 | // Jump to secondary core entry point.\r |
40b0b23e MK |
100 | SecondaryStart = (VOID (*)()) SecondaryEntryAddr;\r |
101 | SecondaryStart ();\r | |
1d5d0ae9 | 102 | \r |
f598bf12 | 103 | // The secondaries shouldn't reach here\r |
40b0b23e | 104 | ASSERT (FALSE);\r |
1d5d0ae9 | 105 | }\r |
106 | \r | |
f598bf12 | 107 | VOID\r |
108 | EFIAPI\r | |
109 | PrimaryMain (\r | |
1d5d0ae9 | 110 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
111 | )\r | |
112 | {\r | |
40b0b23e MK |
113 | EFI_SEC_PEI_HAND_OFF SecCoreData;\r |
114 | UINTN PpiListSize;\r | |
115 | EFI_PEI_PPI_DESCRIPTOR *PpiList;\r | |
116 | UINTN TemporaryRamBase;\r | |
117 | UINTN TemporaryRamSize;\r | |
77de7e53 | 118 | \r |
119 | CreatePpiList (&PpiListSize, &PpiList);\r | |
1d5d0ae9 | 120 | \r |
55a0d64b | 121 | // Enable the GIC Distributor\r |
40b0b23e | 122 | ArmGicEnableDistributor (PcdGet64 (PcdGicDistributorBase));\r |
1d5d0ae9 | 123 | \r |
f598bf12 | 124 | // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r |
55a0d64b | 125 | if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r |
f598bf12 | 126 | // Sending SGI to all the Secondary CPU interfaces\r |
40b0b23e | 127 | ArmGicSendSgiTo (PcdGet64 (PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r |
f598bf12 | 128 | }\r |
1d5d0ae9 | 129 | \r |
77de7e53 | 130 | // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r |
131 | // the base of the primary core stack\r | |
40b0b23e | 132 | PpiListSize = ALIGN_VALUE (PpiListSize, CPU_STACK_ALIGNMENT);\r |
bb5420bb | 133 | TemporaryRamBase = (UINTN)PcdGet64 (PcdCPUCoresStackBase) + PpiListSize;\r |
77de7e53 | 134 | TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r |
135 | \r | |
f598bf12 | 136 | //\r |
137 | // Bind this information into the SEC hand-off state\r | |
138 | // Note: this must be in sync with the stuff in the asm file\r | |
139 | // Note also: HOBs (pei temp ram) MUST be above stack\r | |
140 | //\r | |
40b0b23e | 141 | SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);\r |
bb5420bb | 142 | SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet64 (PcdFvBaseAddress);\r |
f92b93c9 | 143 | SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r |
77de7e53 | 144 | SecCoreData.TemporaryRamBase = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r |
145 | SecCoreData.TemporaryRamSize = TemporaryRamSize;\r | |
146 | SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r | |
7945b29c | 147 | SecCoreData.PeiTemporaryRamSize = ALIGN_VALUE (SecCoreData.TemporaryRamSize / 2, CPU_STACK_ALIGNMENT);\r |
bc299a9f | 148 | SecCoreData.StackBase = (VOID *)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r |
3222e7b1 | 149 | SecCoreData.StackSize = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r |
1d5d0ae9 | 150 | \r |
f598bf12 | 151 | // Jump to PEI core entry point\r |
6f711615 | 152 | PeiCoreEntryPoint (&SecCoreData, PpiList);\r |
1d5d0ae9 | 153 | }\r |