ArmPkg/Drivers/ArmGic: Introduced ArmGicEndOfInterrupt()

[mirror_edk2.git] / ArmPlatformPkg / PrePeiCore / MainMPCore.c

/** @file\r
*\r
*  Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
*\r
*  This program and the accompanying materials\r
*  are licensed and made available under the terms and conditions of the BSD License\r
*  which accompanies this distribution.  The full text of the license may be found at\r
*  http://opensource.org/licenses/bsd-license.php\r
*\r
*  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
*  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
*\r
**/\r
\r
#include <Library/ArmGicLib.h>\r
\r
#include <Ppi/ArmMpCoreInfo.h>\r
\r
#include "PrePeiCore.h"\r
\r
/*\r
 * This is the main function for secondary cores. They loop around until a non Null value is written to\r
 * SYS_FLAGS register.The SYS_FLAGS register is platform specific.\r
 * Note:The secondary cores, while executing secondary_main, assumes that:\r
 *      : SGI 0 is configured as Non-secure interrupt\r
 *      : Priority Mask is configured to allow SGI 0\r
 *      : Interrupt Distributor and CPU interfaces are enabled\r
 *\r
 */\r
VOID\r
EFIAPI\r
SecondaryMain (\r
  IN UINTN MpId\r
  )\r
{\r
  EFI_STATUS              Status;\r
  UINTN                   PpiListSize;\r
  UINTN                   PpiListCount;\r
  EFI_PEI_PPI_DESCRIPTOR  *PpiList;\r
  ARM_MP_CORE_INFO_PPI    *ArmMpCoreInfoPpi;\r
  UINTN                   Index;\r
  UINTN                   ArmCoreCount;\r
  ARM_CORE_INFO           *ArmCoreInfoTable;\r
  UINT32                  ClusterId;\r
  UINT32                  CoreId;\r
  VOID                    (*SecondaryStart)(VOID);\r
  UINTN                   SecondaryEntryAddr;\r
\r
  ClusterId = GET_CLUSTER_ID(MpId);\r
  CoreId    = GET_CORE_ID(MpId);\r
\r
  // Get the gArmMpCoreInfoPpiGuid\r
  PpiListSize = 0;\r
  ArmPlatformGetPlatformPpiList (&PpiListSize, &PpiList);\r
  PpiListCount = PpiListSize / sizeof(EFI_PEI_PPI_DESCRIPTOR);\r
  for (Index = 0; Index < PpiListCount; Index++, PpiList++) {\r
    if (CompareGuid (PpiList->Guid, &gArmMpCoreInfoPpiGuid) == TRUE) {\r
      break;\r
    }\r
  }\r
\r
  // On MP Core Platform we must implement the ARM MP Core Info PPI\r
  ASSERT (Index != PpiListCount);\r
\r
  ArmMpCoreInfoPpi = PpiList->Ppi;\r
  ArmCoreCount = 0;\r
  Status = ArmMpCoreInfoPpi->GetMpCoreInfo (&ArmCoreCount, &ArmCoreInfoTable);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // Find the core in the ArmCoreTable\r
  for (Index = 0; Index < ArmCoreCount; Index++) {\r
    if ((ArmCoreInfoTable[Index].ClusterId == ClusterId) && (ArmCoreInfoTable[Index].CoreId == CoreId)) {\r
      break;\r
    }\r
  }\r
\r
  // The ARM Core Info Table must define every core\r
  ASSERT (Index != ArmCoreCount);\r
\r
  // Clear Secondary cores MailBox\r
  MmioWrite32 (ArmCoreInfoTable[Index].MailboxClearAddress, ArmCoreInfoTable[Index].MailboxClearValue);\r
\r
  do {\r
    ArmCallWFI ();\r
\r
    // Read the Mailbox\r
    SecondaryEntryAddr = MmioRead32 (ArmCoreInfoTable[Index].MailboxGetAddress);\r
\r
    // Acknowledge the interrupt and send End of Interrupt signal.\r
    ArmGicAcknowledgeInterrupt (PcdGet32(PcdGicDistributorBase), PcdGet32(PcdGicInterruptInterfaceBase), NULL, NULL);\r
  } while (SecondaryEntryAddr == 0);\r
\r
  // Jump to secondary core entry point.\r
  SecondaryStart = (VOID (*)())SecondaryEntryAddr;\r
  SecondaryStart();\r
\r
  // The secondaries shouldn't reach here\r
  ASSERT(FALSE);\r
}\r
\r
VOID\r
EFIAPI\r
PrimaryMain (\r
  IN  EFI_PEI_CORE_ENTRY_POINT  PeiCoreEntryPoint\r
  )\r
{\r
  EFI_SEC_PEI_HAND_OFF        SecCoreData;\r
  UINTN                       PpiListSize;\r
  EFI_PEI_PPI_DESCRIPTOR      *PpiList;\r
  UINTN                       TemporaryRamBase;\r
  UINTN                       TemporaryRamSize;\r
\r
  CreatePpiList (&PpiListSize, &PpiList);\r
\r
  // Enable the GIC Distributor\r
  ArmGicEnableDistributor (PcdGet32(PcdGicDistributorBase));\r
\r
  // If ArmVe has not been built as Standalone then we need to wake up the secondary cores\r
  if (FeaturePcdGet (PcdSendSgiToBringUpSecondaryCores)) {\r
    // Sending SGI to all the Secondary CPU interfaces\r
    ArmGicSendSgiTo (PcdGet32(PcdGicDistributorBase), ARM_GIC_ICDSGIR_FILTER_EVERYONEELSE, 0x0E, PcdGet32 (PcdGicSgiIntId));\r
  }\r
\r
  // Adjust the Temporary Ram as the new Ppi List (Common + Platform Ppi Lists) is created at\r
  // the base of the primary core stack\r
  PpiListSize = ALIGN_VALUE(PpiListSize, 0x4);\r
  TemporaryRamBase = (UINTN)PcdGet32 (PcdCPUCoresStackBase) + PpiListSize;\r
  TemporaryRamSize = (UINTN)PcdGet32 (PcdCPUCorePrimaryStackSize) - PpiListSize;\r
\r
  // Make sure the size is 8-byte aligned. Once divided by 2, the size should be 4-byte aligned\r
  // to ensure the stack pointer is 4-byte aligned.\r
  TemporaryRamSize = TemporaryRamSize - (TemporaryRamSize & (0x8-1));\r
\r
  //\r
  // Bind this information into the SEC hand-off state\r
  // Note: this must be in sync with the stuff in the asm file\r
  // Note also:  HOBs (pei temp ram) MUST be above stack\r
  //\r
  SecCoreData.DataSize               = sizeof(EFI_SEC_PEI_HAND_OFF);\r
  SecCoreData.BootFirmwareVolumeBase = (VOID *)(UINTN)PcdGet32 (PcdFvBaseAddress);\r
  SecCoreData.BootFirmwareVolumeSize = PcdGet32 (PcdFvSize);\r
  SecCoreData.TemporaryRamBase       = (VOID *)TemporaryRamBase; // We run on the primary core (and so we use the first stack)\r
  SecCoreData.TemporaryRamSize       = TemporaryRamSize;\r
  SecCoreData.PeiTemporaryRamBase    = SecCoreData.TemporaryRamBase;\r
  SecCoreData.PeiTemporaryRamSize    = SecCoreData.TemporaryRamSize / 2;\r
  SecCoreData.StackBase              = (VOID *)ALIGN_VALUE((UINTN)(SecCoreData.TemporaryRamBase) + SecCoreData.PeiTemporaryRamSize, 0x4);\r
  SecCoreData.StackSize              = (TemporaryRamBase + TemporaryRamSize) - (UINTN)SecCoreData.StackBase;\r
\r
  // Jump to PEI core entry point\r
  PeiCoreEntryPoint (&SecCoreData, PpiList);\r
}\r