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1d5d0ae9 | 1 | /** @file\r |
2 | * Main file supporting the transition to PEI Core in Normal World for Versatile Express\r | |
3 | *\r | |
6d0ca257 | 4 | * Copyright (c) 2011-2014, ARM Limited. All rights reserved.\r |
1d5d0ae9 | 5 | *\r |
6dafb303 OM |
6 | * This program and the accompanying materials\r |
7 | * are licensed and made available under the terms and conditions of the BSD License\r | |
8 | * which accompanies this distribution. The full text of the license may be found at\r | |
9 | * http://opensource.org/licenses/bsd-license.php\r | |
10 | *\r | |
11 | * THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | * WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
1d5d0ae9 | 13 | *\r |
14 | **/\r | |
15 | \r | |
1d5d0ae9 | 16 | #include <Library/BaseLib.h>\r |
a6caee65 | 17 | #include <Library/DebugAgentLib.h>\r |
1d5d0ae9 | 18 | #include <Library/ArmLib.h>\r |
8fc38a3f | 19 | \r |
f598bf12 | 20 | #include "PrePeiCore.h"\r |
1d5d0ae9 | 21 | \r |
0c7cc4fb | 22 | CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r |
1d5d0ae9 | 23 | \r |
0c7cc4fb | 24 | CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r |
1d5d0ae9 | 25 | {\r |
8fc38a3f | 26 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r |
1d5d0ae9 | 27 | &gEfiTemporaryRamSupportPpiGuid,\r |
0c7cc4fb | 28 | (VOID *) &mTemporaryRamSupportPpi\r |
1d5d0ae9 | 29 | }\r |
30 | };\r | |
31 | \r | |
77de7e53 | 32 | VOID\r |
33 | CreatePpiList (\r | |
34 | OUT UINTN *PpiListSize,\r | |
35 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
36 | )\r | |
37 | {\r | |
38 | EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r | |
39 | UINTN PlatformPpiListSize;\r | |
40 | UINTN ListBase;\r | |
41 | EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r | |
42 | \r | |
43 | // Get the Platform PPIs\r | |
44 | PlatformPpiListSize = 0;\r | |
45 | ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r | |
46 | \r | |
47 | // Copy the Common and Platform PPis in Temporrary Memory\r | |
bb5420bb | 48 | ListBase = PcdGet64 (PcdCPUCoresStackBase);\r |
77de7e53 | 49 | CopyMem ((VOID*)ListBase, gCommonPpiTable, sizeof(gCommonPpiTable));\r |
50 | CopyMem ((VOID*)(ListBase + sizeof(gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r | |
51 | \r | |
52 | // Set the Terminate flag on the last PPI entry\r | |
53 | LastPpi = (EFI_PEI_PPI_DESCRIPTOR*)ListBase + ((sizeof(gCommonPpiTable) + PlatformPpiListSize) / sizeof(EFI_PEI_PPI_DESCRIPTOR)) - 1;\r | |
54 | LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r | |
55 | \r | |
56 | *PpiList = (EFI_PEI_PPI_DESCRIPTOR*)ListBase;\r | |
57 | *PpiListSize = sizeof(gCommonPpiTable) + PlatformPpiListSize;\r | |
58 | }\r | |
59 | \r | |
1d5d0ae9 | 60 | VOID\r |
61 | CEntryPoint (\r | |
0787bc61 | 62 | IN UINTN MpId,\r |
1d5d0ae9 | 63 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
64 | )\r | |
65 | {\r | |
6dafb303 OM |
66 | // Data Cache enabled on Primary core when MMU is enabled.\r |
67 | ArmDisableDataCache ();\r | |
68 | // Invalidate Data cache\r | |
69 | ArmInvalidateDataCache ();\r | |
70 | // Invalidate instruction cache\r | |
a9d7090f | 71 | ArmInvalidateInstructionCache ();\r |
6dafb303 | 72 | // Enable Instruction Caches on all cores.\r |
f598bf12 | 73 | ArmEnableInstructionCache ();\r |
1d5d0ae9 | 74 | \r |
75 | //\r | |
76 | // Note: Doesn't have to Enable CPU interface in non-secure world,\r | |
77 | // as Non-secure interface is already enabled in Secure world.\r | |
78 | //\r | |
79 | \r | |
a9d7090f | 80 | // Write VBAR - The Exception Vector table must be aligned to its requirement\r |
6d0ca257 OM |
81 | // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r |
82 | // 'Align=4K' is defined into your FDF for this module.\r | |
83 | ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r | |
a9d7090f | 84 | ArmWriteVBar ((UINTN)PeiVectorTable);\r |
1d5d0ae9 | 85 | \r |
86 | //Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r | |
87 | \r | |
77de7e53 | 88 | // If not primary Jump to Secondary Main\r |
bebda7ce | 89 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
a6caee65 | 90 | // Initialize the Debug Agent for Source Level Debugging\r |
91 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
92 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
93 | \r | |
f437141a | 94 | // Initialize the platform specific controllers\r |
95 | ArmPlatformInitialize (MpId);\r | |
96 | \r | |
a6caee65 | 97 | // Goto primary Main.\r |
f598bf12 | 98 | PrimaryMain (PeiCoreEntryPoint);\r |
1d5d0ae9 | 99 | } else {\r |
0787bc61 | 100 | SecondaryMain (MpId);\r |
1d5d0ae9 | 101 | }\r |
102 | \r | |
103 | // PEI Core should always load and never return\r | |
104 | ASSERT (FALSE);\r | |
105 | }\r | |
106 | \r | |
107 | EFI_STATUS\r | |
108 | EFIAPI\r | |
93d451c6 | 109 | PrePeiCoreTemporaryRamSupport (\r |
1d5d0ae9 | 110 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
111 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
112 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
113 | IN UINTN CopySize\r | |
114 | )\r | |
115 | {\r | |
93d451c6 | 116 | VOID *OldHeap;\r |
117 | VOID *NewHeap;\r | |
118 | VOID *OldStack;\r | |
119 | VOID *NewStack;\r | |
4960d8e0 HG |
120 | UINTN HeapSize;\r |
121 | \r | |
122 | HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r | |
93d451c6 | 123 | \r |
124 | OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r | |
4960d8e0 | 125 | NewHeap = (VOID*)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r |
93d451c6 | 126 | \r |
4960d8e0 | 127 | OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);\r |
93d451c6 | 128 | NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r |
129 | \r | |
130 | //\r | |
131 | // Migrate the temporary memory stack to permanent memory stack.\r | |
1d5d0ae9 | 132 | //\r |
4960d8e0 | 133 | CopyMem (NewStack, OldStack, CopySize - HeapSize);\r |
93d451c6 | 134 | \r |
135 | //\r | |
136 | // Migrate the temporary memory heap to permanent memory heap.\r | |
f598bf12 | 137 | //\r |
4960d8e0 | 138 | CopyMem (NewHeap, OldHeap, HeapSize);\r |
3402aac7 | 139 | \r |
93d451c6 | 140 | SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r |
1d5d0ae9 | 141 | \r |
93d451c6 | 142 | return EFI_SUCCESS;\r |
143 | }\r |