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1d5d0ae9 | 1 | /** @file\r |
5a5440d0 PG |
2 | Main file supporting the transition to PEI Core in Normal World for Versatile Express\r |
3 | \r | |
22c45b7c | 4 | Copyright (c) 2011 - 2022, ARM Limited. All rights reserved.\r |
5a5440d0 PG |
5 | \r |
6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
7 | \r | |
1d5d0ae9 | 8 | **/\r |
9 | \r | |
1d5d0ae9 | 10 | #include <Library/BaseLib.h>\r |
6c9a3d42 | 11 | #include <Library/CacheMaintenanceLib.h>\r |
a6caee65 | 12 | #include <Library/DebugAgentLib.h>\r |
1d5d0ae9 | 13 | #include <Library/ArmLib.h>\r |
56035d1c RC |
14 | #include <Library/PrintLib.h>\r |
15 | #include <Library/SerialPortLib.h>\r | |
8fc38a3f | 16 | \r |
f598bf12 | 17 | #include "PrePeiCore.h"\r |
1d5d0ae9 | 18 | \r |
40b0b23e | 19 | CONST EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI mTemporaryRamSupportPpi = { PrePeiCoreTemporaryRamSupport };\r |
1d5d0ae9 | 20 | \r |
40b0b23e | 21 | CONST EFI_PEI_PPI_DESCRIPTOR gCommonPpiTable[] = {\r |
1d5d0ae9 | 22 | {\r |
8fc38a3f | 23 | EFI_PEI_PPI_DESCRIPTOR_PPI,\r |
1d5d0ae9 | 24 | &gEfiTemporaryRamSupportPpiGuid,\r |
40b0b23e | 25 | (VOID *)&mTemporaryRamSupportPpi\r |
1d5d0ae9 | 26 | }\r |
27 | };\r | |
28 | \r | |
77de7e53 | 29 | VOID\r |
30 | CreatePpiList (\r | |
31 | OUT UINTN *PpiListSize,\r | |
32 | OUT EFI_PEI_PPI_DESCRIPTOR **PpiList\r | |
33 | )\r | |
34 | {\r | |
40b0b23e | 35 | EFI_PEI_PPI_DESCRIPTOR *PlatformPpiList;\r |
77de7e53 | 36 | UINTN PlatformPpiListSize;\r |
37 | UINTN ListBase;\r | |
40b0b23e | 38 | EFI_PEI_PPI_DESCRIPTOR *LastPpi;\r |
77de7e53 | 39 | \r |
40 | // Get the Platform PPIs\r | |
41 | PlatformPpiListSize = 0;\r | |
42 | ArmPlatformGetPlatformPpiList (&PlatformPpiListSize, &PlatformPpiList);\r | |
43 | \r | |
16f3544d | 44 | // Copy the Common and Platform PPis in Temporary Memory\r |
bb5420bb | 45 | ListBase = PcdGet64 (PcdCPUCoresStackBase);\r |
40b0b23e MK |
46 | CopyMem ((VOID *)ListBase, gCommonPpiTable, sizeof (gCommonPpiTable));\r |
47 | CopyMem ((VOID *)(ListBase + sizeof (gCommonPpiTable)), PlatformPpiList, PlatformPpiListSize);\r | |
77de7e53 | 48 | \r |
49 | // Set the Terminate flag on the last PPI entry\r | |
40b0b23e | 50 | LastPpi = (EFI_PEI_PPI_DESCRIPTOR *)ListBase + ((sizeof (gCommonPpiTable) + PlatformPpiListSize) / sizeof (EFI_PEI_PPI_DESCRIPTOR)) - 1;\r |
77de7e53 | 51 | LastPpi->Flags |= EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST;\r |
52 | \r | |
40b0b23e MK |
53 | *PpiList = (EFI_PEI_PPI_DESCRIPTOR *)ListBase;\r |
54 | *PpiListSize = sizeof (gCommonPpiTable) + PlatformPpiListSize;\r | |
77de7e53 | 55 | }\r |
56 | \r | |
56035d1c RC |
57 | /**\r |
58 | \r | |
59 | Prints firmware version and build time to serial console.\r | |
60 | \r | |
61 | **/\r | |
62 | STATIC\r | |
63 | VOID\r | |
64 | PrintFirmwareVersion (\r | |
65 | VOID\r | |
66 | )\r | |
67 | {\r | |
68 | CHAR8 Buffer[100];\r | |
69 | UINTN CharCount;\r | |
70 | \r | |
71 | CharCount = AsciiSPrint (\r | |
72 | Buffer,\r | |
73 | sizeof (Buffer),\r | |
74 | "UEFI firmware (version %s built at %a on %a)\n\r",\r | |
75 | (CHAR16 *)PcdGetPtr (PcdFirmwareVersionString),\r | |
76 | __TIME__,\r | |
77 | __DATE__\r | |
78 | );\r | |
79 | SerialPortWrite ((UINT8 *)Buffer, CharCount);\r | |
80 | }\r | |
81 | \r | |
1d5d0ae9 | 82 | VOID\r |
83 | CEntryPoint (\r | |
0787bc61 | 84 | IN UINTN MpId,\r |
1d5d0ae9 | 85 | IN EFI_PEI_CORE_ENTRY_POINT PeiCoreEntryPoint\r |
86 | )\r | |
87 | {\r | |
fb493ac8 AB |
88 | if (!ArmMmuEnabled ()) {\r |
89 | // Data Cache enabled on Primary core when MMU is enabled.\r | |
90 | ArmDisableDataCache ();\r | |
91 | // Invalidate instruction cache\r | |
92 | ArmInvalidateInstructionCache ();\r | |
93 | // Enable Instruction Caches on all cores.\r | |
94 | ArmEnableInstructionCache ();\r | |
95 | \r | |
96 | InvalidateDataCacheRange (\r | |
97 | (VOID *)(UINTN)PcdGet64 (PcdCPUCoresStackBase),\r | |
98 | PcdGet32 (PcdCPUCorePrimaryStackSize)\r | |
99 | );\r | |
100 | }\r | |
6c9a3d42 | 101 | \r |
1d5d0ae9 | 102 | //\r |
103 | // Note: Doesn't have to Enable CPU interface in non-secure world,\r | |
104 | // as Non-secure interface is already enabled in Secure world.\r | |
105 | //\r | |
106 | \r | |
a9d7090f | 107 | // Write VBAR - The Exception Vector table must be aligned to its requirement\r |
6d0ca257 OM |
108 | // Note: The AArch64 Vector table must be 2k-byte aligned - if this assertion fails ensure\r |
109 | // 'Align=4K' is defined into your FDF for this module.\r | |
110 | ASSERT (((UINTN)PeiVectorTable & ARM_VECTOR_TABLE_ALIGNMENT) == 0);\r | |
a9d7090f | 111 | ArmWriteVBar ((UINTN)PeiVectorTable);\r |
1d5d0ae9 | 112 | \r |
a6a835bd AB |
113 | // Enable Floating Point\r |
114 | if (FixedPcdGet32 (PcdVFPEnabled)) {\r | |
115 | ArmEnableVFP ();\r | |
116 | }\r | |
117 | \r | |
40b0b23e | 118 | // Note: The MMU will be enabled by MemoryPeim. Only the primary core will have the MMU on.\r |
1d5d0ae9 | 119 | \r |
77de7e53 | 120 | // If not primary Jump to Secondary Main\r |
bebda7ce | 121 | if (ArmPlatformIsPrimaryCore (MpId)) {\r |
22c45b7c RM |
122 | // Invoke "ProcessLibraryConstructorList" to have all library constructors\r |
123 | // called.\r | |
124 | ProcessLibraryConstructorList ();\r | |
125 | \r | |
56035d1c RC |
126 | PrintFirmwareVersion ();\r |
127 | \r | |
a6caee65 | 128 | // Initialize the Debug Agent for Source Level Debugging\r |
129 | InitializeDebugAgent (DEBUG_AGENT_INIT_POSTMEM_SEC, NULL, NULL);\r | |
130 | SaveAndSetDebugTimerInterrupt (TRUE);\r | |
131 | \r | |
f437141a | 132 | // Initialize the platform specific controllers\r |
133 | ArmPlatformInitialize (MpId);\r | |
134 | \r | |
a6caee65 | 135 | // Goto primary Main.\r |
f598bf12 | 136 | PrimaryMain (PeiCoreEntryPoint);\r |
1d5d0ae9 | 137 | } else {\r |
0787bc61 | 138 | SecondaryMain (MpId);\r |
1d5d0ae9 | 139 | }\r |
140 | \r | |
141 | // PEI Core should always load and never return\r | |
142 | ASSERT (FALSE);\r | |
143 | }\r | |
144 | \r | |
145 | EFI_STATUS\r | |
146 | EFIAPI\r | |
93d451c6 | 147 | PrePeiCoreTemporaryRamSupport (\r |
40b0b23e MK |
148 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
149 | IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r | |
150 | IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r | |
151 | IN UINTN CopySize\r | |
1d5d0ae9 | 152 | )\r |
153 | {\r | |
40b0b23e MK |
154 | VOID *OldHeap;\r |
155 | VOID *NewHeap;\r | |
156 | VOID *OldStack;\r | |
157 | VOID *NewStack;\r | |
158 | UINTN HeapSize;\r | |
4960d8e0 HG |
159 | \r |
160 | HeapSize = ALIGN_VALUE (CopySize / 2, CPU_STACK_ALIGNMENT);\r | |
93d451c6 | 161 | \r |
40b0b23e MK |
162 | OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;\r |
163 | NewHeap = (VOID *)((UINTN)PermanentMemoryBase + (CopySize - HeapSize));\r | |
93d451c6 | 164 | \r |
40b0b23e MK |
165 | OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);\r |
166 | NewStack = (VOID *)(UINTN)PermanentMemoryBase;\r | |
93d451c6 | 167 | \r |
168 | //\r | |
169 | // Migrate the temporary memory stack to permanent memory stack.\r | |
1d5d0ae9 | 170 | //\r |
4960d8e0 | 171 | CopyMem (NewStack, OldStack, CopySize - HeapSize);\r |
93d451c6 | 172 | \r |
173 | //\r | |
174 | // Migrate the temporary memory heap to permanent memory heap.\r | |
f598bf12 | 175 | //\r |
4960d8e0 | 176 | CopyMem (NewHeap, OldHeap, HeapSize);\r |
3402aac7 | 177 | \r |
93d451c6 | 178 | SecSwitchStack ((UINTN)NewStack - (UINTN)OldStack);\r |
1d5d0ae9 | 179 | \r |
93d451c6 | 180 | return EFI_SUCCESS;\r |
181 | }\r |