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1d5d0ae9 | 1 | //\r |
2 | // Copyright (c) 2011, ARM Limited. All rights reserved.\r | |
3 | // \r | |
4 | // This program and the accompanying materials \r | |
5 | // are licensed and made available under the terms and conditions of the BSD License \r | |
6 | // which accompanies this distribution. The full text of the license may be found at \r | |
7 | // http://opensource.org/licenses/bsd-license.php \r | |
8 | //\r | |
9 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
10 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
11 | //\r | |
12 | //\r | |
13 | \r | |
14 | #include <AsmMacroIoLib.h>\r | |
15 | #include <Base.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | \r | |
19 | INCLUDE AsmMacroIoLib.inc\r | |
20 | \r | |
21 | IMPORT CEntryPoint\r | |
22 | EXPORT _ModuleEntryPoint\r | |
23 | \r | |
24 | PRESERVE8\r | |
25 | AREA PrePeiCoreEntryPoint, CODE, READONLY\r | |
26 | \r | |
27 | StartupAddr DCD CEntryPoint\r | |
28 | \r | |
1d5d0ae9 | 29 | _ModuleEntryPoint\r |
30 | // Identify CPU ID\r | |
31 | mrc p15, 0, r0, c0, c0, 5\r | |
32 | and r0, #0xf\r | |
33 | \r | |
34 | _SetupStack\r | |
35 | // Setup Stack for the 4 CPU cores\r | |
36 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackBase) ,r1)\r | |
37 | LoadConstantToReg (FixedPcdGet32(PcdCPUCoresNonSecStackSize) ,r2)\r | |
38 | \r | |
39 | mov r3,r0 // r3 = core_id\r | |
40 | mul r3,r3,r2 // r3 = core_id * stack_size = offset from the stack base\r | |
41 | add r3,r3,r1 // r3 = stack_base + offset\r | |
42 | add r3,r3,r2,LSR #1 // r3 = stack_offset + (stack_size/2) <-- the top half is for the heap\r | |
43 | mov sp, r3\r | |
44 | \r | |
45 | // The PEI Core Entry Point has been computed by GenFV and stored in the second entry of the Reset Vector\r | |
262a9b04 | 46 | LoadConstantToReg (FixedPcdGet32(PcdNormalFdBaseAddress), r2)\r |
1d5d0ae9 | 47 | add r2, r2, #4\r |
48 | ldr r1, [r2]\r | |
49 | \r | |
50 | // move sec startup address into a data register\r | |
51 | // ensure we're jumping to FV version of the code (not boot remapped alias)\r | |
52 | ldr r2, StartupAddr\r | |
53 | \r | |
262a9b04 | 54 | // jump to PrePeiCore C code\r |
1d5d0ae9 | 55 | // r0 = core_id\r |
56 | // r1 = pei_core_address\r | |
57 | blx r2\r | |
58 | \r | |
59 | END\r |