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cd872e40 1//\r
272a1db6 2// Copyright (c) 2011 - 2020, Arm Limited. All rights reserved.<BR>\r
cd872e40 3//\r
f4dfad05 4// SPDX-License-Identifier: BSD-2-Clause-Patent\r
cd872e40 5//\r
6//\r
7\r
cd872e40 8#include <AutoGen.h>\r
063ad84e 9#include <Chipset/ArmV7.h>\r
10\r
cd872e40 11 INCLUDE AsmMacroIoLib.inc\r
3402aac7 12\r
cd872e40 13 IMPORT CEntryPoint\r
bebda7ce 14 IMPORT ArmPlatformIsPrimaryCore\r
0787bc61 15 IMPORT ArmReadMpidr\r
b5a57223 16 IMPORT ArmPlatformPeiBootAction\r
695df8ba 17 IMPORT ArmPlatformStackSet\r
4aae7419 18 IMPORT mSystemMemoryEnd\r
3402aac7 19\r
cd872e40 20 EXPORT _ModuleEntryPoint\r
21\r
22 PRESERVE8\r
23 AREA PrePiCoreEntryPoint, CODE, READONLY\r
3402aac7 24\r
cd872e40 25StartupAddr DCD CEntryPoint\r
26\r
27_ModuleEntryPoint\r
b5a57223 28 // Do early platform specific actions\r
29 bl ArmPlatformPeiBootAction\r
30\r
272a1db6 31 // Get ID of this CPU in multi-core system\r
0787bc61 32 bl ArmReadMpidr\r
bebda7ce 33 // Keep a copy of the MpId register value\r
c2d87a49 34 mov r8, r0\r
cd872e40 35\r
d269095b 36_SetSVCMode\r
99565b88 37 // Enter SVC mode, Disable FIQ and IRQ\r
063ad84e 38 mov r1, #(CPSR_MODE_SVC :OR: CPSR_IRQ :OR: CPSR_FIQ)\r
d269095b 39 msr CPSR_c, r1\r
40\r
2dbcb8f0 41// Check if we can install the stack at the top of the System Memory or if we need\r
d269095b 42// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
43// at the top of the DRAM)\r
5dbacdb2 44_SystemMemoryEndInit\r
b0609e4f 45 adrll r1, mSystemMemoryEnd\r
4aae7419
AB
46 ldrd r2, r3, [r1]\r
47 teq r3, #0\r
48 moveq r1, r2\r
49 mvnne r1, #0\r
5dbacdb2
OM
50\r
51_SetupStackPosition\r
52 // r1 = SystemMemoryTop\r
cd872e40 53\r
d269095b 54 // Calculate Top of the Firmware Device\r
66edb631
AB
55 mov32 r2, FixedPcdGet32(PcdFdBaseAddress)\r
56 mov32 r3, FixedPcdGet32(PcdFdSize)\r
2569b068 57 sub r3, r3, #1\r
7defe7b3 58 add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
d269095b 59\r
60 // UEFI Memory Size (stacks are allocated in this region)\r
66edb631 61 mov32 r4, FixedPcdGet32(PcdSystemMemoryUefiRegionSize)\r
d269095b 62\r
63 //\r
64 // Reserve the memory for the UEFI region (contain stacks on its top)\r
65 //\r
66\r
67 // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
91c38d4e
RC
68 subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
69 bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
70 cmp r0, r4\r
71 bge _SetupStack\r
d269095b 72\r
73 // Case the top of stacks is the FdBaseAddress\r
91c38d4e 74 mov r1, r2\r
cd872e40 75\r
76_SetupStack\r
2dbcb8f0 77 // r1 contains the top of the stack (and the UEFI Memory)\r
d269095b 78\r
2569b068 79 // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
80 // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
81 // top of the memory space)\r
c2d87a49 82 adds r9, r1, #1\r
2569b068 83 bcs _SetupOverflowStack\r
84\r
85_SetupAlignedStack\r
c2d87a49 86 mov r1, r9\r
2569b068 87 b _GetBaseUefiMemory\r
88\r
89_SetupOverflowStack\r
90 // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
91 // aligned (4KB)\r
66edb631 92 mov32 r9, EFI_PAGE_MASK\r
c2d87a49
OM
93 and r9, r9, r1\r
94 sub r1, r1, r9\r
2569b068 95\r
96_GetBaseUefiMemory\r
d269095b 97 // Calculate the Base of the UEFI Memory\r
c2d87a49 98 sub r9, r1, r4\r
cd872e40 99\r
2dbcb8f0 100_GetStackBase\r
1377db63 101 // r1 = The top of the Mpcore Stacks\r
2dbcb8f0 102 // Stack for the primary core = PrimaryCoreStack\r
66edb631 103 mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)\r
c2d87a49 104 sub r10, r1, r2\r
695df8ba 105\r
106 // Stack for the secondary core = Number of Cores - 1\r
66edb631 107 mov32 r1, (FixedPcdGet32(PcdCoreCount) - 1) * FixedPcdGet32(PcdCPUCoreSecondaryStackSize)\r
c2d87a49 108 sub r10, r10, r1\r
695df8ba 109\r
c2d87a49 110 // r10 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
91c38d4e
RC
111 mov r0, r10\r
112 mov r1, r8\r
695df8ba 113 //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
66edb631
AB
114 mov32 r2, FixedPcdGet32(PcdCPUCorePrimaryStackSize)\r
115 mov32 r3, FixedPcdGet32(PcdCPUCoreSecondaryStackSize)\r
91c38d4e 116 bl ArmPlatformStackSet\r
2dbcb8f0 117\r
118 // Is it the Primary Core ?\r
c2d87a49 119 mov r0, r8\r
bebda7ce 120 bl ArmPlatformIsPrimaryCore\r
121 cmp r0, #1\r
cd872e40 122 bne _PrepareArguments\r
123\r
cd872e40 124_PrepareArguments\r
c2d87a49
OM
125 mov r0, r8\r
126 mov r1, r9\r
127 mov r2, r10\r
c524ffbb 128\r
cd872e40 129 // Move sec startup address into a data register\r
130 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
c524ffbb 131 ldr r4, StartupAddr\r
cd872e40 132\r
d269095b 133 // Jump to PrePiCore C code\r
0787bc61 134 // r0 = MpId\r
cd872e40 135 // r1 = UefiMemoryBase\r
c524ffbb 136 // r2 = StacksBase\r
c524ffbb 137 blx r4\r
cd872e40 138\r
2dbcb8f0 139_NeverReturn\r
140 b _NeverReturn\r
141\r
cd872e40 142 END\r