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cd872e40 1//\r
2569b068 2// Copyright (c) 2011-2012, ARM Limited. All rights reserved.\r
cd872e40 3//\r
4// This program and the accompanying materials\r
5// are licensed and made available under the terms and conditions of the BSD License\r
6// which accompanies this distribution. The full text of the license may be found at\r
7// http://opensource.org/licenses/bsd-license.php\r
8//\r
9// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
10// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
11//\r
12//\r
13\r
14#include <AsmMacroIoLib.h>\r
15#include <Base.h>\r
16#include <Library/PcdLib.h>\r
17#include <AutoGen.h>\r
18\r
19 INCLUDE AsmMacroIoLib.inc\r
20 \r
21 IMPORT CEntryPoint\r
0787bc61 22 IMPORT ArmReadMpidr\r
695df8ba 23 IMPORT ArmPlatformStackSet\r
24 \r
cd872e40 25 EXPORT _ModuleEntryPoint\r
26\r
27 PRESERVE8\r
28 AREA PrePiCoreEntryPoint, CODE, READONLY\r
29 \r
30StartupAddr DCD CEntryPoint\r
31\r
32_ModuleEntryPoint\r
0787bc61 33 // Get ID of this CPU in Multicore system\r
34 bl ArmReadMpidr\r
35 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCoreMask), r1)\r
17839a45 36 and r6, r0, r1\r
cd872e40 37\r
d269095b 38_SetSVCMode\r
99565b88 39 // Enter SVC mode, Disable FIQ and IRQ\r
17839a45 40 //TODO: remove hardcoded values\r
2575b726 41 mov r1, #0x13 :OR: 0x80 :OR: 0x40\r
d269095b 42 msr CPSR_c, r1\r
43\r
2dbcb8f0 44// Check if we can install the stack at the top of the System Memory or if we need\r
d269095b 45// to install the stacks at the bottom of the Firmware Device (case the FD is located\r
46// at the top of the DRAM)\r
47_SetupStackPosition\r
cd872e40 48 // Compute Top of System Memory\r
49 LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryBase), r1)\r
50 LoadConstantToReg (FixedPcdGet32(PcdSystemMemorySize), r2)\r
2569b068 51 sub r2, r2, #1\r
cd872e40 52 add r1, r1, r2 // r1 = SystemMemoryTop = PcdSystemMemoryBase + PcdSystemMemorySize\r
cd872e40 53\r
d269095b 54 // Calculate Top of the Firmware Device\r
f92b93c9 55 LoadConstantToReg (FixedPcdGet32(PcdFdBaseAddress), r2)\r
56 LoadConstantToReg (FixedPcdGet32(PcdFdSize), r3)\r
2569b068 57 sub r3, r3, #1\r
7defe7b3 58 add r3, r3, r2 // r3 = FdTop = PcdFdBaseAddress + PcdFdSize\r
d269095b 59\r
60 // UEFI Memory Size (stacks are allocated in this region)\r
61 LoadConstantToReg (FixedPcdGet32(PcdSystemMemoryUefiRegionSize), r4)\r
62\r
63 //\r
64 // Reserve the memory for the UEFI region (contain stacks on its top)\r
65 //\r
66\r
67 // Calculate how much space there is between the top of the Firmware and the Top of the System Memory\r
2dbcb8f0 68 subs r0, r1, r3 // r0 = SystemMemoryTop - FdTop\r
69 bmi _SetupStack // Jump if negative (FdTop > SystemMemoryTop). Case when the PrePi is in XIP memory outside of the DRAM\r
70 cmp r0, r4\r
d269095b 71 bge _SetupStack\r
72\r
73 // Case the top of stacks is the FdBaseAddress\r
74 mov r1, r2\r
cd872e40 75\r
76_SetupStack\r
2dbcb8f0 77 // r1 contains the top of the stack (and the UEFI Memory)\r
d269095b 78\r
2569b068 79 // Because the 'push' instruction is equivalent to 'stmdb' (decrement before), we need to increment\r
80 // one to the top of the stack. We check if incrementing one does not overflow (case of DRAM at the\r
81 // top of the memory space)\r
17839a45 82 adds r7, r1, #1\r
2569b068 83 bcs _SetupOverflowStack\r
84\r
85_SetupAlignedStack\r
17839a45 86 mov r1, r7\r
2569b068 87 b _GetBaseUefiMemory\r
88\r
89_SetupOverflowStack\r
90 // Case memory at the top of the address space. Ensure the top of the stack is EFI_PAGE_SIZE\r
91 // aligned (4KB)\r
17839a45 92 LoadConstantToReg (EFI_PAGE_MASK, r7)\r
93 and r7, r7, r1\r
94 sub r1, r1, r7\r
2569b068 95\r
96_GetBaseUefiMemory\r
d269095b 97 // Calculate the Base of the UEFI Memory\r
17839a45 98 sub r7, r1, r4\r
cd872e40 99\r
2dbcb8f0 100_GetStackBase\r
1377db63 101 // r1 = The top of the Mpcore Stacks\r
2dbcb8f0 102 // Stack for the primary core = PrimaryCoreStack\r
103 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
695df8ba 104 sub r8, r1, r2\r
105\r
106 // Stack for the secondary core = Number of Cores - 1\r
107 LoadConstantToReg (FixedPcdGet32(PcdCoreCount), r0)\r
108 sub r0, r0, #1\r
109 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r1)\r
110 mul r1, r1, r0\r
111 sub r8, r8, r1\r
112\r
113 // r8 = The base of the MpCore Stacks (primary stack & secondary stacks)\r
114 mov r0, r8\r
115 mov r1, r6\r
116 //ArmPlatformStackSet(StackBase, MpId, PrimaryStackSize, SecondaryStackSize)\r
117 LoadConstantToReg (FixedPcdGet32(PcdCPUCorePrimaryStackSize), r2)\r
2dbcb8f0 118 LoadConstantToReg (FixedPcdGet32(PcdCPUCoreSecondaryStackSize), r3)\r
17839a45 119 bl ArmPlatformStackSet\r
2dbcb8f0 120\r
121 // Is it the Primary Core ?\r
122 LoadConstantToReg (FixedPcdGet32(PcdArmPrimaryCore), r4)\r
17839a45 123 cmp r6, r4\r
cd872e40 124 bne _PrepareArguments\r
125\r
17839a45 126_ReserveGlobalVariable\r
127 LoadConstantToReg (FixedPcdGet32(PcdPeiGlobalVariableSize), r0)\r
128 // InitializePrimaryStack($GlobalVariableSize, $Tmp1)\r
129 InitializePrimaryStack r0, r1\r
2dbcb8f0 130\r
cd872e40 131_PrepareArguments\r
17839a45 132 mov r0, r6\r
133 mov r1, r7\r
134 mov r2, r8\r
c524ffbb 135 mov r3, sp\r
136\r
cd872e40 137 // Move sec startup address into a data register\r
138 // Ensure we're jumping to FV version of the code (not boot remapped alias)\r
c524ffbb 139 ldr r4, StartupAddr\r
cd872e40 140\r
d269095b 141 // Jump to PrePiCore C code\r
0787bc61 142 // r0 = MpId\r
cd872e40 143 // r1 = UefiMemoryBase\r
c524ffbb 144 // r2 = StacksBase\r
145 // r3 = GlobalVariableBase\r
146 blx r4\r
cd872e40 147\r
2dbcb8f0 148_NeverReturn\r
149 b _NeverReturn\r
150\r
cd872e40 151 END\r