[mirror_edk2.git] / ArmPlatformPkg / Sec / AArch64 / Helper.S

#========================================================================================\r
#  Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
#\r
#  This program and the accompanying materials\r
#  are licensed and made available under the terms and conditions of the BSD License\r
#  which accompanies this distribution.  The full text of the license may be found at\r
#  http:#opensource.org/licenses/bsd-license.php\r
#\r
#  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
#  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
#=======================================================================================\r
\r
#include <AsmMacroIoLibV8.h>\r
#include <Chipset/AArch64.h>\r
\r
#start of the code section\r
.text\r
.align 3\r
\r
ASM_GLOBAL ASM_PFX(SetupExceptionLevel3)\r
ASM_GLOBAL ASM_PFX(SwitchToNSExceptionLevel1)\r
ASM_GLOBAL ASM_PFX(enter_monitor_mode)\r
ASM_GLOBAL ASM_PFX(return_from_exception)\r
ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)\r
ASM_GLOBAL ASM_PFX(set_non_secure_mode)\r
\r
ASM_PFX(SetupExceptionLevel3):\r
   mrs    x0, scr_el3            // Read EL3 Secure Configuration Register\r
   orr    x0, x0, #1             // EL0 an EL1 cannot access secure memory\r
\r
   // Send all interrupts to their respective Exception levels for EL3\r
   bic    x0, x0, #(1 << 1)      // IRQ\r
   bic    x0, x0, #(1 << 2)      // FIQ\r
   bic    x0, x0, #(1 << 3)      // Serror and Abort\r
   orr    x0, x0, #(1 << 8)      // Enable HVC\r
   orr    x0, x0, #(1 << 10)     // Make next level down 64Bit. This is EL2 in the case of the Model.\r
                                 // We need a nice way to detect this.\r
   msr    scr_el3, x0            // Write back our settings\r
\r
   msr    cptr_el3, xzr          // Disable copro traps to EL3\r
\r
   // Check for the primary CPU to avoid a race on the distributor registers.\r
   mrs     x0, mpidr_el1\r
   tst     x0, #15\r
   b.ne    1f                              // secondary CPU\r
\r
   LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)\r
   mov     w0, #3                          // EnableGrp0 | EnableGrp1\r
   str     w0, [x1]\r
\r
1: LoadConstantToReg (FixedPcdGet32(PcdGicDistributorBase), x1)\r
   add     x1, x1, #0x80\r
   mov     w0, #~0                         // Grp1 interrupts\r
   str     w0, [x1], #4\r
   b.ne    2f                              // Only local interrupts for secondary CPUs\r
   str     w0, [x1], #4\r
   str     w0, [x1], #4\r
\r
2: LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)\r
   ldr     w0, [x1]\r
   mov     w0, #3                          // EnableGrp0 | EnableGrp1\r
   str     w0, [x1]\r
\r
   mov     w0, #1 << 7                     // allow NS access to GICC_PMR\r
   str     w0, [x1, #4]                    // GICC_PMR\r
\r
   ret\r
\r
// Switch from EL3 to NS-EL1\r
ASM_PFX(SwitchToNSExceptionLevel1):\r
   // Now setup our EL1. Controlled by EL2 config on Model\r
   mrs     x0, hcr_el2            // Read EL2 Hypervisor configuration Register\r
   orr     x0, x0, #(1 << 31)     // Set EL1 to be 64bit\r
\r
   // Send all interrupts to their respective Exception levels for EL2\r
   bic     x0, x0, #(1 << 3)      // Disable virtual FIQ\r
   bic     x0, x0, #(1 << 4)      // Disable virtual IRQ\r
   bic     x0, x0, #(1 << 5)      // Disable virtual SError and Abort\r
   msr     hcr_el2, x0            // Write back our settings\r
\r
   msr     cptr_el2, xzr          // Disable copro traps to EL2\r
\r
   msr     sctlr_el2, xzr\r
\r
   // Enable architected timer access\r
   mrs     x0, cnthctl_el2\r
   orr     x0, x0, #3             // Enable EL1 access to timers\r
   msr     cnthctl_el2, x0\r
\r
   mrs     x0, cntkctl_el1\r
   orr     x0, x0, #3             // EL0 access to counters\r
   msr     cntkctl_el1, x0\r
\r
   // Set ID regs\r
   mrs     x0, midr_el1\r
   mrs     x1, mpidr_el1\r
   msr     vpidr_el2, x0\r
   msr     vmpidr_el2, x1\r
\r
   ret\r
\r
\r
// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7\r
// we don't need a mode switch, just setup the Arguments and jump.\r
// x0: Monitor World EntryPoint\r
// x1: MpId\r
// x2: SecBootMode\r
// x3: Secure Monitor mode stack\r
ASM_PFX(enter_monitor_mode):\r
   mov     x4, x0                 // Swap EntryPoint and MpId registers\r
   mov     x0, x1\r
   mov     x1, x2\r
   mov     x2, x3\r
   br      x4\r
\r
// Put the address in correct ELR_ELx and do a eret.\r
// We may need to do some config before we change to another Mode.\r
ASM_PFX(return_from_exception):\r
   msr     elr_el3, x0\r
\r
   mrs     x7, spsr_el3\r
   ands    w7, w7, #0xC\r
   cmp     w7, #0xC       // EL3?\r
   b.eq    3f\r
   bl      ASM_PFX(SetupExceptionLevel3)\r
   cmp     w7, #0x8       // EL2?\r
   b.eq    2f\r
   cmp     w7, #0x4       // EL1?\r
   b.eq    1f\r
   b       dead           // We should never get here.\r
\r
1: bl      ASM_PFX(SwitchToNSExceptionLevel1)\r
2: // EL2: No more setup required.\r
3: // EL3: Not sure why we would do this.\r
   eret\r
\r
// For AArch64 we need to construct the spsr we want from individual bits and pieces.\r
ASM_PFX(copy_cpsr_into_spsr):\r
   mrs     x0, CurrentEl  // Get the current exception level we  are running at.\r
   mrs     x1, SPSel      // Which Stack are we using\r
   orr     x0, x0, x1\r
   mrs     x1, daif       // Which interrupts are enabled\r
   orr     x0, x0, x1\r
   msr     spsr_el3, x0   // Write to spsr\r
   ret\r
\r
// Get this from platform file.\r
ASM_PFX(set_non_secure_mode):\r
   msr     spsr_el3, x0\r
   ret\r
\r
dead:\r
   b       dead\r
\r
ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r
Commit	Line	Data
1bc83266 HL	1	#========================================================================================\r
	2	# Copyright (c) 2011-2013, ARM Limited. All rights reserved.\r
	3	#\r
	4	# This program and the accompanying materials\r
	5	# are licensed and made available under the terms and conditions of the BSD License\r
	6	# which accompanies this distribution. The full text of the license may be found at\r
	7	# http:#opensource.org/licenses/bsd-license.php\r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	#=======================================================================================\r
	13	\r
	14	#include <AsmMacroIoLibV8.h>\r
	15	#include <Chipset/AArch64.h>\r
	16	\r
	17	#start of the code section\r
	18	.text\r
	19	.align 3\r
	20	\r
	21	ASM_GLOBAL ASM_PFX(SetupExceptionLevel3)\r
	22	ASM_GLOBAL ASM_PFX(SwitchToNSExceptionLevel1)\r
	23	ASM_GLOBAL ASM_PFX(enter_monitor_mode)\r
	24	ASM_GLOBAL ASM_PFX(return_from_exception)\r
	25	ASM_GLOBAL ASM_PFX(copy_cpsr_into_spsr)\r
	26	ASM_GLOBAL ASM_PFX(set_non_secure_mode)\r
	27	\r
	28	ASM_PFX(SetupExceptionLevel3):\r
	29	mrs x0, scr_el3 // Read EL3 Secure Configuration Register\r
	30	orr x0, x0, #1 // EL0 an EL1 cannot access secure memory\r
	31	\r
	32	// Send all interrupts to their respective Exception levels for EL3\r
	33	bic x0, x0, #(1 << 1) // IRQ\r
	34	bic x0, x0, #(1 << 2) // FIQ\r
	35	bic x0, x0, #(1 << 3) // Serror and Abort\r
	36	orr x0, x0, #(1 << 8) // Enable HVC\r
	37	orr x0, x0, #(1 << 10) // Make next level down 64Bit. This is EL2 in the case of the Model.\r
	38	// We need a nice way to detect this.\r
	39	msr scr_el3, x0 // Write back our settings\r
	40	\r
	41	msr cptr_el3, xzr // Disable copro traps to EL3\r
	42	\r
	43	// Check for the primary CPU to avoid a race on the distributor registers.\r
	44	mrs x0, mpidr_el1\r
	45	tst x0, #15\r
	46	b.ne 1f // secondary CPU\r
	47	\r
	48	LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)\r
	49	mov w0, #3 // EnableGrp0 \| EnableGrp1\r
	50	str w0, [x1]\r
	51	\r
	52	1: LoadConstantToReg (FixedPcdGet32(PcdGicDistributorBase), x1)\r
	53	add x1, x1, #0x80\r
	54	mov w0, #~0 // Grp1 interrupts\r
	55	str w0, [x1], #4\r
	56	b.ne 2f // Only local interrupts for secondary CPUs\r
	57	str w0, [x1], #4\r
	58	str w0, [x1], #4\r
	59	\r
	60	2: LoadConstantToReg (FixedPcdGet32(PcdGicInterruptInterfaceBase), x1)\r
	61	ldr w0, [x1]\r
	62	mov w0, #3 // EnableGrp0 \| EnableGrp1\r
	63	str w0, [x1]\r
	64	\r
65	mov w0, #1 << 7 // allow NS access to GICC_PMR\r
66	str w0, [x1, #4] // GICC_PMR\r
67	\r
68	ret\r
69	\r
70	// Switch from EL3 to NS-EL1\r
71	ASM_PFX(SwitchToNSExceptionLevel1):\r
72	// Now setup our EL1. Controlled by EL2 config on Model\r
73	mrs x0, hcr_el2 // Read EL2 Hypervisor configuration Register\r
74	orr x0, x0, #(1 << 31) // Set EL1 to be 64bit\r
75	\r
76	// Send all interrupts to their respective Exception levels for EL2\r
77	bic x0, x0, #(1 << 3) // Disable virtual FIQ\r
78	bic x0, x0, #(1 << 4) // Disable virtual IRQ\r
79	bic x0, x0, #(1 << 5) // Disable virtual SError and Abort\r
80	msr hcr_el2, x0 // Write back our settings\r
81	\r
82	msr cptr_el2, xzr // Disable copro traps to EL2\r
83	\r
84	msr sctlr_el2, xzr\r
85	\r
86	// Enable architected timer access\r
87	mrs x0, cnthctl_el2\r
88	orr x0, x0, #3 // Enable EL1 access to timers\r
89	msr cnthctl_el2, x0\r
90	\r
91	mrs x0, cntkctl_el1\r
92	orr x0, x0, #3 // EL0 access to counters\r
93	msr cntkctl_el1, x0\r
94	\r
95	// Set ID regs\r
96	mrs x0, midr_el1\r
97	mrs x1, mpidr_el1\r
98	msr vpidr_el2, x0\r
99	msr vmpidr_el2, x1\r
100	\r
101	ret\r
102	\r
103	\r
104	// EL3 on AArch64 is Secure/monitor so this funtion is reduced vs ARMv7\r
105	// we don't need a mode switch, just setup the Arguments and jump.\r
106	// x0: Monitor World EntryPoint\r
107	// x1: MpId\r
108	// x2: SecBootMode\r
109	// x3: Secure Monitor mode stack\r
110	ASM_PFX(enter_monitor_mode):\r
111	mov x4, x0 // Swap EntryPoint and MpId registers\r
112	mov x0, x1\r
113	mov x1, x2\r
114	mov x2, x3\r
115	br x4\r
116	\r
117	// Put the address in correct ELR_ELx and do a eret.\r
118	// We may need to do some config before we change to another Mode.\r
119	ASM_PFX(return_from_exception):\r
120	msr elr_el3, x0\r
121	\r
122	mrs x7, spsr_el3\r
123	ands w7, w7, #0xC\r
124	cmp w7, #0xC // EL3?\r
125	b.eq 3f\r
126	bl ASM_PFX(SetupExceptionLevel3)\r
127	cmp w7, #0x8 // EL2?\r
128	b.eq 2f\r
129	cmp w7, #0x4 // EL1?\r
130	b.eq 1f\r
131	b dead // We should never get here.\r
132	\r
133	1: bl ASM_PFX(SwitchToNSExceptionLevel1)\r
134	2: // EL2: No more setup required.\r
135	3: // EL3: Not sure why we would do this.\r
136	eret\r
137	\r
138	// For AArch64 we need to construct the spsr we want from individual bits and pieces.\r
139	ASM_PFX(copy_cpsr_into_spsr):\r
140	mrs x0, CurrentEl // Get the current exception level we are running at.\r
141	mrs x1, SPSel // Which Stack are we using\r
142	orr x0, x0, x1\r
143	mrs x1, daif // Which interrupts are enabled\r
144	orr x0, x0, x1\r
145	msr spsr_el3, x0 // Write to spsr\r
146	ret\r
147	\r
148	// Get this from platform file.\r
149	ASM_PFX(set_non_secure_mode):\r
150	msr spsr_el3, x0\r
151	ret\r
152	\r
153	dead:\r
154	b dead\r
155	\r
156	ASM_FUNCTION_REMOVE_IF_UNREFERENCED\r