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2ef2b01e A |
1 | #------------------------------------------------------------------------------ \r |
2 | #\r | |
1ebd6c11 | 3 | # Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
2ef2b01e | 4 | #\r |
1ebd6c11 | 5 | # This program and the accompanying materials\r |
2ef2b01e A |
6 | # are licensed and made available under the terms and conditions of the BSD License\r |
7 | # which accompanies this distribution. The full text of the license may be found at\r | |
8 | # http://opensource.org/licenses/bsd-license.php\r | |
9 | #\r | |
10 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | #\r | |
13 | #------------------------------------------------------------------------------\r | |
14 | \r | |
15 | #include <AsmMacroIoLib.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | \r | |
18 | .text\r | |
19 | .align 3\r | |
20 | \r | |
21 | .globl ASM_PFX(CEntryPoint)\r | |
6111eb85 | 22 | GCC_ASM_EXPORT(_ModuleEntryPoint)\r |
2ef2b01e A |
23 | \r |
24 | ASM_PFX(_ModuleEntryPoint):\r | |
25 | \r | |
26 | //Disable L2 cache\r | |
27 | mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register\r | |
28 | bic r0, r0, #0x00000002 // disable L2 cache\r | |
29 | mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register\r | |
30 | \r | |
31 | //Enable Strict alignment checking & Instruction cache\r | |
32 | mrc p15, 0, r0, c1, c0, 0\r | |
33 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */\r | |
34 | bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */\r | |
35 | orr r0, r0, #0x00000002 /* set bit 1 (A) Align */\r | |
36 | orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */\r | |
37 | mcr p15, 0, r0, c1, c0, 0\r | |
2ed3c9cc | 38 | \r |
39 | // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r | |
40 | mrc p15, 0, r0, c1, c0, 2\r | |
41 | orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)\r | |
42 | mcr p15, 0, r0, c1, c0, 2\r | |
43 | mov r0, #0x40000000 // Set EN bit in FPEXC\r | |
44 | mcr p10,#0x7,r0,c8,c0,#0 // msr FPEXC,r0 in ARM assembly\r | |
45 | \r | |
97e9818a | 46 | \r |
2ef2b01e | 47 | // Set CPU vectors to start of DRAM\r |
bff4e9ea | 48 | LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r |
2ef2b01e | 49 | mcr p15, 0, r0, c12, c0, 0\r |
4951b248 | 50 | isb // Sync changes to control registers\r |
51 | \r | |
bff4e9ea | 52 | // Fill vector table with branchs to current pc (jmp $)\r |
53 | ldr r1, ShouldNeverGetHere\r | |
54 | movs r2, #0\r | |
55 | FillVectors:\r | |
56 | str r1, [r0, r2]\r | |
57 | adds r2, r2, #4\r | |
58 | cmp r2, #32\r | |
59 | bne FillVectors\r | |
60 | \r | |
61 | /* before we call C code, lets setup the stack pointer in internal RAM */\r | |
2ef2b01e A |
62 | stack_pointer_setup:\r |
63 | \r | |
64 | //\r | |
65 | // Set stack based on PCD values. Need to do it this way to make C code work \r | |
66 | // when it runs from FLASH. \r | |
67 | // \r | |
68 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) /* stack base arg2 */\r | |
69 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) /* stack size arg3 */\r | |
70 | add r4, r2, r3\r | |
71 | \r | |
2ef2b01e A |
72 | //Enter SVC mode and set up SVC stack pointer\r |
73 | mov r0,#0x13|0x80|0x40\r | |
74 | msr CPSR_c,r0\r | |
2ef2b01e A |
75 | mov r13,r4\r |
76 | \r | |
77 | // Call C entry point\r | |
753816a3 | 78 | LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) /* memory size arg1 */\r |
79 | LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) /* memory size arg0 */\r | |
97e9818a | 80 | blx ASM_PFX(CEntryPoint) /* Assume C code is thumb */\r |
2ef2b01e A |
81 | \r |
82 | ShouldNeverGetHere:\r | |
83 | /* _CEntryPoint should never return */\r | |
84 | b ShouldNeverGetHere\r | |
2ef2b01e | 85 | \r |