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2ef2b01e A |
1 | //------------------------------------------------------------------------------ \r |
2 | //\r | |
1ebd6c11 | 3 | // Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
2ef2b01e | 4 | //\r |
1ebd6c11 | 5 | // This program and the accompanying materials\r |
2ef2b01e A |
6 | // are licensed and made available under the terms and conditions of the BSD License\r |
7 | // which accompanies this distribution. The full text of the license may be found at\r | |
8 | // http://opensource.org/licenses/bsd-license.php\r | |
9 | //\r | |
10 | // THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | // WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | //\r | |
13 | //------------------------------------------------------------------------------\r | |
14 | \r | |
15 | #include <AsmMacroIoLib.h>\r | |
16 | #include <Library/PcdLib.h>\r | |
17 | #include <AutoGen.h>\r | |
18 | INCLUDE AsmMacroIoLib.inc\r | |
19 | \r | |
20 | IMPORT CEntryPoint\r | |
21 | EXPORT _ModuleEntryPoint\r | |
22 | \r | |
23 | PRESERVE8\r | |
24 | AREA ModuleEntryPoint, CODE, READONLY\r | |
25 | \r | |
26 | \r | |
27 | _ModuleEntryPoint\r | |
28 | \r | |
29 | //Disable L2 cache\r | |
30 | mrc p15, 0, r0, c1, c0, 1 // read Auxiliary Control Register\r | |
31 | bic r0, r0, #0x00000002 // disable L2 cache\r | |
32 | mcr p15, 0, r0, c1, c0, 1 // store Auxiliary Control Register\r | |
33 | \r | |
34 | //Enable Strict alignment checking & Instruction cache\r | |
35 | mrc p15, 0, r0, c1, c0, 0\r | |
36 | bic r0, r0, #0x00002300 /* clear bits 13, 9:8 (--V- --RS) */\r | |
37 | bic r0, r0, #0x00000005 /* clear bits 0, 2 (---- -C-M) */\r | |
38 | orr r0, r0, #0x00000002 /* set bit 1 (A) Align */\r | |
39 | orr r0, r0, #0x00001000 /* set bit 12 (I) enable I-Cache */\r | |
40 | mcr p15, 0, r0, c1, c0, 0\r | |
41 | \r | |
2ed3c9cc | 42 | // Enable NEON register in case folks want to use them for optimizations (CopyMem)\r |
43 | mrc p15, 0, r0, c1, c0, 2\r | |
44 | orr r0, r0, #0x00f00000 // Enable VPF access (V* instructions)\r | |
45 | mcr p15, 0, r0, c1, c0, 2\r | |
46 | mov r0, #0x40000000 // Set EN bit in FPEXC\r | |
47 | msr FPEXC,r0\r | |
48 | \r | |
2ef2b01e | 49 | // Set CPU vectors to start of DRAM\r |
0f023148 | 50 | LoadConstantToReg (FixedPcdGet32(PcdCpuVectorBaseAddress) ,r0) // Get vector base\r |
2ef2b01e | 51 | mcr p15, 0, r0, c12, c0, 0\r |
4951b248 | 52 | isb // Sync changes to control registers\r |
53 | \r | |
54 | // Fill vector table with branchs to current pc (jmp $)\r | |
55 | ldr r1, ShouldNeverGetHere\r | |
56 | movs r2, #0\r | |
57 | FillVectors\r | |
58 | str r1, [r0, r2]\r | |
59 | adds r2, r2, #4\r | |
60 | cmp r2, #32\r | |
61 | bne FillVectors\r | |
62 | \r | |
bff4e9ea | 63 | /* before we call C code, lets setup the stack pointer in internal RAM */\r |
2ef2b01e A |
64 | stack_pointer_setup\r |
65 | \r | |
66 | //\r | |
67 | // Set stack based on PCD values. Need to do it this way to make C code work \r | |
68 | // when it runs from FLASH. \r | |
69 | // \r | |
0f023148 | 70 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackBase) ,r2) // stack base arg2 \r |
71 | LoadConstantToReg (FixedPcdGet32(PcdPrePiStackSize) ,r3) // stack size arg3 \r | |
2ef2b01e A |
72 | add r4, r2, r3\r |
73 | \r | |
2ef2b01e | 74 | //Enter SVC mode and set up SVC stack pointer\r |
4951b248 | 75 | mov r5,#0x13|0x80|0x40\r |
76 | msr CPSR_c,r5\r | |
2ef2b01e A |
77 | mov r13,r4\r |
78 | \r | |
79 | // Call C entry point\r | |
0f023148 | 80 | LoadConstantToReg (FixedPcdGet32(PcdMemorySize) ,r1) // memory size arg1 \r |
81 | LoadConstantToReg (FixedPcdGet32(PcdMemoryBase) ,r0) // memory start arg0\r | |
82 | blx CEntryPoint // Assume C code is thumb \r | |
2ef2b01e A |
83 | \r |
84 | ShouldNeverGetHere\r | |
85 | /* _CEntryPoint should never return */\r | |
86 | b ShouldNeverGetHere\r | |
87 | \r | |
88 | END\r | |
89 | \r |