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3dbba770 | 1 | /** @file\r |
8e8227d1 | 2 | Internal library declaration for PCI Bus module.\r |
ead42efc | 3 | \r |
8e8227d1 | 4 | Copyright (c) 2006 - 2009, Intel Corporation\r |
ead42efc | 5 | All rights reserved. This program and the accompanying materials\r |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
3dbba770 | 13 | **/\r |
ead42efc | 14 | \r |
eeefcb9d | 15 | #ifndef _EFI_PCI_LIB_H_\r |
16 | #define _EFI_PCI_LIB_H_\r | |
ead42efc | 17 | \r |
18 | //\r | |
19 | // Mask definistions for PCD PcdPciIncompatibleDeviceSupportMask\r | |
20 | //\r | |
21 | #define PCI_INCOMPATIBLE_ACPI_RESOURCE_SUPPORT 0x01\r | |
22 | #define PCI_INCOMPATIBLE_READ_SUPPORT 0x02\r | |
23 | #define PCI_INCOMPATIBLE_WRITE_SUPPORT 0x04\r | |
24 | #define PCI_INCOMPATIBLE_REGISTER_UPDATE_SUPPORT 0x08\r | |
25 | #define PCI_INCOMPATIBLE_ACCESS_WIDTH_SUPPORT 0x0a\r | |
26 | \r | |
a43264f4 | 27 | typedef struct {\r |
28 | EFI_HANDLE Handle;\r | |
29 | } EFI_DEVICE_HANDLE_EXTENDED_DATA_PAYLOAD;\r | |
30 | \r | |
31 | typedef struct {\r | |
32 | UINT32 Bar;\r | |
33 | UINT16 DevicePathSize;\r | |
34 | UINT16 ReqResSize;\r | |
35 | UINT16 AllocResSize;\r | |
36 | UINT8 *DevicePath;\r | |
37 | UINT8 *ReqRes;\r | |
38 | UINT8 *AllocRes;\r | |
39 | } EFI_RESOURCE_ALLOC_FAILURE_ERROR_DATA_PAYLOAD;\r | |
40 | \r | |
ead42efc | 41 | \r |
57076f45 | 42 | /**\r |
8e8227d1 | 43 | Retrieve the PCI Card device BAR information via PciIo interface.\r |
44 | \r | |
45 | @param PciIoDevice PCI Card device instance.\r | |
46 | \r | |
57076f45 | 47 | **/\r |
ead42efc | 48 | VOID\r |
49 | GetBackPcCardBar (\r | |
50 | IN PCI_IO_DEVICE *PciIoDevice\r | |
ed66e1bc | 51 | );\r |
ead42efc | 52 | \r |
57076f45 | 53 | /**\r |
54 | Remove rejected pci device from specific root bridge\r | |
55 | handle.\r | |
8e8227d1 | 56 | \r |
57 | @param RootBridgeHandle Specific parent root bridge handle.\r | |
eeefcb9d | 58 | @param Bridge Bridge device instance.\r |
8e8227d1 | 59 | \r |
57076f45 | 60 | **/\r |
8e8227d1 | 61 | VOID\r |
ead42efc | 62 | RemoveRejectedPciDevices (\r |
8e8227d1 | 63 | IN EFI_HANDLE RootBridgeHandle,\r |
64 | IN PCI_IO_DEVICE *Bridge\r | |
ed66e1bc | 65 | );\r |
ead42efc | 66 | \r |
57076f45 | 67 | /**\r |
8e8227d1 | 68 | Submits the I/O and memory resource requirements for the specified PCI Host Bridge.\r |
69 | \r | |
70 | @param PciResAlloc Point to protocol instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r | |
71 | \r | |
72 | @retval EFI_SUCCESS Successfully finished resource allocation.\r | |
73 | @retval EFI_NOT_FOUND Cannot get root bridge instance.\r | |
74 | @retval EFI_OUT_OF_RESOURCES Platform failed to program the resources if no hot plug supported.\r | |
75 | @retval other Some error occurred when allocating resources for the PCI Host Bridge.\r | |
76 | \r | |
77 | @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r | |
78 | \r | |
57076f45 | 79 | **/\r |
ead42efc | 80 | EFI_STATUS\r |
81 | PciHostBridgeResourceAllocator (\r | |
82 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r | |
ed66e1bc | 83 | );\r |
ead42efc | 84 | \r |
eeefcb9d | 85 | /**\r |
8e8227d1 | 86 | Scan pci bus and assign bus number to the given PCI bus system.\r |
ead42efc | 87 | \r |
8e8227d1 | 88 | @param Bridge Bridge device instance.\r |
89 | @param StartBusNumber start point.\r | |
90 | @param SubBusNumber Point to sub bus number.\r | |
91 | @param PaddedBusRange Customized bus number.\r | |
92 | \r | |
93 | @retval EFI_SUCCESS Successfully scanned and assigned bus number.\r | |
94 | @retval other Some error occurred when scanning pci bus.\r | |
95 | \r | |
96 | @note Feature flag PcdPciBusHotplugDeviceSupport determine whether need support hotplug.\r | |
ead42efc | 97 | \r |
57076f45 | 98 | **/\r |
ead42efc | 99 | EFI_STATUS\r |
100 | PciScanBus (\r | |
101 | IN PCI_IO_DEVICE *Bridge,\r | |
102 | IN UINT8 StartBusNumber,\r | |
103 | OUT UINT8 *SubBusNumber,\r | |
104 | OUT UINT8 *PaddedBusRange\r | |
ed66e1bc | 105 | );\r |
ead42efc | 106 | \r |
eeefcb9d | 107 | /**\r |
8e8227d1 | 108 | Process Option Rom on the specified root bridge.\r |
ead42efc | 109 | \r |
8e8227d1 | 110 | @param Bridge Pci root bridge device instance.\r |
111 | \r | |
112 | @retval EFI_SUCCESS Success process.\r | |
113 | @retval other Some error occurred when processing Option Rom on the root bridge.\r | |
ead42efc | 114 | \r |
57076f45 | 115 | **/\r |
ead42efc | 116 | EFI_STATUS\r |
117 | PciRootBridgeP2CProcess (\r | |
118 | IN PCI_IO_DEVICE *Bridge\r | |
ed66e1bc | 119 | );\r |
ead42efc | 120 | \r |
57076f45 | 121 | /**\r |
8e8227d1 | 122 | Process Option Rom on the specified host bridge.\r |
123 | \r | |
124 | @param PciResAlloc Pointer to instance of EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL.\r | |
125 | \r | |
eeefcb9d | 126 | @retval EFI_SUCCESS Success process.\r |
8e8227d1 | 127 | @retval EFI_NOT_FOUND Can not find the root bridge instance.\r |
128 | @retval other Some error occurred when processing Option Rom on the host bridge.\r | |
129 | \r | |
57076f45 | 130 | **/\r |
ead42efc | 131 | EFI_STATUS\r |
132 | PciHostBridgeP2CProcess (\r | |
133 | IN EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r | |
ed66e1bc | 134 | );\r |
ead42efc | 135 | \r |
57076f45 | 136 | /**\r |
137 | This function is used to enumerate the entire host bridge\r | |
eeefcb9d | 138 | in a given platform.\r |
ead42efc | 139 | \r |
8e8227d1 | 140 | @param PciResAlloc A pointer to the PCI Host Resource Allocation protocol.\r |
ead42efc | 141 | \r |
8e8227d1 | 142 | @retval EFI_SUCCESS Successfully enumerated the host bridge.\r |
143 | @retval EFI_OUT_OF_RESOURCES No enough memory available.\r | |
144 | @retval other Some error occurred when enumerating the host bridge.\r | |
ead42efc | 145 | \r |
bcd70414 | 146 | **/\r |
ead42efc | 147 | EFI_STATUS\r |
148 | PciHostBridgeEnumerator (\r | |
149 | EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL *PciResAlloc\r | |
ed66e1bc | 150 | );\r |
ead42efc | 151 | \r |
152 | /**\r | |
153 | Read PCI configuration space through EFI_PCI_IO_PROTOCOL.\r | |
154 | \r | |
155 | @param PciIo A pointer to the EFI_PCI_O_PROTOCOL.\r | |
156 | @param Width Signifies the width of the memory operations.\r | |
ae358cb2 | 157 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
eeefcb9d | 158 | @param Count The number of unit to be read.\r |
ead42efc | 159 | @param Buffer For read operations, the destination buffer to store the results. For\r |
160 | write operations, the source buffer to write data from.\r | |
161 | \r | |
8e8227d1 | 162 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
163 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
164 | valid for the PCI configuration header of the PCI controller.\r | |
165 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
166 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r | |
ead42efc | 167 | \r |
168 | **/\r | |
169 | EFI_STATUS\r | |
170 | PciIoRead (\r | |
171 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
172 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
ae358cb2 | 173 | IN UINT32 Offset,\r |
ead42efc | 174 | IN UINTN Count,\r |
175 | IN OUT VOID *Buffer\r | |
176 | );\r | |
177 | \r | |
178 | /**\r | |
179 | Write PCI configuration space through EFI_PCI_IO_PROTOCOL.\r | |
180 | \r | |
8e8227d1 | 181 | If PCI incompatibility check is enabled, do incompatibility check.\r |
182 | \r | |
183 | @param PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
184 | @param Width Signifies the width of the memory operations.\r | |
185 | @param Offset The offset within the PCI configuration space for the PCI controller.\r | |
186 | @param Count The number of PCI configuration operations to perform.\r | |
187 | @param Buffer For read operations, the destination buffer to store the results. For write\r | |
188 | operations, the source buffer to write data from.\r | |
ead42efc | 189 | \r |
8e8227d1 | 190 | @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r |
191 | @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r | |
192 | valid for the PCI configuration header of the PCI controller.\r | |
193 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
194 | @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r | |
ead42efc | 195 | \r |
196 | **/\r | |
197 | EFI_STATUS\r | |
198 | PciIoWrite (\r | |
199 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
200 | IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r | |
ae358cb2 | 201 | IN UINT32 Offset,\r |
ead42efc | 202 | IN UINTN Count,\r |
203 | IN OUT VOID *Buffer\r | |
204 | );\r | |
205 | \r | |
206 | /**\r | |
207 | Write PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
208 | \r | |
209 | @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
210 | @param Pci A pointer to PCI_TYPE00.\r | |
211 | @param Width Signifies the width of the memory operations.\r | |
ae358cb2 | 212 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
8e8227d1 | 213 | @param Count The number of unit to be read.\r |
ead42efc | 214 | @param Buffer For read operations, the destination buffer to store the results. For\r |
215 | write operations, the source buffer to write data from.\r | |
216 | \r | |
8e8227d1 | 217 | @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r |
218 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
219 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
ead42efc | 220 | \r |
221 | **/\r | |
222 | EFI_STATUS\r | |
223 | PciRootBridgeIoWrite (\r | |
224 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r | |
225 | IN PCI_TYPE00 *Pci,\r | |
226 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
ae358cb2 | 227 | IN UINT64 Offset,\r |
ead42efc | 228 | IN UINTN Count,\r |
229 | IN OUT VOID *Buffer\r | |
230 | );\r | |
231 | \r | |
232 | /**\r | |
233 | Read PCI configuration space through EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
234 | \r | |
235 | @param PciRootBridgeIo A pointer to the EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.\r | |
236 | @param Pci A pointer to PCI_TYPE00.\r | |
237 | @param Width Signifies the width of the memory operations.\r | |
ae358cb2 | 238 | @param Offset The offset within the PCI configuration space for the PCI controller.\r |
eeefcb9d | 239 | @param Count The number of unit to be read.\r |
ead42efc | 240 | @param Buffer For read operations, the destination buffer to store the results. For\r |
241 | write operations, the source buffer to write data from.\r | |
242 | \r | |
8e8227d1 | 243 | @retval EFI_SUCCESS The data was read from or written to the PCI root bridge.\r |
244 | @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r | |
245 | @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r | |
ead42efc | 246 | \r |
247 | **/\r | |
248 | EFI_STATUS\r | |
249 | PciRootBridgeIoRead (\r | |
250 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo,\r | |
8e8227d1 | 251 | IN PCI_TYPE00 *Pci, OPTIONAL\r |
ead42efc | 252 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r |
ae358cb2 | 253 | IN UINT64 Offset,\r |
ead42efc | 254 | IN UINTN Count,\r |
255 | IN OUT VOID *Buffer\r | |
256 | );\r | |
ae358cb2 | 257 | \r |
ead42efc | 258 | #endif\r |