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Commit | Line | Data |
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cf1d4549 JY |
1 | /** @file\r |
2 | \r | |
d40965b9 | 3 | Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r |
9672cd30 | 4 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
cf1d4549 JY |
5 | \r |
6 | **/\r | |
7 | \r | |
8 | #ifndef _FSP_GLOBAL_DATA_H_\r | |
9 | #define _FSP_GLOBAL_DATA_H_\r | |
10 | \r | |
11 | #include <FspEas.h>\r | |
12 | \r | |
48249243 HZ |
13 | #define FSP_IN_API_MODE 0\r |
14 | #define FSP_IN_DISPATCH_MODE 1\r | |
5a3641bf | 15 | #define FSP_GLOBAL_DATA_VERSION 0x2\r |
a2e61f34 | 16 | \r |
cf1d4549 JY |
17 | #pragma pack(1)\r |
18 | \r | |
19 | typedef enum {\r | |
20 | TempRamInitApiIndex,\r | |
21 | FspInitApiIndex,\r | |
22 | NotifyPhaseApiIndex,\r | |
23 | FspMemoryInitApiIndex,\r | |
24 | TempRamExitApiIndex,\r | |
25 | FspSiliconInitApiIndex,\r | |
f2cdb268 | 26 | FspMultiPhaseSiInitApiIndex,\r |
48249243 | 27 | FspSmmInitApiIndex,\r |
cf1d4549 JY |
28 | FspApiIndexMax\r |
29 | } FSP_API_INDEX;\r | |
30 | \r | |
31 | typedef struct {\r | |
48249243 HZ |
32 | VOID *DataPtr;\r |
33 | UINTN MicrocodeRegionBase;\r | |
34 | UINTN MicrocodeRegionSize;\r | |
35 | UINTN CodeRegionBase;\r | |
36 | UINTN CodeRegionSize;\r | |
37 | UINTN Reserved;\r | |
cf1d4549 JY |
38 | } FSP_PLAT_DATA;\r |
39 | \r | |
111f2228 MK |
40 | #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')\r |
41 | #define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')\r | |
42 | #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF\r | |
cf1d4549 JY |
43 | \r |
44 | typedef struct {\r | |
3eca64f1 CC |
45 | UINT32 Signature;\r |
46 | UINT8 Version;\r | |
47 | UINT8 Reserved1[3];\r | |
d40965b9 TK |
48 | ///\r |
49 | /// Offset 0x08\r | |
50 | ///\r | |
3eca64f1 CC |
51 | UINTN CoreStack;\r |
52 | VOID *SmmInitUpdPtr;\r | |
d40965b9 TK |
53 | ///\r |
54 | /// IA32: Offset 0x10; X64: Offset 0x18\r | |
55 | ///\r | |
3eca64f1 CC |
56 | UINT32 StatusCode;\r |
57 | UINT8 ApiIdx;\r | |
111f2228 MK |
58 | ///\r |
59 | /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r | |
60 | ///\r | |
3eca64f1 CC |
61 | UINT8 FspMode;\r |
62 | UINT8 OnSeparateStack;\r | |
63 | UINT8 Reserved2;\r | |
64 | UINT32 NumberOfPhases;\r | |
65 | UINT32 PhasesExecuted;\r | |
66 | UINT32 Reserved3[8];\r | |
111f2228 | 67 | ///\r |
d40965b9 TK |
68 | /// IA32: Offset 0x40; X64: Offset 0x48\r |
69 | /// Start of UINTN and pointer section\r | |
3eca64f1 CC |
70 | /// All UINTN and pointer members are put in this section\r |
71 | /// for maintaining natural alignment for both IA32 and X64 builds.\r | |
d40965b9 TK |
72 | ///\r |
73 | FSP_PLAT_DATA PlatformData;\r | |
74 | VOID *TempRamInitUpdPtr;\r | |
75 | VOID *MemoryInitUpdPtr;\r | |
76 | VOID *SiliconInitUpdPtr;\r | |
77 | ///\r | |
3eca64f1 | 78 | /// IA32: Offset 0x64; X64: Offset 0x90\r |
111f2228 MK |
79 | /// To store function parameters pointer\r |
80 | /// so it can be retrieved after stack switched.\r | |
81 | ///\r | |
82 | VOID *FunctionParameterPtr;\r | |
d40965b9 TK |
83 | FSP_INFO_HEADER *FspInfoHeader;\r |
84 | VOID *UpdDataPtr;\r | |
85 | ///\r | |
86 | /// End of UINTN and pointer section\r | |
3eca64f1 CC |
87 | /// At this point, next field offset must be either *0h or *8h to\r |
88 | /// meet natural alignment requirement.\r | |
d40965b9 | 89 | ///\r |
3eca64f1 | 90 | UINT8 Reserved4[16];\r |
111f2228 MK |
91 | UINT32 PerfSig;\r |
92 | UINT16 PerfLen;\r | |
3eca64f1 | 93 | UINT16 Reserved5;\r |
111f2228 | 94 | UINT32 PerfIdx;\r |
3eca64f1 | 95 | UINT32 Reserved6;\r |
111f2228 | 96 | UINT64 PerfData[32];\r |
cf1d4549 JY |
97 | } FSP_GLOBAL_DATA;\r |
98 | \r | |
99 | #pragma pack()\r | |
100 | \r | |
101 | #endif\r |