UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm

[mirror_edk2.git] / IntelFsp2Pkg / Include / FspGlobalData.h

/** @file\r
\r
  Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _FSP_GLOBAL_DATA_H_\r
#define _FSP_GLOBAL_DATA_H_\r
\r
#include <FspEas.h>\r
\r
#define FSP_IN_API_MODE          0\r
#define FSP_IN_DISPATCH_MODE     1\r
#define FSP_GLOBAL_DATA_VERSION  0x3\r
\r
#pragma pack(1)\r
\r
typedef enum {\r
  TempRamInitApiIndex,\r
  FspInitApiIndex,\r
  NotifyPhaseApiIndex,\r
  FspMemoryInitApiIndex,\r
  TempRamExitApiIndex,\r
  FspSiliconInitApiIndex,\r
  FspMultiPhaseSiInitApiIndex,\r
  FspSmmInitApiIndex,\r
  FspMultiPhaseMemInitApiIndex,\r
  FspApiIndexMax\r
} FSP_API_INDEX;\r
\r
typedef struct  {\r
  VOID     *DataPtr;\r
  UINTN    MicrocodeRegionBase;\r
  UINTN    MicrocodeRegionSize;\r
  UINTN    CodeRegionBase;\r
  UINTN    CodeRegionSize;\r
  UINTN    Reserved;\r
} FSP_PLAT_DATA;\r
\r
#define FSP_GLOBAL_DATA_SIGNATURE        SIGNATURE_32 ('F', 'S', 'P', 'D')\r
#define FSP_PERFORMANCE_DATA_SIGNATURE   SIGNATURE_32 ('P', 'E', 'R', 'F')\r
#define FSP_PERFORMANCE_DATA_TIMER_MASK  0xFFFFFFFFFFFFFF\r
\r
typedef struct  {\r
  UINT32             Signature;\r
  UINT8              Version;\r
  UINT8              Reserved1[3];\r
  ///\r
  /// Offset 0x08\r
  ///\r
  UINTN              CoreStack;\r
  VOID               *SmmInitUpdPtr;\r
  ///\r
  /// IA32: Offset 0x10; X64: Offset 0x18\r
  ///\r
  UINT32             StatusCode;\r
  UINT8              ApiIdx;\r
  ///\r
  /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r
  ///\r
  UINT8              FspMode;\r
  UINT8              OnSeparateStack;\r
  UINT8              Reserved2;\r
  UINT32             NumberOfPhases;\r
  UINT32             PhasesExecuted;\r
  UINT32             Reserved3[8];\r
  ///\r
  /// IA32: Offset 0x40; X64: Offset 0x48\r
  /// Start of UINTN and pointer section\r
  /// All UINTN and pointer members are put in this section\r
  /// for maintaining natural alignment for both IA32 and X64 builds.\r
  ///\r
  FSP_PLAT_DATA      PlatformData;\r
  VOID               *TempRamInitUpdPtr;\r
  VOID               *MemoryInitUpdPtr;\r
  VOID               *SiliconInitUpdPtr;\r
  ///\r
  /// IA32: Offset 0x64; X64: Offset 0x90\r
  /// To store function parameters pointer\r
  /// so it can be retrieved after stack switched.\r
  ///\r
  VOID               *FunctionParameterPtr;\r
  FSP_INFO_HEADER    *FspInfoHeader;\r
  VOID               *UpdDataPtr;\r
  VOID               *FspHobListPtr;\r
  VOID               *VariableRequestParameterPtr;\r
  ///\r
  /// End of UINTN and pointer section\r
  /// At this point, next field offset must be either *0h or *8h to\r
  /// meet natural alignment requirement.\r
  ///\r
  UINT8              Reserved4[16];\r
  UINT32             PerfSig;\r
  UINT16             PerfLen;\r
  UINT16             Reserved5;\r
  UINT32             PerfIdx;\r
  UINT32             Reserved6;\r
  UINT64             PerfData[32];\r
} FSP_GLOBAL_DATA;\r
\r
#pragma pack()\r
\r
#endif\r