| | 1 | /** @file\r |
| | 2 | \r |
| | 3 | Copyright (c) 2014 - 2022, Intel Corporation. All rights reserved.<BR>\r |
| | 4 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| | 5 | \r |
| | 6 | **/\r |
| | 7 | \r |
| | 8 | #ifndef _FSP_GLOBAL_DATA_H_\r |
| | 9 | #define _FSP_GLOBAL_DATA_H_\r |
| | 10 | \r |
| | 11 | #include <FspEas.h>\r |
| | 12 | \r |
| | 13 | #define FSP_IN_API_MODE 0\r |
| | 14 | #define FSP_IN_DISPATCH_MODE 1\r |
| | 15 | #define FSP_GLOBAL_DATA_VERSION 0x3\r |
| | 16 | \r |
| | 17 | #pragma pack(1)\r |
| | 18 | \r |
| | 19 | typedef enum {\r |
| | 20 | TempRamInitApiIndex,\r |
| | 21 | FspInitApiIndex,\r |
| | 22 | NotifyPhaseApiIndex,\r |
| | 23 | FspMemoryInitApiIndex,\r |
| | 24 | TempRamExitApiIndex,\r |
| | 25 | FspSiliconInitApiIndex,\r |
| | 26 | FspMultiPhaseSiInitApiIndex,\r |
| | 27 | FspSmmInitApiIndex,\r |
| | 28 | FspMultiPhaseMemInitApiIndex,\r |
| | 29 | FspApiIndexMax\r |
| | 30 | } FSP_API_INDEX;\r |
| | 31 | \r |
| | 32 | typedef struct {\r |
| | 33 | VOID *DataPtr;\r |
| | 34 | UINTN MicrocodeRegionBase;\r |
| | 35 | UINTN MicrocodeRegionSize;\r |
| | 36 | UINTN CodeRegionBase;\r |
| | 37 | UINTN CodeRegionSize;\r |
| | 38 | UINTN Reserved;\r |
| | 39 | } FSP_PLAT_DATA;\r |
| | 40 | \r |
| | 41 | #define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')\r |
| | 42 | #define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')\r |
| | 43 | #define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF\r |
| | 44 | \r |
| | 45 | typedef struct {\r |
| | 46 | UINT32 Signature;\r |
| | 47 | UINT8 Version;\r |
| | 48 | UINT8 Reserved1[3];\r |
| | 49 | ///\r |
| | 50 | /// Offset 0x08\r |
| | 51 | ///\r |
| | 52 | UINTN CoreStack;\r |
| | 53 | VOID *SmmInitUpdPtr;\r |
| | 54 | ///\r |
| | 55 | /// IA32: Offset 0x10; X64: Offset 0x18\r |
| | 56 | ///\r |
| | 57 | UINT32 StatusCode;\r |
| | 58 | UINT8 ApiIdx;\r |
| | 59 | ///\r |
| | 60 | /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r |
| | 61 | ///\r |
| | 62 | UINT8 FspMode;\r |
| | 63 | UINT8 OnSeparateStack;\r |
| | 64 | UINT8 Reserved2;\r |
| | 65 | UINT32 NumberOfPhases;\r |
| | 66 | UINT32 PhasesExecuted;\r |
| | 67 | UINT32 Reserved3[8];\r |
| | 68 | ///\r |
| | 69 | /// IA32: Offset 0x40; X64: Offset 0x48\r |
| | 70 | /// Start of UINTN and pointer section\r |
| | 71 | /// All UINTN and pointer members are put in this section\r |
| | 72 | /// for maintaining natural alignment for both IA32 and X64 builds.\r |
| | 73 | ///\r |
| | 74 | FSP_PLAT_DATA PlatformData;\r |
| | 75 | VOID *TempRamInitUpdPtr;\r |
| | 76 | VOID *MemoryInitUpdPtr;\r |
| | 77 | VOID *SiliconInitUpdPtr;\r |
| | 78 | ///\r |
| | 79 | /// IA32: Offset 0x64; X64: Offset 0x90\r |
| | 80 | /// To store function parameters pointer\r |
| | 81 | /// so it can be retrieved after stack switched.\r |
| | 82 | ///\r |
| | 83 | VOID *FunctionParameterPtr;\r |
| | 84 | FSP_INFO_HEADER *FspInfoHeader;\r |
| | 85 | VOID *UpdDataPtr;\r |
| | 86 | VOID *FspHobListPtr;\r |
| | 87 | VOID *VariableRequestParameterPtr;\r |
| | 88 | ///\r |
| | 89 | /// End of UINTN and pointer section\r |
| | 90 | /// At this point, next field offset must be either *0h or *8h to\r |
| | 91 | /// meet natural alignment requirement.\r |
| | 92 | ///\r |
| | 93 | UINT8 Reserved4[16];\r |
| | 94 | UINT32 PerfSig;\r |
| | 95 | UINT16 PerfLen;\r |
| | 96 | UINT16 Reserved5;\r |
| | 97 | UINT32 PerfIdx;\r |
| | 98 | UINT32 Reserved6;\r |
| | 99 | UINT64 PerfData[32];\r |
| | 100 | } FSP_GLOBAL_DATA;\r |
| | 101 | \r |
| | 102 | #pragma pack()\r |
| | 103 | \r |
| | 104 | #endif\r |
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