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cf1d4549 JY |
1 | /** @file\r |
2 | Intel FSP Header File definition from Intel Firmware Support Package External\r | |
f2cdb268 | 3 | Architecture Specification v2.0 and above.\r |
cf1d4549 | 4 | \r |
4cc1458d | 5 | Copyright (c) 2014 - 2021, Intel Corporation. All rights reserved.<BR>\r |
9672cd30 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
cf1d4549 JY |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #ifndef __FSP_HEADER_FILE_H__\r | |
11 | #define __FSP_HEADER_FILE_H__\r | |
12 | \r | |
111f2228 | 13 | #define FSP_HEADER_REVISION_3 3\r |
cf1d4549 JY |
14 | \r |
15 | #define FSPE_HEADER_REVISION_1 1\r | |
16 | #define FSPP_HEADER_REVISION_1 1\r | |
17 | \r | |
18 | ///\r | |
19 | /// Fixed FSP header offset in the FSP image\r | |
20 | ///\r | |
111f2228 | 21 | #define FSP_INFO_HEADER_OFF 0x94\r |
cf1d4549 JY |
22 | \r |
23 | #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r | |
24 | \r | |
25 | #define FSP_INFO_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'H')\r | |
26 | \r | |
27 | #pragma pack(1)\r | |
28 | \r | |
29 | ///\r | |
30 | /// FSP Information Header as described in FSP v2.0 Spec section 5.1.1.\r | |
31 | ///\r | |
32 | typedef struct {\r | |
33 | ///\r | |
34 | /// Byte 0x00: Signature ('FSPH') for the FSP Information Header.\r | |
35 | ///\r | |
111f2228 | 36 | UINT32 Signature;\r |
cf1d4549 JY |
37 | ///\r |
38 | /// Byte 0x04: Length of the FSP Information Header.\r | |
39 | ///\r | |
111f2228 | 40 | UINT32 HeaderLength;\r |
cf1d4549 JY |
41 | ///\r |
42 | /// Byte 0x08: Reserved.\r | |
43 | ///\r | |
111f2228 | 44 | UINT8 Reserved1[2];\r |
cf1d4549 JY |
45 | ///\r |
46 | /// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.\r | |
4cc1458d | 47 | /// For revision v2.3 the value will be 0x23.\r |
cf1d4549 | 48 | ///\r |
111f2228 | 49 | UINT8 SpecVersion;\r |
cf1d4549 JY |
50 | ///\r |
51 | /// Byte 0x0B: Revision of the FSP Information Header.\r | |
4cc1458d | 52 | /// The Current value for this field is 0x6.\r |
cf1d4549 | 53 | ///\r |
111f2228 | 54 | UINT8 HeaderRevision;\r |
cf1d4549 JY |
55 | ///\r |
56 | /// Byte 0x0C: Revision of the FSP binary.\r | |
4cc1458d CC |
57 | /// Major.Minor.Revision.Build\r |
58 | /// If FSP HeaderRevision is <= 5, the ImageRevision can be decoded as follows:\r | |
59 | /// 7 : 0 - Build Number\r | |
60 | /// 15 : 8 - Revision\r | |
61 | /// 23 : 16 - Minor Version\r | |
62 | /// 31 : 24 - Major Version\r | |
63 | /// If FSP HeaderRevision is >= 6, ImageRevision specifies the low-order bytes of the build number and revision\r | |
64 | /// while ExtendedImageRevision specifies the high-order bytes of the build number and revision.\r | |
65 | /// 7 : 0 - Low Byte of Build Number\r | |
66 | /// 15 : 8 - Low Byte of Revision\r | |
67 | /// 23 : 16 - Minor Version\r | |
68 | /// 31 : 24 - Major Version\r | |
cf1d4549 | 69 | ///\r |
111f2228 | 70 | UINT32 ImageRevision;\r |
cf1d4549 JY |
71 | ///\r |
72 | /// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.\r | |
73 | ///\r | |
111f2228 | 74 | CHAR8 ImageId[8];\r |
cf1d4549 JY |
75 | ///\r |
76 | /// Byte 0x18: Size of the entire FSP binary.\r | |
77 | ///\r | |
111f2228 | 78 | UINT32 ImageSize;\r |
cf1d4549 JY |
79 | ///\r |
80 | /// Byte 0x1C: FSP binary preferred base address.\r | |
81 | ///\r | |
111f2228 | 82 | UINT32 ImageBase;\r |
cf1d4549 JY |
83 | ///\r |
84 | /// Byte 0x20: Attribute for the FSP binary.\r | |
85 | ///\r | |
111f2228 | 86 | UINT16 ImageAttribute;\r |
cf1d4549 JY |
87 | ///\r |
88 | /// Byte 0x22: Attributes of the FSP Component.\r | |
89 | ///\r | |
111f2228 | 90 | UINT16 ComponentAttribute;\r |
cf1d4549 JY |
91 | ///\r |
92 | /// Byte 0x24: Offset of the FSP configuration region.\r | |
93 | ///\r | |
111f2228 | 94 | UINT32 CfgRegionOffset;\r |
cf1d4549 JY |
95 | ///\r |
96 | /// Byte 0x28: Size of the FSP configuration region.\r | |
97 | ///\r | |
111f2228 | 98 | UINT32 CfgRegionSize;\r |
cf1d4549 JY |
99 | ///\r |
100 | /// Byte 0x2C: Reserved2.\r | |
101 | ///\r | |
111f2228 | 102 | UINT32 Reserved2;\r |
cf1d4549 JY |
103 | ///\r |
104 | /// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.\r | |
105 | ///\r | |
111f2228 | 106 | UINT32 TempRamInitEntryOffset;\r |
cf1d4549 JY |
107 | ///\r |
108 | /// Byte 0x34: Reserved3.\r | |
109 | ///\r | |
111f2228 | 110 | UINT32 Reserved3;\r |
cf1d4549 JY |
111 | ///\r |
112 | /// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.\r | |
113 | ///\r | |
111f2228 | 114 | UINT32 NotifyPhaseEntryOffset;\r |
cf1d4549 JY |
115 | ///\r |
116 | /// Byte 0x3C: The offset for the API to initialize the memory.\r | |
117 | ///\r | |
111f2228 | 118 | UINT32 FspMemoryInitEntryOffset;\r |
cf1d4549 JY |
119 | ///\r |
120 | /// Byte 0x40: The offset for the API to tear down temporary RAM.\r | |
121 | ///\r | |
111f2228 | 122 | UINT32 TempRamExitEntryOffset;\r |
cf1d4549 JY |
123 | ///\r |
124 | /// Byte 0x44: The offset for the API to initialize the CPU and chipset.\r | |
125 | ///\r | |
111f2228 | 126 | UINT32 FspSiliconInitEntryOffset;\r |
f2cdb268 CC |
127 | ///\r |
128 | /// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.\r | |
129 | /// This value is only valid if FSP HeaderRevision is >= 5.\r | |
130 | /// If the value is set to 0x00000000, then this API is not available in this component.\r | |
131 | ///\r | |
111f2228 | 132 | UINT32 FspMultiPhaseSiInitEntryOffset;\r |
4cc1458d CC |
133 | ///\r |
134 | /// Byte 0x4C: Extended revision of the FSP binary.\r | |
135 | /// This value is only valid if FSP HeaderRevision is >= 6.\r | |
136 | /// ExtendedImageRevision specifies the high-order byte of the revision and build number in the FSP binary revision.\r | |
137 | /// 7 : 0 - High Byte of Build Number\r | |
138 | /// 15 : 8 - High Byte of Revision\r | |
139 | /// The FSP binary build number can be decoded as follows:\r | |
140 | /// Build Number = (ExtendedImageRevision[7:0] << 8) | ImageRevision[7:0]\r | |
141 | /// Revision = (ExtendedImageRevision[15:8] << 8) | ImageRevision[15:8]\r | |
142 | /// Minor Version = ImageRevision[23:16]\r | |
143 | /// Major Version = ImageRevision[31:24]\r | |
144 | ///\r | |
111f2228 | 145 | UINT16 ExtendedImageRevision;\r |
4cc1458d CC |
146 | ///\r |
147 | /// Byte 0x4E: Reserved4.\r | |
148 | ///\r | |
111f2228 | 149 | UINT16 Reserved4;\r |
cf1d4549 JY |
150 | } FSP_INFO_HEADER;\r |
151 | \r | |
152 | ///\r | |
153 | /// Signature of the FSP Extended Header\r | |
154 | ///\r | |
155 | #define FSP_INFO_EXTENDED_HEADER_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'E')\r | |
156 | \r | |
157 | ///\r | |
158 | /// FSP Information Extended Header as described in FSP v2.0 Spec section 5.1.2.\r | |
159 | ///\r | |
160 | typedef struct {\r | |
161 | ///\r | |
162 | /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.\r | |
163 | ///\r | |
111f2228 | 164 | UINT32 Signature;\r |
cf1d4549 JY |
165 | ///\r |
166 | /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.\r | |
167 | ///\r | |
111f2228 | 168 | UINT32 Length;\r |
cf1d4549 JY |
169 | ///\r |
170 | /// Byte 0x08: FSP producer defined revision of the table.\r | |
171 | ///\r | |
111f2228 | 172 | UINT8 Revision;\r |
cf1d4549 JY |
173 | ///\r |
174 | /// Byte 0x09: Reserved for future use.\r | |
175 | ///\r | |
111f2228 | 176 | UINT8 Reserved;\r |
cf1d4549 | 177 | ///\r |
e37bb20c | 178 | /// Byte 0x0A: FSP producer identification string\r |
cf1d4549 | 179 | ///\r |
111f2228 | 180 | CHAR8 FspProducerId[6];\r |
cf1d4549 JY |
181 | ///\r |
182 | /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.\r | |
183 | ///\r | |
111f2228 | 184 | UINT32 FspProducerRevision;\r |
cf1d4549 JY |
185 | ///\r |
186 | /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.\r | |
187 | ///\r | |
111f2228 | 188 | UINT32 FspProducerDataSize;\r |
cf1d4549 JY |
189 | ///\r |
190 | /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.\r | |
191 | ///\r | |
192 | } FSP_INFO_EXTENDED_HEADER;\r | |
193 | \r | |
194 | //\r | |
195 | // A generic table search algorithm for additional tables can be implemented with a\r | |
196 | // signature search algorithm until a terminator signature 'FSPP' is found.\r | |
197 | //\r | |
111f2228 | 198 | #define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')\r |
cf1d4549 JY |
199 | #define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE\r |
200 | \r | |
201 | ///\r | |
202 | /// FSP Patch Table as described in FSP v2.0 Spec section 5.1.5.\r | |
203 | ///\r | |
204 | typedef struct {\r | |
205 | ///\r | |
206 | /// Byte 0x00: FSP Patch Table Signature "FSPP".\r | |
207 | ///\r | |
111f2228 | 208 | UINT32 Signature;\r |
cf1d4549 JY |
209 | ///\r |
210 | /// Byte 0x04: Size including the PatchData.\r | |
211 | ///\r | |
111f2228 | 212 | UINT16 HeaderLength;\r |
cf1d4549 JY |
213 | ///\r |
214 | /// Byte 0x06: Revision is set to 0x01.\r | |
215 | ///\r | |
111f2228 | 216 | UINT8 HeaderRevision;\r |
cf1d4549 JY |
217 | ///\r |
218 | /// Byte 0x07: Reserved for future use.\r | |
219 | ///\r | |
111f2228 | 220 | UINT8 Reserved;\r |
cf1d4549 JY |
221 | ///\r |
222 | /// Byte 0x08: Number of entries to Patch.\r | |
223 | ///\r | |
111f2228 | 224 | UINT32 PatchEntryNum;\r |
cf1d4549 JY |
225 | ///\r |
226 | /// Byte 0x0C: Patch Data.\r | |
227 | ///\r | |
111f2228 | 228 | // UINT32 PatchData[];\r |
cf1d4549 JY |
229 | } FSP_PATCH_TABLE;\r |
230 | \r | |
231 | #pragma pack()\r | |
232 | \r | |
111f2228 | 233 | extern EFI_GUID gFspHeaderFileGuid;\r |
cf1d4549 JY |
234 | \r |
235 | #endif\r |