EFI_STATUS\r
EFIAPI\r
WaitForNotify (\r
- IN CONST EFI_DXE_IPL_PPI *This,\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_HOB_POINTERS HobList\r
+ IN CONST EFI_DXE_IPL_PPI *This,\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_HOB_POINTERS HobList\r
);\r
\r
-CONST EFI_DXE_IPL_PPI mDxeIplPpi = {\r
+CONST EFI_DXE_IPL_PPI mDxeIplPpi = {\r
WaitForNotify\r
};\r
\r
-CONST EFI_PEI_PPI_DESCRIPTOR mInstallDxeIplPpi = {\r
+CONST EFI_PEI_PPI_DESCRIPTOR mInstallDxeIplPpi = {\r
EFI_PEI_PPI_DESCRIPTOR_PPI,\r
&gEfiDxeIplPpiGuid,\r
- (VOID *) &mDxeIplPpi\r
+ (VOID *)&mDxeIplPpi\r
};\r
\r
-CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = {\r
+CONST EFI_PEI_PPI_DESCRIPTOR gEndOfPeiSignalPpi = {\r
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
&gEfiEndOfPeiSignalPpiGuid,\r
NULL\r
};\r
\r
-CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {\r
+CONST EFI_PEI_PPI_DESCRIPTOR gFspReadyForNotifyPhasePpi = {\r
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
&gFspReadyForNotifyPhasePpiGuid,\r
NULL\r
EFI_STATUS\r
EFIAPI\r
WaitForNotify (\r
- IN CONST EFI_DXE_IPL_PPI *This,\r
- IN EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PEI_HOB_POINTERS HobList\r
+ IN CONST EFI_DXE_IPL_PPI *This,\r
+ IN EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PEI_HOB_POINTERS HobList\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP HOB is located at 0x%08X\n", HobList));\r
\r
**/\r
EFI_STATUS\r
FspNotifyPhasePeimEntryPoint (\r
- IN EFI_PEI_FILE_HANDLE FileHandle,\r
- IN CONST EFI_PEI_SERVICES **PeiServices\r
+ IN EFI_PEI_FILE_HANDLE FileHandle,\r
+ IN CONST EFI_PEI_SERVICES **PeiServices\r
)\r
{\r
- EFI_STATUS Status;\r
- VOID *OldDxeIplPpi;\r
- EFI_PEI_PPI_DESCRIPTOR *OldDescriptor;\r
+ EFI_STATUS Status;\r
+ VOID *OldDxeIplPpi;\r
+ EFI_PEI_PPI_DESCRIPTOR *OldDescriptor;\r
\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "The entry of FspNotificationPeim\n"));\r
\r
// Locate old DXE IPL PPI\r
//\r
Status = PeiServicesLocatePpi (\r
- &gEfiDxeIplPpiGuid,\r
- 0,\r
- &OldDescriptor,\r
- &OldDxeIplPpi\r
- );\r
+ &gEfiDxeIplPpiGuid,\r
+ 0,\r
+ &OldDescriptor,\r
+ &OldDxeIplPpi\r
+ );\r
ASSERT_EFI_ERROR (Status);\r
\r
//\r
\r
**/\r
UINT64\r
-FspGetExceptionHandler(\r
+FspGetExceptionHandler (\r
IN UINT64 IdtEntryTemplate\r
)\r
{\r
UINT32 Entry;\r
UINT64 ExceptionHandler;\r
- IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor;\r
- FSP_INFO_HEADER *FspInfoHeader;\r
-\r
- FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader();\r
- ExceptionHandler = IdtEntryTemplate;\r
- IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler;\r
- Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow;\r
- Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1);\r
+ IA32_IDT_GATE_DESCRIPTOR *IdtGateDescriptor;\r
+ FSP_INFO_HEADER *FspInfoHeader;\r
+\r
+ FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader ();\r
+ ExceptionHandler = IdtEntryTemplate;\r
+ IdtGateDescriptor = (IA32_IDT_GATE_DESCRIPTOR *)&ExceptionHandler;\r
+ Entry = (IdtGateDescriptor->Bits.OffsetHigh << 16) | IdtGateDescriptor->Bits.OffsetLow;\r
+ Entry = FspInfoHeader->ImageBase + FspInfoHeader->ImageSize - (~Entry + 1);\r
IdtGateDescriptor->Bits.OffsetHigh = (UINT16)(Entry >> 16);\r
IdtGateDescriptor->Bits.OffsetLow = (UINT16)Entry;\r
\r
VOID\r
EFIAPI\r
SecGetPlatformData (\r
- IN OUT FSP_GLOBAL_DATA *FspData\r
+ IN OUT FSP_GLOBAL_DATA *FspData\r
)\r
{\r
- FSP_PLAT_DATA *FspPlatformData;\r
- UINT32 TopOfCar;\r
- UINT32 *StackPtr;\r
- UINT32 DwordSize;\r
+ FSP_PLAT_DATA *FspPlatformData;\r
+ UINT32 TopOfCar;\r
+ UINT32 *StackPtr;\r
+ UINT32 DwordSize;\r
\r
FspPlatformData = &FspData->PlatformData;\r
\r
// reside in the bottom of stack, left untouched by normal stack operation.\r
//\r
\r
- FspPlatformData->DataPtr = NULL;\r
+ FspPlatformData->DataPtr = NULL;\r
FspPlatformData->MicrocodeRegionBase = 0;\r
FspPlatformData->MicrocodeRegionSize = 0;\r
FspPlatformData->CodeRegionBase = 0;\r
//\r
// Pointer to the size field\r
//\r
- TopOfCar = PcdGet32(PcdTemporaryRamBase) + PcdGet32(PcdTemporaryRamSize);\r
+ TopOfCar = PcdGet32 (PcdTemporaryRamBase) + PcdGet32 (PcdTemporaryRamSize);\r
StackPtr = (UINT32 *)(TopOfCar - sizeof (UINT32));\r
\r
if (*(StackPtr - 1) == FSP_MCUD_SIGNATURE) {\r
**/\r
VOID\r
FspGlobalDataInit (\r
- IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
- IN UINT32 BootLoaderStack,\r
- IN UINT8 ApiIdx\r
+ IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
+ IN UINT32 BootLoaderStack,\r
+ IN UINT8 ApiIdx\r
)\r
{\r
- VOID *FspmUpdDataPtr;\r
- CHAR8 ImageId[9];\r
- UINTN Idx;\r
+ VOID *FspmUpdDataPtr;\r
+ CHAR8 ImageId[9];\r
+ UINTN Idx;\r
\r
//\r
// Set FSP Global Data pointer\r
//\r
- SetFspGlobalDataPointer (PeiFspData);\r
- ZeroMem ((VOID *)PeiFspData, sizeof(FSP_GLOBAL_DATA));\r
+ SetFspGlobalDataPointer (PeiFspData);\r
+ ZeroMem ((VOID *)PeiFspData, sizeof (FSP_GLOBAL_DATA));\r
\r
- PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;\r
- PeiFspData->Version = 0;\r
- PeiFspData->CoreStack = BootLoaderStack;\r
- PeiFspData->PerfIdx = 2;\r
- PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;\r
+ PeiFspData->Signature = FSP_GLOBAL_DATA_SIGNATURE;\r
+ PeiFspData->Version = 0;\r
+ PeiFspData->CoreStack = BootLoaderStack;\r
+ PeiFspData->PerfIdx = 2;\r
+ PeiFspData->PerfSig = FSP_PERFORMANCE_DATA_SIGNATURE;\r
\r
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY);\r
\r
// Get FSP Header offset\r
// It may have multiple FVs, so look into the last one for FSP header\r
//\r
- PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader();\r
+ PeiFspData->FspInfoHeader = (FSP_INFO_HEADER *)AsmGetFspInfoHeader ();\r
SecGetPlatformData (PeiFspData);\r
\r
//\r
//\r
// Set UPD pointer\r
//\r
- FspmUpdDataPtr = (VOID *) GetFspApiParameter ();\r
+ FspmUpdDataPtr = (VOID *)GetFspApiParameter ();\r
if (FspmUpdDataPtr == NULL) {\r
FspmUpdDataPtr = (VOID *)(PeiFspData->FspInfoHeader->ImageBase + PeiFspData->FspInfoHeader->CfgRegionOffset);\r
}\r
+\r
SetFspUpdDataPointer (FspmUpdDataPtr);\r
SetFspMemoryInitUpdDataPointer (FspmUpdDataPtr);\r
SetFspSiliconInitUpdDataPointer (NULL);\r
for (Idx = 0; Idx < 8; Idx++) {\r
ImageId[Idx] = PeiFspData->FspInfoHeader->ImageId[Idx];\r
}\r
+\r
ImageId[Idx] = 0;\r
\r
- DEBUG ((DEBUG_INFO | DEBUG_INIT, "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \\r
- (PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \\r
- PeiFspData->FspInfoHeader->SpecVersion & 0xF, \\r
- PeiFspData->FspInfoHeader->HeaderRevision, \\r
- ImageId, \\r
- (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \\r
- (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \\r
- (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \\r
- PeiFspData->FspInfoHeader->ImageRevision & 0xFF));\r
+ DEBUG ((\r
+ DEBUG_INFO | DEBUG_INIT,\r
+ "\n============= FSP Spec v%d.%d Header Revision v%x (%a v%x.%x.%x.%x) =============\n", \\r
+ (PeiFspData->FspInfoHeader->SpecVersion >> 4) & 0xF, \\r
+ PeiFspData->FspInfoHeader->SpecVersion & 0xF, \\r
+ PeiFspData->FspInfoHeader->HeaderRevision, \\r
+ ImageId, \\r
+ (PeiFspData->FspInfoHeader->ImageRevision >> 24) & 0xFF, \\r
+ (PeiFspData->FspInfoHeader->ImageRevision >> 16) & 0xFF, \\r
+ (PeiFspData->FspInfoHeader->ImageRevision >> 8) & 0xFF, \\r
+ PeiFspData->FspInfoHeader->ImageRevision & 0xFF\r
+ ));\r
}\r
\r
/**\r
**/\r
VOID\r
FspDataPointerFixUp (\r
- IN UINT32 OffsetGap\r
+ IN UINT32 OffsetGap\r
)\r
{\r
FSP_GLOBAL_DATA *NewFspData;\r
\r
- NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer() + (UINTN)OffsetGap);\r
+ NewFspData = (FSP_GLOBAL_DATA *)((UINTN)GetFspGlobalDataPointer () + (UINTN)OffsetGap);\r
SetFspGlobalDataPointer (NewFspData);\r
}\r
\r
**/\r
UINT64\r
-FspGetExceptionHandler(\r
+FspGetExceptionHandler (\r
IN UINT64 IdtEntryTemplate\r
);\r
\r
**/\r
VOID\r
FspGlobalDataInit (\r
- IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
- IN UINT32 BootLoaderStack,\r
- IN UINT8 ApiIdx\r
+ IN OUT FSP_GLOBAL_DATA *PeiFspData,\r
+ IN UINT32 BootLoaderStack,\r
+ IN UINT8 ApiIdx\r
);\r
\r
-\r
/**\r
\r
Adjust the FSP data pointers after the stack is migrated to memory.\r
**/\r
VOID\r
FspDataPointerFixUp (\r
- IN UINT32 OffsetGap\r
+ IN UINT32 OffsetGap\r
);\r
\r
-\r
/**\r
This interface returns the base address of FSP binary.\r
\r
\r
#include "SecFsp.h"\r
\r
-\r
/**\r
This function check the FSP API calling condition.\r
\r
EFI_STATUS\r
EFIAPI\r
FspApiCallingCheck (\r
- IN UINT8 ApiIdx,\r
- IN VOID *ApiParam\r
+ IN UINT8 ApiIdx,\r
+ IN VOID *ApiParam\r
)\r
{\r
- EFI_STATUS Status;\r
- FSP_GLOBAL_DATA *FspData;\r
+ EFI_STATUS Status;\r
+ FSP_GLOBAL_DATA *FspData;\r
\r
- Status = EFI_SUCCESS;\r
+ Status = EFI_SUCCESS;\r
FspData = GetFspGlobalDataPointer ();\r
\r
if (ApiIdx == NotifyPhaseApiIndex) {\r
#include "SecMain.h"\r
#include "SecFsp.h"\r
\r
-EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {\r
+EFI_PEI_TEMPORARY_RAM_SUPPORT_PPI gSecTemporaryRamSupportPpi = {\r
SecTemporaryRamSupport\r
};\r
\r
-EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {\r
+EFI_PEI_PPI_DESCRIPTOR mPeiSecPlatformInformationPpi[] = {\r
{\r
EFI_PEI_PPI_DESCRIPTOR_PPI,\r
&gFspInApiModePpiGuid,\r
VOID\r
EFIAPI\r
SecStartup (\r
- IN UINT32 SizeOfRam,\r
- IN UINT32 TempRamBase,\r
- IN VOID *BootFirmwareVolume,\r
- IN PEI_CORE_ENTRY PeiCore,\r
- IN UINT32 BootLoaderStack,\r
- IN UINT32 ApiIdx\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume,\r
+ IN PEI_CORE_ENTRY PeiCore,\r
+ IN UINT32 BootLoaderStack,\r
+ IN UINT32 ApiIdx\r
)\r
{\r
- EFI_SEC_PEI_HAND_OFF SecCoreData;\r
- IA32_DESCRIPTOR IdtDescriptor;\r
- SEC_IDT_TABLE IdtTableInStack;\r
- UINT32 Index;\r
- FSP_GLOBAL_DATA PeiFspData;\r
- UINT64 ExceptionHandler;\r
- UINTN IdtSize;\r
+ EFI_SEC_PEI_HAND_OFF SecCoreData;\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ SEC_IDT_TABLE IdtTableInStack;\r
+ UINT32 Index;\r
+ FSP_GLOBAL_DATA PeiFspData;\r
+ UINT64 ExceptionHandler;\r
+ UINTN IdtSize;\r
\r
//\r
// Process all libraries constructor function linked to SecCore.\r
IdtTableInStack.PeiService = 0;\r
AsmReadIdtr (&IdtDescriptor);\r
if (IdtDescriptor.Base == 0) {\r
- ExceptionHandler = FspGetExceptionHandler(mIdtEntryTemplate);\r
- for (Index = 0; Index < FixedPcdGet8(PcdFspMaxInterruptSupported); Index ++) {\r
- CopyMem ((VOID*)&IdtTableInStack.IdtTable[Index], (VOID*)&ExceptionHandler, sizeof (UINT64));\r
+ ExceptionHandler = FspGetExceptionHandler (mIdtEntryTemplate);\r
+ for (Index = 0; Index < FixedPcdGet8 (PcdFspMaxInterruptSupported); Index++) {\r
+ CopyMem ((VOID *)&IdtTableInStack.IdtTable[Index], (VOID *)&ExceptionHandler, sizeof (UINT64));\r
}\r
+\r
IdtSize = sizeof (IdtTableInStack.IdtTable);\r
} else {\r
IdtSize = IdtDescriptor.Limit + 1;\r
//\r
// ERROR: IDT table size from boot loader is larger than FSP can support, DeadLoop here!\r
//\r
- CpuDeadLoop();\r
+ CpuDeadLoop ();\r
} else {\r
- CopyMem ((VOID *) (UINTN) &IdtTableInStack.IdtTable, (VOID *) IdtDescriptor.Base, IdtSize);\r
+ CopyMem ((VOID *)(UINTN)&IdtTableInStack.IdtTable, (VOID *)IdtDescriptor.Base, IdtSize);\r
}\r
}\r
- IdtDescriptor.Base = (UINTN) &IdtTableInStack.IdtTable;\r
+\r
+ IdtDescriptor.Base = (UINTN)&IdtTableInStack.IdtTable;\r
IdtDescriptor.Limit = (UINT16)(IdtSize - 1);\r
\r
AsmWriteIdtr (&IdtDescriptor);\r
// Support FSP reserved temporary memory from the whole temporary memory provided by bootloader.\r
// FSP reserved temporary memory will not be given to PeiCore.\r
//\r
- SecCoreData.TemporaryRamBase = (UINT8 *)(UINTN) TempRamBase + PcdGet32 (PcdFspPrivateTemporaryRamSize);\r
- SecCoreData.TemporaryRamSize = SizeOfRam - PcdGet32 (PcdFspPrivateTemporaryRamSize);\r
+ SecCoreData.TemporaryRamBase = (UINT8 *)(UINTN)TempRamBase + PcdGet32 (PcdFspPrivateTemporaryRamSize);\r
+ SecCoreData.TemporaryRamSize = SizeOfRam - PcdGet32 (PcdFspPrivateTemporaryRamSize);\r
if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {\r
- SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize;\r
- SecCoreData.StackBase = (VOID *)GetFspEntryStack(); // Share the same boot loader stack\r
- SecCoreData.StackSize = 0;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize;\r
+ SecCoreData.StackBase = (VOID *)GetFspEntryStack (); // Share the same boot loader stack\r
+ SecCoreData.StackSize = 0;\r
} else {\r
- SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
- SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;\r
- SecCoreData.StackBase = (VOID*)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
- SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
+ SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
+ SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize * PcdGet8 (PcdFspHeapSizePercentage) / 100;\r
+ SecCoreData.StackBase = (VOID *)(UINTN)((UINTN)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize);\r
+ SecCoreData.StackSize = SecCoreData.TemporaryRamSize - SecCoreData.PeiTemporaryRamSize;\r
}\r
\r
DEBUG ((DEBUG_INFO, "Fsp BootFirmwareVolumeBase - 0x%x\n", SecCoreData.BootFirmwareVolumeBase));\r
EFI_STATUS\r
EFIAPI\r
SecTemporaryRamSupport (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
- IN UINTN CopySize\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
)\r
{\r
- IA32_DESCRIPTOR IdtDescriptor;\r
- VOID* OldHeap;\r
- VOID* NewHeap;\r
- VOID* OldStack;\r
- VOID* NewStack;\r
- UINTN HeapSize;\r
- UINTN StackSize;\r
+ IA32_DESCRIPTOR IdtDescriptor;\r
+ VOID *OldHeap;\r
+ VOID *NewHeap;\r
+ VOID *OldStack;\r
+ VOID *NewStack;\r
+ UINTN HeapSize;\r
+ UINTN StackSize;\r
\r
- UINTN CurrentStack;\r
- UINTN FspStackBase;\r
+ UINTN CurrentStack;\r
+ UINTN FspStackBase;\r
\r
//\r
// Override OnSeparateStack to 1 because this function will switch stack to permanent memory\r
GetFspGlobalDataPointer ()->OnSeparateStack = 1;\r
\r
if (PcdGet8 (PcdFspHeapSizePercentage) == 0) {\r
-\r
- CurrentStack = AsmReadEsp();\r
- FspStackBase = (UINTN)GetFspEntryStack();\r
+ CurrentStack = AsmReadEsp ();\r
+ FspStackBase = (UINTN)GetFspEntryStack ();\r
\r
StackSize = FspStackBase - CurrentStack;\r
HeapSize = CopySize;\r
\r
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase);\r
+ OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;\r
+ NewHeap = (VOID *)((UINTN)PermanentMemoryBase);\r
\r
- OldStack = (VOID*)CurrentStack;\r
+ OldStack = (VOID *)CurrentStack;\r
//\r
- //The old stack is copied at the end of the stack region because stack grows down.\r
+ // The old stack is copied at the end of the stack region because stack grows down.\r
//\r
- NewStack = (VOID*)((UINTN)PermanentMemoryBase - StackSize);\r
-\r
+ NewStack = (VOID *)((UINTN)PermanentMemoryBase - StackSize);\r
} else {\r
- HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100 ;\r
- StackSize = CopySize - HeapSize;\r
+ HeapSize = CopySize * PcdGet8 (PcdFspHeapSizePercentage) / 100;\r
+ StackSize = CopySize - HeapSize;\r
\r
- OldHeap = (VOID*)(UINTN)TemporaryMemoryBase;\r
- NewHeap = (VOID*)((UINTN)PermanentMemoryBase + StackSize);\r
-\r
- OldStack = (VOID*)((UINTN)TemporaryMemoryBase + HeapSize);\r
- NewStack = (VOID*)(UINTN)PermanentMemoryBase;\r
+ OldHeap = (VOID *)(UINTN)TemporaryMemoryBase;\r
+ NewHeap = (VOID *)((UINTN)PermanentMemoryBase + StackSize);\r
\r
+ OldStack = (VOID *)((UINTN)TemporaryMemoryBase + HeapSize);\r
+ NewStack = (VOID *)(UINTN)PermanentMemoryBase;\r
}\r
+\r
//\r
// Migrate Heap\r
//\r
//\r
CopyMem (NewStack, OldStack, StackSize);\r
\r
-\r
//\r
// We need *not* fix the return address because currently,\r
// The PeiCore is executed in flash.\r
// permanent memory.\r
//\r
SecSwitchStack (\r
- (UINT32) (UINTN) OldStack,\r
- (UINT32) (UINTN) NewStack\r
+ (UINT32)(UINTN)OldStack,\r
+ (UINT32)(UINTN)NewStack\r
);\r
\r
return EFI_SUCCESS;\r
#ifndef _SEC_CORE_H_\r
#define _SEC_CORE_H_\r
\r
-\r
#include <PiPei.h>\r
#include <Ppi/TemporaryRamSupport.h>\r
\r
typedef VOID (*PEI_CORE_ENTRY) ( \\r
IN CONST EFI_SEC_PEI_HAND_OFF *SecCoreData, \\r
IN CONST EFI_PEI_PPI_DESCRIPTOR *PpiList \\r
-);\r
+ );\r
\r
typedef struct _SEC_IDT_TABLE {\r
//\r
// Note: For IA32, only the 4 bytes immediately preceding IDT is used to store\r
// EFI_PEI_SERVICES**\r
//\r
- UINT64 PeiService;\r
- UINT64 IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];\r
+ UINT64 PeiService;\r
+ UINT64 IdtTable[FixedPcdGet8 (PcdFspMaxInterruptSupported)];\r
} SEC_IDT_TABLE;\r
\r
/**\r
VOID\r
EFIAPI\r
SecSwitchStack (\r
- IN UINT32 TemporaryMemoryBase,\r
- IN UINT32 PermenentMemoryBase\r
+ IN UINT32 TemporaryMemoryBase,\r
+ IN UINT32 PermenentMemoryBase\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
SecTemporaryRamSupport (\r
- IN CONST EFI_PEI_SERVICES **PeiServices,\r
- IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
- IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
- IN UINTN CopySize\r
+ IN CONST EFI_PEI_SERVICES **PeiServices,\r
+ IN EFI_PHYSICAL_ADDRESS TemporaryMemoryBase,\r
+ IN EFI_PHYSICAL_ADDRESS PermanentMemoryBase,\r
+ IN UINTN CopySize\r
);\r
\r
-\r
/**\r
\r
Entry point to the C language phase of SEC. After the SEC assembly\r
VOID\r
EFIAPI\r
SecStartup (\r
- IN UINT32 SizeOfRam,\r
- IN UINT32 TempRamBase,\r
- IN VOID *BootFirmwareVolume,\r
- IN PEI_CORE_ENTRY PeiCore,\r
- IN UINT32 BootLoaderStack,\r
- IN UINT32 ApiIdx\r
+ IN UINT32 SizeOfRam,\r
+ IN UINT32 TempRamBase,\r
+ IN VOID *BootFirmwareVolume,\r
+ IN PEI_CORE_ENTRY PeiCore,\r
+ IN UINT32 BootLoaderStack,\r
+ IN UINT32 ApiIdx\r
);\r
\r
/**\r
/// FSP Reset Status code\r
/// These are defined in FSP EAS v2.0 section 11.2.2 - OEM Status Code\r
/// @{\r
-#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001\r
-#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002\r
-#define FSP_STATUS_RESET_REQUIRED_3 0x40000003\r
-#define FSP_STATUS_RESET_REQUIRED_4 0x40000004\r
-#define FSP_STATUS_RESET_REQUIRED_5 0x40000005\r
-#define FSP_STATUS_RESET_REQUIRED_6 0x40000006\r
-#define FSP_STATUS_RESET_REQUIRED_7 0x40000007\r
-#define FSP_STATUS_RESET_REQUIRED_8 0x40000008\r
+#define FSP_STATUS_RESET_REQUIRED_COLD 0x40000001\r
+#define FSP_STATUS_RESET_REQUIRED_WARM 0x40000002\r
+#define FSP_STATUS_RESET_REQUIRED_3 0x40000003\r
+#define FSP_STATUS_RESET_REQUIRED_4 0x40000004\r
+#define FSP_STATUS_RESET_REQUIRED_5 0x40000005\r
+#define FSP_STATUS_RESET_REQUIRED_6 0x40000006\r
+#define FSP_STATUS_RESET_REQUIRED_7 0x40000007\r
+#define FSP_STATUS_RESET_REQUIRED_8 0x40000008\r
/// @}\r
\r
///\r
/// FSP Event related definition.\r
///\r
-#define FSP_EVENT_CODE 0xF5000000\r
-#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)\r
+#define FSP_EVENT_CODE 0xF5000000\r
+#define FSP_POST_CODE (FSP_EVENT_CODE | 0x00F80000)\r
\r
/*\r
FSP may optionally include the capability of generating events messages to aid in the debugging of firmware issues.\r
*/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_EVENT_HANDLER) (\r
+(EFIAPI *FSP_EVENT_HANDLER)(\r
IN EFI_STATUS_CODE_TYPE Type,\r
IN EFI_STATUS_CODE_VALUE Value,\r
IN UINT32 Instance,\r
*/\r
typedef\r
UINT32\r
-(EFIAPI *FSP_DEBUG_HANDLER) (\r
- IN CHAR8* DebugMessage,\r
+(EFIAPI *FSP_DEBUG_HANDLER)(\r
+ IN CHAR8 *DebugMessage,\r
IN UINT32 MessageLength\r
);\r
\r
/// "XXXXXX_S" for FSP-S\r
/// Where XXXXXX is an unique signature\r
///\r
- UINT64 Signature;\r
+ UINT64 Signature;\r
///\r
/// Revision of the Data structure.\r
/// For FSP spec 2.0/2.1 value is 1.\r
/// For FSP spec 2.2 value is 2.\r
///\r
- UINT8 Revision;\r
- UINT8 Reserved[23];\r
+ UINT8 Revision;\r
+ UINT8 Reserved[23];\r
} FSP_UPD_HEADER;\r
\r
///\r
///\r
/// Revision Revision of the structure is 1 for this version of the specification.\r
///\r
- UINT8 Revision;\r
- UINT8 Reserved[3];\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
///\r
/// Length Length of the structure in bytes. The current value for this field is 32.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
///\r
/// FspDebugHandler Optional debug handler for the bootloader to receive debug messages\r
/// occurring during FSP execution.\r
///\r
- FSP_DEBUG_HANDLER FspDebugHandler;\r
- UINT8 Reserved1[20];\r
+ FSP_DEBUG_HANDLER FspDebugHandler;\r
+ UINT8 Reserved1[20];\r
} FSPT_ARCH_UPD;\r
\r
///\r
///\r
/// Revision of the structure. For FSP v2.0 value is 1.\r
///\r
- UINT8 Revision;\r
- UINT8 Reserved[3];\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
///\r
/// Pointer to the non-volatile storage (NVS) data buffer.\r
/// If it is NULL it indicates the NVS data is not available.\r
///\r
- VOID *NvsBufferPtr;\r
+ VOID *NvsBufferPtr;\r
///\r
/// Pointer to the temporary stack base address to be\r
/// consumed inside FspMemoryInit() API.\r
///\r
- VOID *StackBase;\r
+ VOID *StackBase;\r
///\r
/// Temporary stack size to be consumed inside\r
/// FspMemoryInit() API.\r
///\r
- UINT32 StackSize;\r
+ UINT32 StackSize;\r
///\r
/// Size of memory to be reserved by FSP below "top\r
/// of low usable memory" for bootloader usage.\r
///\r
- UINT32 BootLoaderTolumSize;\r
+ UINT32 BootLoaderTolumSize;\r
///\r
/// Current boot mode.\r
///\r
- UINT32 BootMode;\r
+ UINT32 BootMode;\r
///\r
/// Optional event handler for the bootloader to be informed of events occurring during FSP execution.\r
/// This value is only valid if Revision is >= 2.\r
///\r
- FSP_EVENT_HANDLER *FspEventHandler;\r
- UINT8 Reserved1[4];\r
+ FSP_EVENT_HANDLER *FspEventHandler;\r
+ UINT8 Reserved1[4];\r
} FSPM_ARCH_UPD;\r
\r
typedef struct {\r
///\r
/// Revision Revision of the structure is 1 for this version of the specification.\r
///\r
- UINT8 Revision;\r
- UINT8 Reserved[3];\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
///\r
/// Length Length of the structure in bytes. The current value for this field is 32.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
///\r
/// FspEventHandler Optional event handler for the bootloader to be informed of events\r
/// occurring during FSP execution.\r
///\r
- FSP_EVENT_HANDLER FspEventHandler;\r
+ FSP_EVENT_HANDLER FspEventHandler;\r
///\r
/// A FSP binary may optionally implement multi-phase silicon initialization,\r
/// This is only supported if the FspMultiPhaseSiInitEntryOffset field in FSP_INFO_HEADER\r
/// To enable multi-phase silicon initialization, the bootloader must set\r
/// EnableMultiPhaseSiliconInit to a non-zero value.\r
///\r
- UINT8 EnableMultiPhaseSiliconInit;\r
- UINT8 Reserved1[19];\r
+ UINT8 EnableMultiPhaseSiliconInit;\r
+ UINT8 Reserved1[19];\r
} FSPS_ARCH_UPD;\r
\r
///\r
///\r
/// FSP_UPD_HEADER Configuration.\r
///\r
- FSP_UPD_HEADER FspUpdHeader;\r
+ FSP_UPD_HEADER FspUpdHeader;\r
} FSPT_UPD_COMMON;\r
\r
///\r
///\r
/// FSP_UPD_HEADER Configuration.\r
///\r
- FSP_UPD_HEADER FspUpdHeader;\r
+ FSP_UPD_HEADER FspUpdHeader;\r
\r
///\r
/// FSPT_ARCH_UPD Configuration.\r
///\r
- FSPT_ARCH_UPD FsptArchUpd;\r
+ FSPT_ARCH_UPD FsptArchUpd;\r
} FSPT_UPD_COMMON_FSP22;\r
\r
///\r
///\r
/// FSP_UPD_HEADER Configuration.\r
///\r
- FSP_UPD_HEADER FspUpdHeader;\r
+ FSP_UPD_HEADER FspUpdHeader;\r
///\r
/// FSPM_ARCH_UPD Configuration.\r
///\r
- FSPM_ARCH_UPD FspmArchUpd;\r
+ FSPM_ARCH_UPD FspmArchUpd;\r
} FSPM_UPD_COMMON;\r
\r
///\r
///\r
/// FSP_UPD_HEADER Configuration.\r
///\r
- FSP_UPD_HEADER FspUpdHeader;\r
+ FSP_UPD_HEADER FspUpdHeader;\r
} FSPS_UPD_COMMON;\r
\r
///\r
///\r
/// FSP_UPD_HEADER Configuration.\r
///\r
- FSP_UPD_HEADER FspUpdHeader;\r
+ FSP_UPD_HEADER FspUpdHeader;\r
\r
///\r
/// FSPS_ARCH_UPD Configuration.\r
///\r
- FSPS_ARCH_UPD FspsArchUpd;\r
+ FSPS_ARCH_UPD FspsArchUpd;\r
} FSPS_UPD_COMMON_FSP22;\r
\r
///\r
/// This stage is notified just before the bootloader hand-off\r
/// to the OS loader.\r
///\r
- EnumInitPhaseReadyToBoot = 0x40,\r
+ EnumInitPhaseReadyToBoot = 0x40,\r
///\r
/// This stage is notified just before the firmware/Preboot\r
/// environment transfers management of all system resources\r
/// to the OS or next level execution environment.\r
///\r
- EnumInitPhaseEndOfFirmware = 0xF0\r
+ EnumInitPhaseEndOfFirmware = 0xF0\r
} FSP_INIT_PHASE;\r
\r
///\r
///\r
/// Notification phase used for NotifyPhase API\r
///\r
- FSP_INIT_PHASE Phase;\r
+ FSP_INIT_PHASE Phase;\r
} NOTIFY_PHASE_PARAMS;\r
\r
///\r
/// Action definition for FspMultiPhaseSiInit API\r
///\r
typedef enum {\r
- EnumMultiPhaseGetNumberOfPhases = 0x0,\r
- EnumMultiPhaseExecutePhase = 0x1\r
+ EnumMultiPhaseGetNumberOfPhases = 0x0,\r
+ EnumMultiPhaseExecutePhase = 0x1\r
} FSP_MULTI_PHASE_ACTION;\r
\r
///\r
/// FspMultiPhaseSiInit API with action 0 (EnumMultiPhaseGetNumberOfPhases)\r
///\r
typedef struct {\r
- UINT32 NumberOfPhases;\r
- UINT32 PhasesExecuted;\r
+ UINT32 NumberOfPhases;\r
+ UINT32 PhasesExecuted;\r
} FSP_MULTI_PHASE_GET_NUMBER_OF_PHASES_PARAMS;\r
\r
///\r
/// - MultiPhaseParamPtr shall be NULL.\r
///\r
typedef struct {\r
- IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;\r
- IN UINT32 PhaseIndex;\r
- IN OUT VOID *MultiPhaseParamPtr;\r
+ IN FSP_MULTI_PHASE_ACTION MultiPhaseAction;\r
+ IN UINT32 PhaseIndex;\r
+ IN OUT VOID *MultiPhaseParamPtr;\r
} FSP_MULTI_PHASE_PARAMS;\r
\r
#pragma pack()\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_TEMP_RAM_INIT) (\r
+(EFIAPI *FSP_TEMP_RAM_INIT)(\r
IN VOID *FsptUpdDataPtr\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_NOTIFY_PHASE) (\r
+(EFIAPI *FSP_NOTIFY_PHASE)(\r
IN NOTIFY_PHASE_PARAMS *NotifyPhaseParamPtr\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_MEMORY_INIT) (\r
+(EFIAPI *FSP_MEMORY_INIT)(\r
IN VOID *FspmUpdDataPtr,\r
OUT VOID **HobListPtr\r
);\r
\r
-\r
/**\r
This FSP API is called after FspMemoryInit API. This FSP API tears down the temporary\r
memory setup by TempRamInit API. This FSP API accepts a pointer to a data structure\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_TEMP_RAM_EXIT) (\r
+(EFIAPI *FSP_TEMP_RAM_EXIT)(\r
IN VOID *TempRamExitParamPtr\r
);\r
\r
-\r
/**\r
This FSP API is called after TempRamExit API.\r
FspMemoryInit, TempRamExit and FspSiliconInit APIs provide an alternate method to complete the\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_SILICON_INIT) (\r
+(EFIAPI *FSP_SILICON_INIT)(\r
IN VOID *FspsUpdDataPtr\r
);\r
\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_MULTI_PHASE_SI_INIT) (\r
+(EFIAPI *FSP_MULTI_PHASE_SI_INIT)(\r
IN FSP_MULTI_PHASE_PARAMS *MultiPhaseSiInitParamPtr\r
-);\r
+ );\r
\r
#endif\r
\r
#include <FspEas.h>\r
\r
-#define FSP_IN_API_MODE 0\r
-#define FSP_IN_DISPATCH_MODE 1\r
+#define FSP_IN_API_MODE 0\r
+#define FSP_IN_DISPATCH_MODE 1\r
\r
#pragma pack(1)\r
\r
} FSP_API_INDEX;\r
\r
typedef struct {\r
- VOID *DataPtr;\r
- UINT32 MicrocodeRegionBase;\r
- UINT32 MicrocodeRegionSize;\r
- UINT32 CodeRegionBase;\r
- UINT32 CodeRegionSize;\r
+ VOID *DataPtr;\r
+ UINT32 MicrocodeRegionBase;\r
+ UINT32 MicrocodeRegionSize;\r
+ UINT32 CodeRegionBase;\r
+ UINT32 CodeRegionSize;\r
} FSP_PLAT_DATA;\r
\r
-#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')\r
-#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')\r
-#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF\r
+#define FSP_GLOBAL_DATA_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'D')\r
+#define FSP_PERFORMANCE_DATA_SIGNATURE SIGNATURE_32 ('P', 'E', 'R', 'F')\r
+#define FSP_PERFORMANCE_DATA_TIMER_MASK 0xFFFFFFFFFFFFFF\r
\r
typedef struct {\r
- UINT32 Signature;\r
- UINT8 Version;\r
- UINT8 Reserved1[3];\r
- UINT32 CoreStack;\r
- UINT32 StatusCode;\r
- UINT32 Reserved2[8];\r
- FSP_PLAT_DATA PlatformData;\r
- FSP_INFO_HEADER *FspInfoHeader;\r
- VOID *UpdDataPtr;\r
- VOID *TempRamInitUpdPtr;\r
- VOID *MemoryInitUpdPtr;\r
- VOID *SiliconInitUpdPtr;\r
- UINT8 ApiIdx;\r
- ///\r
- /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r
- ///\r
- UINT8 FspMode;\r
- UINT8 OnSeparateStack;\r
- UINT8 Reserved3;\r
- UINT32 NumberOfPhases;\r
- UINT32 PhasesExecuted;\r
- ///\r
- /// To store function parameters pointer\r
- /// so it can be retrieved after stack switched.\r
- ///\r
- VOID *FunctionParameterPtr;\r
- UINT8 Reserved4[16];\r
- UINT32 PerfSig;\r
- UINT16 PerfLen;\r
- UINT16 Reserved5;\r
- UINT32 PerfIdx;\r
- UINT64 PerfData[32];\r
+ UINT32 Signature;\r
+ UINT8 Version;\r
+ UINT8 Reserved1[3];\r
+ UINT32 CoreStack;\r
+ UINT32 StatusCode;\r
+ UINT32 Reserved2[8];\r
+ FSP_PLAT_DATA PlatformData;\r
+ FSP_INFO_HEADER *FspInfoHeader;\r
+ VOID *UpdDataPtr;\r
+ VOID *TempRamInitUpdPtr;\r
+ VOID *MemoryInitUpdPtr;\r
+ VOID *SiliconInitUpdPtr;\r
+ UINT8 ApiIdx;\r
+ ///\r
+ /// 0: FSP in API mode; 1: FSP in DISPATCH mode\r
+ ///\r
+ UINT8 FspMode;\r
+ UINT8 OnSeparateStack;\r
+ UINT8 Reserved3;\r
+ UINT32 NumberOfPhases;\r
+ UINT32 PhasesExecuted;\r
+ ///\r
+ /// To store function parameters pointer\r
+ /// so it can be retrieved after stack switched.\r
+ ///\r
+ VOID *FunctionParameterPtr;\r
+ UINT8 Reserved4[16];\r
+ UINT32 PerfSig;\r
+ UINT16 PerfLen;\r
+ UINT16 Reserved5;\r
+ UINT32 PerfIdx;\r
+ UINT64 PerfData[32];\r
} FSP_GLOBAL_DATA;\r
\r
#pragma pack()\r
//\r
// 0xD0 - 0xEF are reserved for FSP common measure point\r
//\r
-#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0\r
-#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0\r
+#define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8\r
-#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8\r
+#define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA\r
-#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA\r
+#define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0\r
-#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0\r
+#define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8\r
-#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8\r
+#define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA\r
-#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_ME_INIT_ENTRY 0xEA\r
+#define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)\r
\r
//\r
// 0xF0 - 0xFF are reserved for FSP API\r
//\r
-#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0\r
-#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0\r
+#define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2\r
-#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2\r
+#define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4\r
-#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)\r
+#define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4\r
+#define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6\r
-#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)\r
+#define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6\r
+#define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8\r
-#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)\r
+#define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8\r
+#define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)\r
\r
-#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA\r
-#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)\r
+#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA\r
+#define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)\r
\r
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC\r
#define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)\r
//\r
// FSP API - 4 BITS\r
//\r
-#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000\r
-#define FSP_STATUS_CODE_MEMORY_INIT 0xD000\r
-#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000\r
-#define FSP_STATUS_CODE_SILICON_INIT 0x9000\r
-#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000\r
-#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000\r
-#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000\r
+#define FSP_STATUS_CODE_TEMP_RAM_INIT 0xF000\r
+#define FSP_STATUS_CODE_MEMORY_INIT 0xD000\r
+#define FSP_STATUS_CODE_TEMP_RAM_EXIT 0xB000\r
+#define FSP_STATUS_CODE_SILICON_INIT 0x9000\r
+#define FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION 0x6000\r
+#define FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION 0x4000\r
+#define FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION 0x2000\r
\r
//\r
// MODULE - 4 BITS\r
//\r
-#define FSP_STATUS_CODE_GFX_PEIM 0x0700\r
-#define FSP_STATUS_CODE_COMMON_CODE 0x0800\r
-#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900\r
-#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00\r
-#define FSP_STATUS_CODE_PCH 0x0B00\r
-#define FSP_STATUS_CODE_CPU 0x0C00\r
-#define FSP_STATUS_CODE_MRC 0x0D00\r
-#define FSP_STATUS_CODE_ME_BIOS 0x0E00\r
+#define FSP_STATUS_CODE_GFX_PEIM 0x0700\r
+#define FSP_STATUS_CODE_COMMON_CODE 0x0800\r
+#define FSP_STATUS_CODE_SILICON_COMMON_CODE 0x0900\r
+#define FSP_STATUS_CODE_SYSTEM_AGENT 0x0A00\r
+#define FSP_STATUS_CODE_PCH 0x0B00\r
+#define FSP_STATUS_CODE_CPU 0x0C00\r
+#define FSP_STATUS_CODE_MRC 0x0D00\r
+#define FSP_STATUS_CODE_ME_BIOS 0x0E00\r
//\r
// Individual Codes - 1 BYTE\r
//\r
-#define FSP_STATUS_CODE_API_ENTRY 0x0000\r
-#define FSP_STATUS_CODE_API_EXIT 0x007F\r
+#define FSP_STATUS_CODE_API_ENTRY 0x0000\r
+#define FSP_STATUS_CODE_API_EXIT 0x007F\r
\r
#endif\r
#ifndef __FSP_HEADER_FILE_H__\r
#define __FSP_HEADER_FILE_H__\r
\r
-#define FSP_HEADER_REVISION_3 3\r
+#define FSP_HEADER_REVISION_3 3\r
\r
#define FSPE_HEADER_REVISION_1 1\r
#define FSPP_HEADER_REVISION_1 1\r
///\r
/// Fixed FSP header offset in the FSP image\r
///\r
-#define FSP_INFO_HEADER_OFF 0x94\r
+#define FSP_INFO_HEADER_OFF 0x94\r
\r
#define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r
\r
///\r
/// Byte 0x00: Signature ('FSPH') for the FSP Information Header.\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// Byte 0x04: Length of the FSP Information Header.\r
///\r
- UINT32 HeaderLength;\r
+ UINT32 HeaderLength;\r
///\r
/// Byte 0x08: Reserved.\r
///\r
- UINT8 Reserved1[2];\r
+ UINT8 Reserved1[2];\r
///\r
/// Byte 0x0A: Indicates compliance with a revision of this specification in the BCD format.\r
/// For revision v2.3 the value will be 0x23.\r
///\r
- UINT8 SpecVersion;\r
+ UINT8 SpecVersion;\r
///\r
/// Byte 0x0B: Revision of the FSP Information Header.\r
/// The Current value for this field is 0x6.\r
///\r
- UINT8 HeaderRevision;\r
+ UINT8 HeaderRevision;\r
///\r
/// Byte 0x0C: Revision of the FSP binary.\r
/// Major.Minor.Revision.Build\r
/// 23 : 16 - Minor Version\r
/// 31 : 24 - Major Version\r
///\r
- UINT32 ImageRevision;\r
+ UINT32 ImageRevision;\r
///\r
/// Byte 0x10: Signature string that will help match the FSP Binary to a supported HW configuration.\r
///\r
- CHAR8 ImageId[8];\r
+ CHAR8 ImageId[8];\r
///\r
/// Byte 0x18: Size of the entire FSP binary.\r
///\r
- UINT32 ImageSize;\r
+ UINT32 ImageSize;\r
///\r
/// Byte 0x1C: FSP binary preferred base address.\r
///\r
- UINT32 ImageBase;\r
+ UINT32 ImageBase;\r
///\r
/// Byte 0x20: Attribute for the FSP binary.\r
///\r
- UINT16 ImageAttribute;\r
+ UINT16 ImageAttribute;\r
///\r
/// Byte 0x22: Attributes of the FSP Component.\r
///\r
- UINT16 ComponentAttribute;\r
+ UINT16 ComponentAttribute;\r
///\r
/// Byte 0x24: Offset of the FSP configuration region.\r
///\r
- UINT32 CfgRegionOffset;\r
+ UINT32 CfgRegionOffset;\r
///\r
/// Byte 0x28: Size of the FSP configuration region.\r
///\r
- UINT32 CfgRegionSize;\r
+ UINT32 CfgRegionSize;\r
///\r
/// Byte 0x2C: Reserved2.\r
///\r
- UINT32 Reserved2;\r
+ UINT32 Reserved2;\r
///\r
/// Byte 0x30: The offset for the API to setup a temporary stack till the memory is initialized.\r
///\r
- UINT32 TempRamInitEntryOffset;\r
+ UINT32 TempRamInitEntryOffset;\r
///\r
/// Byte 0x34: Reserved3.\r
///\r
- UINT32 Reserved3;\r
+ UINT32 Reserved3;\r
///\r
/// Byte 0x38: The offset for the API to inform the FSP about the different stages in the boot process.\r
///\r
- UINT32 NotifyPhaseEntryOffset;\r
+ UINT32 NotifyPhaseEntryOffset;\r
///\r
/// Byte 0x3C: The offset for the API to initialize the memory.\r
///\r
- UINT32 FspMemoryInitEntryOffset;\r
+ UINT32 FspMemoryInitEntryOffset;\r
///\r
/// Byte 0x40: The offset for the API to tear down temporary RAM.\r
///\r
- UINT32 TempRamExitEntryOffset;\r
+ UINT32 TempRamExitEntryOffset;\r
///\r
/// Byte 0x44: The offset for the API to initialize the CPU and chipset.\r
///\r
- UINT32 FspSiliconInitEntryOffset;\r
+ UINT32 FspSiliconInitEntryOffset;\r
///\r
/// Byte 0x48: Offset for the API for the optional Multi-Phase processor and chipset initialization.\r
/// This value is only valid if FSP HeaderRevision is >= 5.\r
/// If the value is set to 0x00000000, then this API is not available in this component.\r
///\r
- UINT32 FspMultiPhaseSiInitEntryOffset;\r
+ UINT32 FspMultiPhaseSiInitEntryOffset;\r
///\r
/// Byte 0x4C: Extended revision of the FSP binary.\r
/// This value is only valid if FSP HeaderRevision is >= 6.\r
/// Minor Version = ImageRevision[23:16]\r
/// Major Version = ImageRevision[31:24]\r
///\r
- UINT16 ExtendedImageRevision;\r
+ UINT16 ExtendedImageRevision;\r
///\r
/// Byte 0x4E: Reserved4.\r
///\r
- UINT16 Reserved4;\r
+ UINT16 Reserved4;\r
} FSP_INFO_HEADER;\r
\r
///\r
///\r
/// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header.\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.\r
///\r
- UINT32 Length;\r
+ UINT32 Length;\r
///\r
/// Byte 0x08: FSP producer defined revision of the table.\r
///\r
- UINT8 Revision;\r
+ UINT8 Revision;\r
///\r
/// Byte 0x09: Reserved for future use.\r
///\r
- UINT8 Reserved;\r
+ UINT8 Reserved;\r
///\r
/// Byte 0x0A: FSP producer identification string\r
///\r
- CHAR8 FspProducerId[6];\r
+ CHAR8 FspProducerId[6];\r
///\r
/// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.\r
///\r
- UINT32 FspProducerRevision;\r
+ UINT32 FspProducerRevision;\r
///\r
/// Byte 0x14: Size of the FSP producer defined data (n) in bytes.\r
///\r
- UINT32 FspProducerDataSize;\r
+ UINT32 FspProducerDataSize;\r
///\r
/// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.\r
///\r
// A generic table search algorithm for additional tables can be implemented with a\r
// signature search algorithm until a terminator signature 'FSPP' is found.\r
//\r
-#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')\r
+#define FSP_FSPP_SIGNATURE SIGNATURE_32 ('F', 'S', 'P', 'P')\r
#define FSP_PATCH_TABLE_SIGNATURE FSP_FSPP_SIGNATURE\r
\r
///\r
///\r
/// Byte 0x00: FSP Patch Table Signature "FSPP".\r
///\r
- UINT32 Signature;\r
+ UINT32 Signature;\r
///\r
/// Byte 0x04: Size including the PatchData.\r
///\r
- UINT16 HeaderLength;\r
+ UINT16 HeaderLength;\r
///\r
/// Byte 0x06: Revision is set to 0x01.\r
///\r
- UINT8 HeaderRevision;\r
+ UINT8 HeaderRevision;\r
///\r
/// Byte 0x07: Reserved for future use.\r
///\r
- UINT8 Reserved;\r
+ UINT8 Reserved;\r
///\r
/// Byte 0x08: Number of entries to Patch.\r
///\r
- UINT32 PatchEntryNum;\r
+ UINT32 PatchEntryNum;\r
///\r
/// Byte 0x0C: Patch Data.\r
///\r
-//UINT32 PatchData[];\r
+ // UINT32 PatchData[];\r
} FSP_PATCH_TABLE;\r
\r
#pragma pack()\r
\r
-extern EFI_GUID gFspHeaderFileGuid;\r
+extern EFI_GUID gFspHeaderFileGuid;\r
\r
#endif\r
/// The Non-Volatile Storage (NVS) HOB version 2 provides > 64KB buffer support.\r
///\r
typedef struct {\r
- EFI_HOB_GUID_TYPE GuidHob;\r
- EFI_PHYSICAL_ADDRESS NvsDataPtr;\r
- UINT64 NvsDataLength;\r
+ EFI_HOB_GUID_TYPE GuidHob;\r
+ EFI_PHYSICAL_ADDRESS NvsDataPtr;\r
+ UINT64 NvsDataLength;\r
} FSP_NON_VOLATILE_STORAGE_HOB2;\r
\r
-extern EFI_GUID gFspNonVolatileStorageHob2Guid;\r
+extern EFI_GUID gFspNonVolatileStorageHob2Guid;\r
\r
#endif\r
#ifndef __GUID_HOB_FSP_EAS_GUID__\r
#define __GUID_HOB_FSP_EAS_GUID__\r
\r
-extern EFI_GUID gFspBootLoaderTolumHobGuid;\r
-extern EFI_GUID gFspReservedMemoryResourceHobGuid;\r
-extern EFI_GUID gFspNonVolatileStorageHobGuid;\r
+extern EFI_GUID gFspBootLoaderTolumHobGuid;\r
+extern EFI_GUID gFspReservedMemoryResourceHobGuid;\r
+extern EFI_GUID gFspNonVolatileStorageHobGuid;\r
\r
#endif\r
VOID\r
EFIAPI\r
DisableCacheAsRam (\r
- IN BOOLEAN DisableCar\r
+ IN BOOLEAN DisableCar\r
);\r
\r
#endif\r
-\r
//\r
typedef INT32 EFI_MEMORY_CACHE_TYPE;\r
\r
-#define EFI_CACHE_UNCACHEABLE 0\r
-#define EFI_CACHE_WRITECOMBINING 1\r
-#define EFI_CACHE_WRITETHROUGH 4\r
-#define EFI_CACHE_WRITEPROTECTED 5\r
-#define EFI_CACHE_WRITEBACK 6\r
+#define EFI_CACHE_UNCACHEABLE 0\r
+#define EFI_CACHE_WRITECOMBINING 1\r
+#define EFI_CACHE_WRITETHROUGH 4\r
+#define EFI_CACHE_WRITEPROTECTED 5\r
+#define EFI_CACHE_WRITEBACK 6\r
\r
/**\r
Reset all the MTRRs to a known state.\r
EFI_STATUS\r
EFIAPI\r
SetCacheAttributes (\r
- IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
- IN UINT64 MemoryLength,\r
- IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
);\r
\r
#endif\r
-\r
VOID\r
EFIAPI\r
SetFspGlobalDataPointer (\r
- IN FSP_GLOBAL_DATA *FspData\r
+ IN FSP_GLOBAL_DATA *FspData\r
);\r
\r
/**\r
\r
@retval FSP entry stack pointer.\r
**/\r
-VOID*\r
+VOID *\r
EFIAPI\r
GetFspEntryStack (\r
VOID\r
VOID\r
EFIAPI\r
SetFspApiParameter (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspCoreStackPointer (\r
- IN VOID *NewStackTop\r
+ IN VOID *NewStackTop\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspPlatformDataPointer (\r
- IN VOID *PlatformData\r
+ IN VOID *PlatformData\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspUpdDataPointer (\r
- IN VOID *UpdDataPtr\r
+ IN VOID *UpdDataPtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspMemoryInitUpdDataPointer (\r
- IN VOID *MemoryInitUpdPtr\r
+ IN VOID *MemoryInitUpdPtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspSiliconInitUpdDataPointer (\r
- IN VOID *SiliconInitUpdPtr\r
+ IN VOID *SiliconInitUpdPtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspInfoHeader (\r
- FSP_INFO_HEADER *FspInfoHeader\r
+ FSP_INFO_HEADER *FspInfoHeader\r
);\r
\r
/**\r
VOID\r
);\r
\r
-\r
/**\r
This function sets FSP Phase StatusCode.\r
\r
VOID\r
EFIAPI\r
FspApiReturnStatusReset (\r
- IN UINT32 FspResetType\r
+ IN UINT32 FspResetType\r
);\r
+\r
#endif\r
EFI_HOB_RESOURCE_DESCRIPTOR *\r
EFIAPI\r
FspGetResourceDescriptorByOwner (\r
- IN EFI_GUID *OwnerGuid\r
+ IN EFI_GUID *OwnerGuid\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
FspGetSystemMemorySize (\r
- IN OUT UINT64 *LowMemoryLength,\r
- IN OUT UINT64 *HighMemoryLength\r
+ IN OUT UINT64 *LowMemoryLength,\r
+ IN OUT UINT64 *HighMemoryLength\r
);\r
\r
-\r
/**\r
Set a new stack frame for the continuation function.\r
\r
VOID\r
EFIAPI\r
FspMemoryInitDone (\r
- IN OUT VOID **HobListPtr\r
+ IN OUT VOID **HobListPtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
FspSiliconInitDone2 (\r
- IN EFI_STATUS Status\r
+ IN EFI_STATUS Status\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
FspMemoryInitDone2 (\r
- IN EFI_STATUS Status,\r
- IN OUT VOID **HobListPtr\r
+ IN EFI_STATUS Status,\r
+ IN OUT VOID **HobListPtr\r
);\r
\r
/**\r
VOID\r
EFIAPI\r
FspTempRamExitDone2 (\r
- IN EFI_STATUS Status\r
+ IN EFI_STATUS Status\r
);\r
\r
#endif\r
UINT32\r
EFIAPI\r
LoadMicrocode (\r
- IN VOID *FsptUpdDataPtr\r
+ IN VOID *FsptUpdDataPtr\r
);\r
\r
/**\r
UINT32\r
EFIAPI\r
SecCarInit (\r
- IN VOID *FsptUpdDataPtr\r
+ IN VOID *FsptUpdDataPtr\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FspUpdSignatureCheck (\r
- IN UINT32 ApiIdx,\r
- IN VOID *ApiParam\r
+ IN UINT32 ApiIdx,\r
+ IN VOID *ApiParam\r
);\r
\r
/**\r
EFI_STATUS\r
EFIAPI\r
FspMultiPhaseSiInitApiHandler (\r
- IN UINT32 ApiIdx,\r
- IN VOID *ApiParam\r
+ IN UINT32 ApiIdx,\r
+ IN VOID *ApiParam\r
);\r
\r
#endif\r
#ifndef _FSPM_ARCH_CONFIG_PPI_H_\r
#define _FSPM_ARCH_CONFIG_PPI_H_\r
\r
-#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1\r
+#define FSPM_ARCH_CONFIG_PPI_REVISION 0x1\r
\r
///\r
/// Global ID for the FSPM_ARCH_CONFIG_PPI.\r
///\r
/// Revision of the structure\r
///\r
- UINT8 Revision;\r
- UINT8 Reserved[3];\r
+ UINT8 Revision;\r
+ UINT8 Reserved[3];\r
///\r
/// Pointer to the non-volatile storage (NVS) data buffer.\r
/// If it is NULL it indicates the NVS data is not available.\r
///\r
- VOID *NvsBufferPtr;\r
+ VOID *NvsBufferPtr;\r
///\r
/// Size of memory to be reserved by FSP below "top\r
/// of low usable memory" for bootloader usage.\r
///\r
- UINT32 BootLoaderTolumSize;\r
- UINT8 Reserved1[4];\r
+ UINT32 BootLoaderTolumSize;\r
+ UINT8 Reserved1[4];\r
} FSPM_ARCH_CONFIG_PPI;\r
\r
-extern EFI_GUID gFspmArchConfigPpiGuid;\r
+extern EFI_GUID gFspmArchConfigPpiGuid;\r
\r
#endif // _FSPM_ARCH_CONFIG_PPI_H_\r
**/\r
typedef\r
EFI_STATUS\r
-(EFIAPI *FSP_TEMP_RAM_EXIT) (\r
+(EFIAPI *FSP_TEMP_RAM_EXIT)(\r
IN VOID *TempRamExitParamPtr\r
);\r
\r
/// This PPI provides function to disable temporary memory.\r
///\r
struct _FSP_TEMP_RAM_EXIT_PPI {\r
- FSP_TEMP_RAM_EXIT TempRamExit;\r
+ FSP_TEMP_RAM_EXIT TempRamExit;\r
};\r
\r
-extern EFI_GUID gFspTempRamExitPpiGuid;\r
+extern EFI_GUID gFspTempRamExitPpiGuid;\r
\r
#endif // _FSP_TEMP_RAM_EXIT_PPI_H_\r
VOID\r
EFIAPI\r
DisableCacheAsRam (\r
- IN BOOLEAN DisableCar\r
+ IN BOOLEAN DisableCar\r
)\r
{\r
//\r
if (DisableCar) {\r
AsmInvd ();\r
} else {\r
- AsmWbinvd();\r
+ AsmWbinvd ();\r
}\r
\r
- return ;\r
+ return;\r
}\r
**/\r
EFI_STATUS\r
SearchForExactMtrr (\r
- IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
- IN UINT64 MemoryLength,\r
- IN UINT64 ValidMtrrAddressMask,\r
- OUT UINT32 *UsedMsrNum,\r
- OUT EFI_MEMORY_CACHE_TYPE *MemoryCacheType\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN UINT64 ValidMtrrAddressMask,\r
+ OUT UINT32 *UsedMsrNum,\r
+ OUT EFI_MEMORY_CACHE_TYPE *MemoryCacheType\r
);\r
\r
/**\r
**/\r
BOOLEAN\r
IsDefaultType (\r
- IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
+ IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
);\r
\r
/**\r
**/\r
UINT32\r
CheckMtrrAlignment (\r
- IN UINT64 BaseAddress,\r
- IN UINT64 Size\r
+ IN UINT64 BaseAddress,\r
+ IN UINT64 Size\r
);\r
\r
typedef struct {\r
UINT32 Length;\r
} EFI_FIXED_MTRR;\r
\r
-EFI_FIXED_MTRR mFixedMtrrTable[] = {\r
- { EFI_MSR_IA32_MTRR_FIX64K_00000, 0, 0x10000},\r
- { EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000},\r
- { EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_C0000, 0xC0000, 0x1000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_C8000, 0xC8000, 0x1000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_D0000, 0xD0000, 0x1000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_D8000, 0xD8000, 0x1000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_E0000, 0xE0000, 0x1000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_E8000, 0xE8000, 0x1000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_F0000, 0xF0000, 0x1000},\r
- { EFI_MSR_IA32_MTRR_FIX4K_F8000, 0xF8000, 0x1000}\r
+EFI_FIXED_MTRR mFixedMtrrTable[] = {\r
+ { EFI_MSR_IA32_MTRR_FIX64K_00000, 0, 0x10000 },\r
+ { EFI_MSR_IA32_MTRR_FIX16K_80000, 0x80000, 0x4000 },\r
+ { EFI_MSR_IA32_MTRR_FIX16K_A0000, 0xA0000, 0x4000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_C0000, 0xC0000, 0x1000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_C8000, 0xC8000, 0x1000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_D0000, 0xD0000, 0x1000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_D8000, 0xD8000, 0x1000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_E0000, 0xE0000, 0x1000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_E8000, 0xE8000, 0x1000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_F0000, 0xF0000, 0x1000 },\r
+ { EFI_MSR_IA32_MTRR_FIX4K_F8000, 0xF8000, 0x1000 }\r
};\r
\r
/**\r
**/\r
INT8\r
CheckDirection (\r
- IN UINT64 Input\r
+ IN UINT64 Input\r
)\r
{\r
return 0;\r
**/\r
VOID\r
EfiDisableCacheMtrr (\r
- OUT UINT64 *OldMtrr\r
+ OUT UINT64 *OldMtrr\r
)\r
{\r
UINT64 TempQword;\r
//\r
// Disable Cache MTRR\r
//\r
- *OldMtrr = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);\r
+ *OldMtrr = AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);\r
TempQword = (*OldMtrr) & ~B_EFI_MSR_GLOBAL_MTRR_ENABLE & ~B_EFI_MSR_FIXED_MTRR_ENABLE;\r
- AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);\r
+ AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, TempQword);\r
AsmDisableCache ();\r
}\r
\r
**/\r
VOID\r
EfiRecoverCacheMtrr (\r
- IN BOOLEAN EnableMtrr,\r
- IN UINT64 OldMtrr\r
+ IN BOOLEAN EnableMtrr,\r
+ IN UINT64 OldMtrr\r
)\r
{\r
UINT64 TempQword;\r
// Enable Cache MTRR\r
//\r
if (EnableMtrr) {\r
- TempQword = AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);\r
+ TempQword = AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE);\r
TempQword |= (UINT64)(B_EFI_MSR_GLOBAL_MTRR_ENABLE | B_EFI_MSR_FIXED_MTRR_ENABLE);\r
} else {\r
TempQword = OldMtrr;\r
**/\r
VOID\r
EfiProgramMtrr (\r
- IN UINT32 MtrrNumber,\r
- IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
- IN UINT64 MemoryLength,\r
- IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,\r
- IN UINT64 ValidMtrrAddressMask\r
+ IN UINT32 MtrrNumber,\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,\r
+ IN UINT64 ValidMtrrAddressMask\r
)\r
{\r
- UINT64 TempQword;\r
- UINT64 OldMtrr;\r
+ UINT64 TempQword;\r
+ UINT64 OldMtrr;\r
\r
if (MemoryLength == 0) {\r
return;\r
**/\r
UINT64\r
Power2MaxMemory (\r
- IN UINT64 MemoryAddress,\r
- IN UINT64 MemoryLength\r
+ IN UINT64 MemoryAddress,\r
+ IN UINT64 MemoryLength\r
)\r
{\r
- UINT64 Result;\r
+ UINT64 Result;\r
\r
if (MemoryLength == 0) {\r
return EFI_INVALID_PARAMETER;\r
//\r
// Compute initial power of 2 size to return\r
//\r
- Result = GetPowerOfTwo64(MemoryLength);\r
+ Result = GetPowerOfTwo64 (MemoryLength);\r
\r
//\r
// Special case base of 0 as all ranges are valid\r
**/\r
UINT32\r
CheckMtrrAlignment (\r
- IN UINT64 BaseAddress,\r
- IN UINT64 Size\r
+ IN UINT64 BaseAddress,\r
+ IN UINT64 Size\r
)\r
{\r
- UINT32 ShiftedBase;\r
- UINT32 ShiftedSize;\r
+ UINT32 ShiftedBase;\r
+ UINT32 ShiftedSize;\r
\r
//\r
// Shift base and size right 12 bits to allow for larger memory sizes. The\r
// MTRRs do not use the first 12 bits so this is safe for now. Only supports\r
// up to 52 bits of physical address space.\r
//\r
- ShiftedBase = (UINT32) RShiftU64 (BaseAddress, 12);\r
- ShiftedSize = (UINT32) RShiftU64 (Size, 12);\r
+ ShiftedBase = (UINT32)RShiftU64 (BaseAddress, 12);\r
+ ShiftedSize = (UINT32)RShiftU64 (Size, 12);\r
\r
//\r
// Return the results to the caller of the MOD\r
**/\r
EFI_STATUS\r
ProgramFixedMtrr (\r
- IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,\r
- IN UINT64 *Base,\r
- IN UINT64 *Len\r
+ IN EFI_MEMORY_CACHE_TYPE MemoryCacheType,\r
+ IN UINT64 *Base,\r
+ IN UINT64 *Len\r
)\r
{\r
- UINT32 MsrNum;\r
- UINT32 ByteShift;\r
- UINT64 TempQword;\r
- UINT64 OrMask;\r
- UINT64 ClearMask;\r
+ UINT32 MsrNum;\r
+ UINT32 ByteShift;\r
+ UINT64 TempQword;\r
+ UINT64 OrMask;\r
+ UINT64 ClearMask;\r
\r
TempQword = 0;\r
- OrMask = 0;\r
+ OrMask = 0;\r
ClearMask = 0;\r
\r
for (MsrNum = 0; MsrNum < V_EFI_FIXED_MTRR_NUMBER; MsrNum++) {\r
if ((*Base >= mFixedMtrrTable[MsrNum].BaseAddress) &&\r
- (*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length))) {\r
+ (*Base < (mFixedMtrrTable[MsrNum].BaseAddress + 8 * mFixedMtrrTable[MsrNum].Length)))\r
+ {\r
break;\r
}\r
}\r
+\r
if (MsrNum == V_EFI_FIXED_MTRR_NUMBER ) {\r
return EFI_DEVICE_ERROR;\r
}\r
+\r
//\r
// We found the fixed MTRR to be programmed\r
//\r
- for (ByteShift=0; ByteShift < 8; ByteShift++) {\r
+ for (ByteShift = 0; ByteShift < 8; ByteShift++) {\r
if ( *Base == (mFixedMtrrTable[MsrNum].BaseAddress + ByteShift * mFixedMtrrTable[MsrNum].Length)) {\r
break;\r
}\r
}\r
+\r
if (ByteShift == 8 ) {\r
return EFI_DEVICE_ERROR;\r
}\r
- for (; ((ByteShift<8) && (*Len >= mFixedMtrrTable[MsrNum].Length));ByteShift++) {\r
- OrMask |= LShiftU64((UINT64) MemoryCacheType, (UINT32) (ByteShift* 8));\r
- ClearMask |= LShiftU64((UINT64) 0xFF, (UINT32) (ByteShift * 8));\r
- *Len -= mFixedMtrrTable[MsrNum].Length;\r
- *Base += mFixedMtrrTable[MsrNum].Length;\r
+\r
+ for ( ; ((ByteShift < 8) && (*Len >= mFixedMtrrTable[MsrNum].Length)); ByteShift++) {\r
+ OrMask |= LShiftU64 ((UINT64)MemoryCacheType, (UINT32)(ByteShift* 8));\r
+ ClearMask |= LShiftU64 ((UINT64)0xFF, (UINT32)(ByteShift * 8));\r
+ *Len -= mFixedMtrrTable[MsrNum].Length;\r
+ *Base += mFixedMtrrTable[MsrNum].Length;\r
}\r
+\r
TempQword = (AsmReadMsr64 (mFixedMtrrTable[MsrNum].Msr) & (~ClearMask)) | OrMask;\r
AsmWriteMsr64 (mFixedMtrrTable[MsrNum].Msr, TempQword);\r
\r
**/\r
BOOLEAN\r
CheckMtrrOverlap (\r
- IN EFI_PHYSICAL_ADDRESS Start,\r
- IN EFI_PHYSICAL_ADDRESS End\r
+ IN EFI_PHYSICAL_ADDRESS Start,\r
+ IN EFI_PHYSICAL_ADDRESS End\r
)\r
{\r
return FALSE;\r
EFI_STATUS\r
EFIAPI\r
SetCacheAttributes (\r
- IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
- IN UINT64 MemoryLength,\r
- IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 MsrNum, MsrNumEnd;\r
- UINT64 TempQword;\r
- UINT32 LastVariableMtrrForBios;\r
- UINT64 OldMtrr;\r
- UINT32 UsedMsrNum;\r
- EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType;\r
- UINT64 ValidMtrrAddressMask;\r
- UINT32 Cpuid_RegEax;\r
+ EFI_STATUS Status;\r
+ UINT32 MsrNum, MsrNumEnd;\r
+ UINT64 TempQword;\r
+ UINT32 LastVariableMtrrForBios;\r
+ UINT64 OldMtrr;\r
+ UINT32 UsedMsrNum;\r
+ EFI_MEMORY_CACHE_TYPE UsedMemoryCacheType;\r
+ UINT64 ValidMtrrAddressMask;\r
+ UINT32 Cpuid_RegEax;\r
\r
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Cpuid_RegEax, NULL, NULL, NULL);\r
if (Cpuid_RegEax >= CPUID_VIR_PHY_ADDRESS_SIZE) {\r
AsmCpuid (CPUID_VIR_PHY_ADDRESS_SIZE, &Cpuid_RegEax, NULL, NULL, NULL);\r
- ValidMtrrAddressMask = (LShiftU64((UINT64) 1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF);\r
+ ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, (Cpuid_RegEax & 0xFF)) - 1) & (~(UINT64)0x0FFF);\r
} else {\r
- ValidMtrrAddressMask = (LShiftU64((UINT64) 1, 36) - 1) & (~(UINT64)0x0FFF);\r
+ ValidMtrrAddressMask = (LShiftU64 ((UINT64)1, 36) - 1) & (~(UINT64)0x0FFF);\r
}\r
\r
//\r
// Check for invalid parameter\r
//\r
- if ((MemoryAddress & ~ValidMtrrAddressMask) != 0 || (MemoryLength & ~ValidMtrrAddressMask) != 0) {\r
+ if (((MemoryAddress & ~ValidMtrrAddressMask) != 0) || ((MemoryLength & ~ValidMtrrAddressMask) != 0)) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
while ((MemoryLength > 0) && (Status == EFI_SUCCESS)) {\r
Status = ProgramFixedMtrr (MemoryCacheType, &MemoryAddress, &MemoryLength);\r
}\r
+\r
EfiRecoverCacheMtrr (TRUE, OldMtrr);\r
return Status;\r
}\r
//\r
// Search if the range attribute has been set before\r
//\r
- Status = SearchForExactMtrr(\r
- MemoryAddress,\r
- MemoryLength,\r
- ValidMtrrAddressMask,\r
- &UsedMsrNum,\r
- &UsedMemoryCacheType\r
- );\r
+ Status = SearchForExactMtrr (\r
+ MemoryAddress,\r
+ MemoryLength,\r
+ ValidMtrrAddressMask,\r
+ &UsedMsrNum,\r
+ &UsedMemoryCacheType\r
+ );\r
\r
- if (!EFI_ERROR(Status)) {\r
+ if (!EFI_ERROR (Status)) {\r
//\r
// Compare if it has the same type as current setting\r
//\r
//\r
// Check if the set type is the same as Default Type\r
//\r
- if (IsDefaultType(MemoryCacheType)) {\r
+ if (IsDefaultType (MemoryCacheType)) {\r
//\r
// Clear the MTRR\r
//\r
- AsmWriteMsr64(UsedMsrNum, 0);\r
- AsmWriteMsr64(UsedMsrNum + 1, 0);\r
+ AsmWriteMsr64 (UsedMsrNum, 0);\r
+ AsmWriteMsr64 (UsedMsrNum + 1, 0);\r
\r
return EFI_SUCCESS;\r
} else {\r
//\r
// Modify the MTRR type\r
//\r
- EfiProgramMtrr(UsedMsrNum,\r
- MemoryAddress,\r
- MemoryLength,\r
- MemoryCacheType,\r
- ValidMtrrAddressMask\r
- );\r
+ EfiProgramMtrr (\r
+ UsedMsrNum,\r
+ MemoryAddress,\r
+ MemoryLength,\r
+ MemoryCacheType,\r
+ ValidMtrrAddressMask\r
+ );\r
return EFI_SUCCESS;\r
}\r
}\r
}\r
\r
-#if 0\r
+ #if 0\r
//\r
// @bug - Need to create memory map so that when checking for overlap we\r
// can determine if an overlap exists based on all caching requests.\r
//\r
// Don't waste a variable MTRR if the caching attrib is same as default in MTRR_DEF_TYPE\r
//\r
- if (MemoryCacheType == (AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE)) {\r
+ if (MemoryCacheType == (AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE)) {\r
if (!CheckMtrrOverlap (MemoryAddress, MemoryAddress+MemoryLength-1)) {\r
return EFI_SUCCESS;\r
}\r
}\r
-#endif\r
+\r
+ #endif\r
\r
//\r
// Find first unused MTRR\r
//\r
- MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));\r
- for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {\r
- if ((AsmReadMsr64(MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) {\r
+ MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));\r
+ for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum += 2) {\r
+ if ((AsmReadMsr64 (MsrNum+1) & B_EFI_MSR_CACHE_MTRR_VALID) == 0 ) {\r
break;\r
}\r
}\r
//\r
TempQword = MemoryLength;\r
\r
- if (TempQword == Power2MaxMemory(MemoryAddress, TempQword)) {\r
- EfiProgramMtrr(MsrNum,\r
- MemoryAddress,\r
- MemoryLength,\r
- MemoryCacheType,\r
- ValidMtrrAddressMask\r
- );\r
-\r
+ if (TempQword == Power2MaxMemory (MemoryAddress, TempQword)) {\r
+ EfiProgramMtrr (\r
+ MsrNum,\r
+ MemoryAddress,\r
+ MemoryLength,\r
+ MemoryCacheType,\r
+ ValidMtrrAddressMask\r
+ );\r
} else {\r
//\r
// Fill in MTRRs with values. Direction can not be checked for this method\r
//\r
// Set next power of 2 region\r
//\r
- MemoryLength = Power2MaxMemory(MemoryAddress, TempQword);\r
- EfiProgramMtrr(MsrNum,\r
- MemoryAddress,\r
- MemoryLength,\r
- MemoryCacheType,\r
- ValidMtrrAddressMask\r
- );\r
+ MemoryLength = Power2MaxMemory (MemoryAddress, TempQword);\r
+ EfiProgramMtrr (\r
+ MsrNum,\r
+ MemoryAddress,\r
+ MemoryLength,\r
+ MemoryCacheType,\r
+ ValidMtrrAddressMask\r
+ );\r
MemoryAddress += MemoryLength;\r
- TempQword -= MemoryLength;\r
- MsrNum += 2;\r
+ TempQword -= MemoryLength;\r
+ MsrNum += 2;\r
} while (TempQword != 0);\r
}\r
\r
VOID\r
)\r
{\r
- UINT32 MsrNum, MsrNumEnd;\r
- UINT16 Index;\r
- UINT64 OldMtrr;\r
- UINT64 CacheType;\r
- BOOLEAN DisableCar;\r
- Index = 0;\r
+ UINT32 MsrNum, MsrNumEnd;\r
+ UINT16 Index;\r
+ UINT64 OldMtrr;\r
+ UINT64 CacheType;\r
+ BOOLEAN DisableCar;\r
+\r
+ Index = 0;\r
DisableCar = TRUE;\r
\r
//\r
//\r
// Set default cache type\r
//\r
- AsmWriteMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType);\r
+ AsmWriteMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE, CacheType);\r
\r
//\r
// Disable CAR\r
//\r
// Reset Variable MTRRs\r
//\r
- MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));\r
+ MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));\r
for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum++) {\r
AsmWriteMsr64 (MsrNum, 0);\r
}\r
**/\r
EFI_STATUS\r
SearchForExactMtrr (\r
- IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
- IN UINT64 MemoryLength,\r
- IN UINT64 ValidMtrrAddressMask,\r
- OUT UINT32 *UsedMsrNum,\r
- OUT EFI_MEMORY_CACHE_TYPE *UsedMemoryCacheType\r
+ IN EFI_PHYSICAL_ADDRESS MemoryAddress,\r
+ IN UINT64 MemoryLength,\r
+ IN UINT64 ValidMtrrAddressMask,\r
+ OUT UINT32 *UsedMsrNum,\r
+ OUT EFI_MEMORY_CACHE_TYPE *UsedMemoryCacheType\r
)\r
{\r
- UINT32 MsrNum, MsrNumEnd;\r
- UINT64 TempQword;\r
+ UINT32 MsrNum, MsrNumEnd;\r
+ UINT64 TempQword;\r
\r
if (MemoryLength == 0) {\r
return EFI_INVALID_PARAMETER;\r
}\r
\r
- MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64(EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));\r
- for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum +=2) {\r
- TempQword = AsmReadMsr64(MsrNum+1);\r
+ MsrNumEnd = EFI_MSR_CACHE_VARIABLE_MTRR_BASE + (2 * (UINT32)(AsmReadMsr64 (EFI_MSR_IA32_MTRR_CAP) & B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT));\r
+ for (MsrNum = EFI_MSR_CACHE_VARIABLE_MTRR_BASE; MsrNum < MsrNumEnd; MsrNum += 2) {\r
+ TempQword = AsmReadMsr64 (MsrNum+1);\r
if ((TempQword & B_EFI_MSR_CACHE_MTRR_VALID) == 0) {\r
continue;\r
}\r
}\r
\r
*UsedMemoryCacheType = (EFI_MEMORY_CACHE_TYPE)(TempQword & B_EFI_MSR_CACHE_MEMORY_TYPE);\r
- *UsedMsrNum = MsrNum;\r
+ *UsedMsrNum = MsrNum;\r
\r
return EFI_SUCCESS;\r
}\r
**/\r
BOOLEAN\r
IsDefaultType (\r
- IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
+ IN EFI_MEMORY_CACHE_TYPE MemoryCacheType\r
)\r
{\r
- if ((AsmReadMsr64(EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) {\r
+ if ((AsmReadMsr64 (EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE) & B_EFI_MSR_CACHE_MEMORY_TYPE) != MemoryCacheType) {\r
return FALSE;\r
}\r
\r
return TRUE;\r
}\r
-\r
#ifndef _CACHE_LIB_INTERNAL_H_\r
#define _CACHE_LIB_INTERNAL_H_\r
\r
-#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200\r
-#define EFI_MSR_CACHE_VARIABLE_MTRR_END 0x0000020F\r
-#define V_EFI_FIXED_MTRR_NUMBER 11\r
-\r
-#define EFI_MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
-#define EFI_MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
-#define EFI_MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
-#define EFI_MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
-#define EFI_MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
-#define EFI_MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
-#define EFI_MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
-#define EFI_MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
-#define EFI_MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
-#define EFI_MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
-#define EFI_MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
-#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE 0x000002FF\r
-#define B_EFI_MSR_CACHE_MTRR_VALID BIT11\r
-#define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11\r
-#define B_EFI_MSR_FIXED_MTRR_ENABLE BIT10\r
-#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0)\r
-\r
-#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
-#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
-#define EFI_SMRR_CACHE_VALID_ADDRESS 0xFFFFF000\r
-#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r
+#define EFI_MSR_CACHE_VARIABLE_MTRR_BASE 0x00000200\r
+#define EFI_MSR_CACHE_VARIABLE_MTRR_END 0x0000020F\r
+#define V_EFI_FIXED_MTRR_NUMBER 11\r
+\r
+#define EFI_MSR_IA32_MTRR_FIX64K_00000 0x00000250\r
+#define EFI_MSR_IA32_MTRR_FIX16K_80000 0x00000258\r
+#define EFI_MSR_IA32_MTRR_FIX16K_A0000 0x00000259\r
+#define EFI_MSR_IA32_MTRR_FIX4K_C0000 0x00000268\r
+#define EFI_MSR_IA32_MTRR_FIX4K_C8000 0x00000269\r
+#define EFI_MSR_IA32_MTRR_FIX4K_D0000 0x0000026A\r
+#define EFI_MSR_IA32_MTRR_FIX4K_D8000 0x0000026B\r
+#define EFI_MSR_IA32_MTRR_FIX4K_E0000 0x0000026C\r
+#define EFI_MSR_IA32_MTRR_FIX4K_E8000 0x0000026D\r
+#define EFI_MSR_IA32_MTRR_FIX4K_F0000 0x0000026E\r
+#define EFI_MSR_IA32_MTRR_FIX4K_F8000 0x0000026F\r
+#define EFI_MSR_CACHE_IA32_MTRR_DEF_TYPE 0x000002FF\r
+#define B_EFI_MSR_CACHE_MTRR_VALID BIT11\r
+#define B_EFI_MSR_GLOBAL_MTRR_ENABLE BIT11\r
+#define B_EFI_MSR_FIXED_MTRR_ENABLE BIT10\r
+#define B_EFI_MSR_CACHE_MEMORY_TYPE (BIT2 | BIT1 | BIT0)\r
+\r
+#define EFI_MSR_VALID_MASK 0xFFFFFFFFF\r
+#define EFI_CACHE_VALID_ADDRESS 0xFFFFFF000\r
+#define EFI_SMRR_CACHE_VALID_ADDRESS 0xFFFFF000\r
+#define EFI_CACHE_VALID_EXTENDED_ADDRESS 0xFFFFFFFFFF000\r
\r
// Leave one MTRR pairs for OS use\r
-#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS 1\r
-#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) - \\r
+#define EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS 1\r
+#define EFI_CACHE_LAST_VARIABLE_MTRR_FOR_BIOS (EFI_MSR_CACHE_VARIABLE_MTRR_END) -\\r
(EFI_CACHE_NUM_VAR_MTRR_PAIRS_FOR_OS * 2)\r
\r
-#define EFI_MSR_IA32_MTRR_CAP 0x000000FE\r
-#define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT BIT12\r
-#define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11\r
-#define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT BIT10\r
-#define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8\r
-#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)\r
+#define EFI_MSR_IA32_MTRR_CAP 0x000000FE\r
+#define B_EFI_MSR_IA32_MTRR_CAP_EMRR_SUPPORT BIT12\r
+#define B_EFI_MSR_IA32_MTRR_CAP_SMRR_SUPPORT BIT11\r
+#define B_EFI_MSR_IA32_MTRR_CAP_WC_SUPPORT BIT10\r
+#define B_EFI_MSR_IA32_MTRR_CAP_FIXED_SUPPORT BIT8\r
+#define B_EFI_MSR_IA32_MTRR_CAP_VARIABLE_SUPPORT (BIT7 | BIT6 | BIT5 | BIT4 | BIT3 | BIT2 | BIT1 | BIT0)\r
\r
-#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
-#define CPUID_EXTENDED_FUNCTION 0x80000000\r
+#define CPUID_VIR_PHY_ADDRESS_SIZE 0x80000008\r
+#define CPUID_EXTENDED_FUNCTION 0x80000000\r
\r
#endif\r
-\r
VOID\r
EFIAPI\r
SetFspGlobalDataPointer (\r
- IN FSP_GLOBAL_DATA *FspData\r
+ IN FSP_GLOBAL_DATA *FspData\r
)\r
{\r
ASSERT (FspData != NULL);\r
- *((volatile UINT32 *)(UINTN)PcdGet32(PcdGlobalDataPointerAddress)) = (UINT32)(UINTN)FspData;\r
+ *((volatile UINT32 *)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress)) = (UINT32)(UINTN)FspData;\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- FSP_GLOBAL_DATA *FspData;\r
+ FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = *(FSP_GLOBAL_DATA **)(UINTN)PcdGet32(PcdGlobalDataPointerAddress);\r
+ FspData = *(FSP_GLOBAL_DATA **)(UINTN)PcdGet32 (PcdGlobalDataPointerAddress);\r
return FspData;\r
}\r
\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[0]));\r
+ FspData = GetFspGlobalDataPointer ();\r
+ return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[0]));\r
}\r
\r
/**\r
\r
@retval FSP entry stack pointer.\r
**/\r
-VOID*\r
+VOID *\r
EFIAPI\r
GetFspEntryStack (\r
VOID\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- return (VOID*)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[0]));\r
+ FspData = GetFspGlobalDataPointer ();\r
+ return (VOID *)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[0]));\r
}\r
\r
/**\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam[1]));\r
+ FspData = GetFspGlobalDataPointer ();\r
+ return *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam[1]));\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspApiParameter (\r
- IN UINT32 Value\r
+ IN UINT32 Value\r
)\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(ApiParam)) = Value;\r
+ FspData = GetFspGlobalDataPointer ();\r
+ *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (ApiParam)) = Value;\r
}\r
\r
/**\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(Eax)) = ReturnStatus;\r
+ FspData = GetFspGlobalDataPointer ();\r
+ *(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (Eax)) = ReturnStatus;\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspCoreStackPointer (\r
- IN VOID *NewStackTop\r
+ IN VOID *NewStackTop\r
)\r
{\r
FSP_GLOBAL_DATA *FspData;\r
UINT32 *NewStack;\r
UINT32 StackContextLen;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- StackContextLen = sizeof(CONTEXT_STACK) / sizeof(UINT32);\r
+ FspData = GetFspGlobalDataPointer ();\r
+ StackContextLen = sizeof (CONTEXT_STACK) / sizeof (UINT32);\r
\r
//\r
// Reserve space for the ContinuationFunc two parameters\r
//\r
- OldStack = (UINT32 *)FspData->CoreStack;\r
- NewStack = (UINT32 *)NewStackTop - StackContextLen - 2;\r
+ OldStack = (UINT32 *)FspData->CoreStack;\r
+ NewStack = (UINT32 *)NewStackTop - StackContextLen - 2;\r
FspData->CoreStack = (UINT32)NewStack;\r
while (StackContextLen-- != 0) {\r
*NewStack++ = *OldStack++;\r
VOID\r
EFIAPI\r
SetFspPlatformDataPointer (\r
- IN VOID *PlatformData\r
+ IN VOID *PlatformData\r
)\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
FspData->PlatformData.DataPtr = PlatformData;\r
}\r
\r
-\r
/**\r
This function gets the platform specific data pointer.\r
\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
return FspData->PlatformData.DataPtr;\r
}\r
\r
-\r
/**\r
This function sets the UPD data pointer.\r
\r
VOID\r
EFIAPI\r
SetFspUpdDataPointer (\r
- IN VOID *UpdDataPtr\r
+ IN VOID *UpdDataPtr\r
)\r
{\r
FSP_GLOBAL_DATA *FspData;\r
//\r
// Get the FSP Global Data Pointer\r
//\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
\r
//\r
// Set the UPD pointer.\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
return FspData->UpdDataPtr;\r
}\r
\r
-\r
/**\r
This function sets the FspMemoryInit UPD data pointer.\r
\r
VOID\r
EFIAPI\r
SetFspMemoryInitUpdDataPointer (\r
- IN VOID *MemoryInitUpdPtr\r
+ IN VOID *MemoryInitUpdPtr\r
)\r
{\r
FSP_GLOBAL_DATA *FspData;\r
//\r
// Get the FSP Global Data Pointer\r
//\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
\r
//\r
// Set the FspMemoryInit UPD pointer.\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
return FspData->MemoryInitUpdPtr;\r
}\r
\r
-\r
/**\r
This function sets the FspSiliconInit UPD data pointer.\r
\r
VOID\r
EFIAPI\r
SetFspSiliconInitUpdDataPointer (\r
- IN VOID *SiliconInitUpdPtr\r
+ IN VOID *SiliconInitUpdPtr\r
)\r
{\r
FSP_GLOBAL_DATA *FspData;\r
//\r
// Get the FSP Global Data Pointer\r
//\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
\r
//\r
// Set the FspSiliconInit UPD data pointer.\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
return FspData->SiliconInitUpdPtr;\r
}\r
\r
-\r
/**\r
Set FSP measurement point timestamp.\r
\r
// Bit [55: 0] will be the timestamp\r
// Bit [63:56] will be the ID\r
//\r
- FspData = GetFspGlobalDataPointer ();\r
- if (FspData->PerfIdx < sizeof(FspData->PerfData) / sizeof(FspData->PerfData[0])) {\r
- FspData->PerfData[FspData->PerfIdx] = AsmReadTsc ();\r
+ FspData = GetFspGlobalDataPointer ();\r
+ if (FspData->PerfIdx < sizeof (FspData->PerfData) / sizeof (FspData->PerfData[0])) {\r
+ FspData->PerfData[FspData->PerfIdx] = AsmReadTsc ();\r
((UINT8 *)(&FspData->PerfData[FspData->PerfIdx]))[7] = Id;\r
}\r
\r
VOID\r
)\r
{\r
- return GetFspGlobalDataPointer()->FspInfoHeader;\r
+ return GetFspGlobalDataPointer ()->FspInfoHeader;\r
}\r
\r
/**\r
VOID\r
EFIAPI\r
SetFspInfoHeader (\r
- FSP_INFO_HEADER *FspInfoHeader\r
+ FSP_INFO_HEADER *FspInfoHeader\r
)\r
{\r
- GetFspGlobalDataPointer()->FspInfoHeader = FspInfoHeader;\r
+ GetFspGlobalDataPointer ()->FspInfoHeader = FspInfoHeader;\r
}\r
\r
/**\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- return (FSP_INFO_HEADER *)(*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET(FspInfoHeader)));\r
+ FspData = GetFspGlobalDataPointer ();\r
+ return (FSP_INFO_HEADER *)(*(UINT32 *)(UINTN)(FspData->CoreStack + CONTEXT_STACK_OFFSET (FspInfoHeader)));\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- FSP_INFO_HEADER *FspInfoHeader;\r
+ FSP_INFO_HEADER *FspInfoHeader;\r
\r
FspInfoHeader = GetFspInfoHeader ();\r
return (VOID *)(FspInfoHeader->ImageBase + FspInfoHeader->CfgRegionOffset);\r
VOID\r
)\r
{\r
- return GetFspGlobalDataPointer()->ApiIdx;\r
+ return GetFspGlobalDataPointer ()->ApiIdx;\r
}\r
\r
/**\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
FspData->ApiIdx = Index;\r
}\r
\r
VOID\r
)\r
{\r
- return GetFspGlobalDataPointer()->StatusCode;\r
+ return GetFspGlobalDataPointer ()->StatusCode;\r
}\r
\r
/**\r
{\r
FSP_GLOBAL_DATA *FspData;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
+ FspData = GetFspGlobalDataPointer ();\r
FspData->StatusCode = StatusCode;\r
}\r
\r
VOID\r
EFIAPI\r
FspApiReturnStatusReset (\r
- IN UINT32 FspResetType\r
+ IN UINT32 FspResetType\r
)\r
{\r
volatile BOOLEAN LoopUntilReset;\r
\r
LoopUntilReset = TRUE;\r
- DEBUG ((DEBUG_INFO, "FSP returning control to Bootloader with reset required return status %x\n",FspResetType));\r
+ DEBUG ((DEBUG_INFO, "FSP returning control to Bootloader with reset required return status %x\n", FspResetType));\r
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {\r
///\r
/// Below code is not an infinite loop.The control will go back to API calling function in BootLoader each time BootLoader\r
// VA_LIST can not initialize to NULL for all compiler, so we use this to\r
// indicate a null VA_LIST\r
//\r
-VA_LIST mVaListNull;\r
+VA_LIST mVaListNull;\r
\r
/**\r
Get stack frame pointer of function call.\r
VOID\r
);\r
\r
-\r
/**\r
Prints a debug message to the debug output device if the specified error level is enabled.\r
\r
...\r
)\r
{\r
- VA_LIST Marker;\r
+ VA_LIST Marker;\r
\r
VA_START (Marker, Format);\r
DebugVPrint (ErrorLevel, Format, Marker);\r
**/\r
VOID\r
DebugPrintMarker (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
\r
//\r
// If Format is NULL, then ASSERT().\r
VOID\r
EFIAPI\r
DebugVPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN VA_LIST VaListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN VA_LIST VaListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, VaListMarker, NULL);\r
VOID\r
EFIAPI\r
DebugBPrint (\r
- IN UINTN ErrorLevel,\r
- IN CONST CHAR8 *Format,\r
- IN BASE_LIST BaseListMarker\r
+ IN UINTN ErrorLevel,\r
+ IN CONST CHAR8 *Format,\r
+ IN BASE_LIST BaseListMarker\r
)\r
{\r
DebugPrintMarker (ErrorLevel, Format, mVaListNull, BaseListMarker);\r
**/\r
VOID\r
FillHex (\r
- UINT32 Value,\r
+ UINT32 Value,\r
CHAR8 *Buffer\r
)\r
{\r
INTN Idx;\r
+\r
for (Idx = 7; Idx >= 0; Idx--) {\r
Buffer[Idx] = mHexTable[Value & 0x0F];\r
- Value >>= 4;\r
+ Value >>= 4;\r
}\r
}\r
\r
VOID\r
)\r
{\r
- CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
- UINT32 *Frame;\r
+ CHAR8 Buffer[MAX_DEBUG_MESSAGE_LENGTH];\r
+ UINT32 *Frame;\r
\r
Frame = (UINT32 *)GetStackFramePointer ();\r
\r
//\r
AsciiStrnCpyS (\r
Buffer,\r
- sizeof(Buffer) / sizeof(CHAR8),\r
+ sizeof (Buffer) / sizeof (CHAR8),\r
"-> EBP:0x00000000 EIP:0x00000000\n",\r
- sizeof(Buffer) / sizeof(CHAR8) - 1\r
+ sizeof (Buffer) / sizeof (CHAR8) - 1\r
);\r
SerialPortWrite ((UINT8 *)"ASSERT DUMP:\n", 13);\r
while (Frame != NULL) {\r
DebugAssertInternal ();\r
}\r
\r
-\r
/**\r
Fills a target buffer with PcdDebugClearMemoryValue, and returns the target buffer.\r
\r
return Buffer;\r
}\r
\r
-\r
/**\r
Returns TRUE if ASSERT() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_ASSERT_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG() macros are enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_PRINT_ENABLED) != 0);\r
}\r
\r
/**\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_DEBUG_CODE_ENABLED) != 0);\r
}\r
\r
-\r
/**\r
Returns TRUE if DEBUG_CLEAR_MEMORY() macro is enabled.\r
\r
VOID\r
)\r
{\r
- return (BOOLEAN) ((PcdGet8(PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
+ return (BOOLEAN)((PcdGet8 (PcdDebugPropertyMask) & DEBUG_PROPERTY_CLEAR_MEMORY_ENABLED) != 0);\r
}\r
\r
/**\r
BOOLEAN\r
EFIAPI\r
DebugPrintLevelEnabled (\r
- IN CONST UINTN ErrorLevel\r
+ IN CONST UINTN ErrorLevel\r
)\r
{\r
- return (BOOLEAN) ((ErrorLevel & PcdGet32(PcdFixedDebugPrintErrorLevel)) != 0);\r
+ return (BOOLEAN)((ErrorLevel & PcdGet32 (PcdFixedDebugPrintErrorLevel)) != 0);\r
}\r
EFI_HOB_RESOURCE_DESCRIPTOR *\r
EFIAPI\r
FspGetResourceDescriptorByOwner (\r
- IN EFI_GUID *OwnerGuid\r
+ IN EFI_GUID *OwnerGuid\r
)\r
{\r
- EFI_PEI_HOB_POINTERS Hob;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
\r
//\r
// Get the HOB list for processing\r
while (!END_OF_HOB_LIST (Hob)) {\r
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {\r
if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) && \\r
- (CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid))) {\r
- return Hob.ResourceDescriptor;\r
+ (CompareGuid (&Hob.ResourceDescriptor->Owner, OwnerGuid)))\r
+ {\r
+ return Hob.ResourceDescriptor;\r
}\r
}\r
+\r
Hob.Raw = GET_NEXT_HOB (Hob);\r
}\r
\r
VOID\r
EFIAPI\r
FspGetSystemMemorySize (\r
- IN OUT UINT64 *LowMemoryLength,\r
- IN OUT UINT64 *HighMemoryLength\r
+ IN OUT UINT64 *LowMemoryLength,\r
+ IN OUT UINT64 *HighMemoryLength\r
)\r
{\r
- EFI_STATUS Status;\r
- EFI_BOOT_MODE BootMode;\r
- EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;\r
- EFI_PEI_HOB_POINTERS Hob;\r
+ EFI_STATUS Status;\r
+ EFI_BOOT_MODE BootMode;\r
+ EFI_RESOURCE_ATTRIBUTE_TYPE ResourceAttribute;\r
+ EFI_PEI_HOB_POINTERS Hob;\r
\r
ResourceAttribute = (\r
EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
if (Hob.Header->HobType == EFI_HOB_TYPE_RESOURCE_DESCRIPTOR) {\r
if ((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_SYSTEM_MEMORY) ||\r
((Hob.ResourceDescriptor->ResourceType == EFI_RESOURCE_MEMORY_RESERVED) &&\r
- (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute))) {\r
+ (Hob.ResourceDescriptor->ResourceAttribute == ResourceAttribute)))\r
+ {\r
//\r
// Need memory above 1MB to be collected here\r
//\r
- if (Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB &&\r
- Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS) BASE_4GB) {\r
- *LowMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);\r
- } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS) BASE_4GB) {\r
- *HighMemoryLength += (UINT64) (Hob.ResourceDescriptor->ResourceLength);\r
+ if ((Hob.ResourceDescriptor->PhysicalStart >= BASE_1MB) &&\r
+ (Hob.ResourceDescriptor->PhysicalStart < (EFI_PHYSICAL_ADDRESS)BASE_4GB))\r
+ {\r
+ *LowMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);\r
+ } else if (Hob.ResourceDescriptor->PhysicalStart >= (EFI_PHYSICAL_ADDRESS)BASE_4GB) {\r
+ *HighMemoryLength += (UINT64)(Hob.ResourceDescriptor->ResourceLength);\r
}\r
}\r
}\r
+\r
Hob.Raw = GET_NEXT_HOB (Hob);\r
}\r
}\r
#include <Protocol/PciEnumerationComplete.h>\r
#include <Library/ReportStatusCodeLib.h>\r
#include <Library/PerformanceLib.h>\r
-extern EFI_GUID gFspPerformanceDataGuid;\r
+extern EFI_GUID gFspPerformanceDataGuid;\r
\r
-EFI_PEI_PPI_DESCRIPTOR mPeiPostPciEnumerationPpi = {\r
+EFI_PEI_PPI_DESCRIPTOR mPeiPostPciEnumerationPpi = {\r
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
&gEfiPciEnumerationCompleteProtocolGuid,\r
NULL\r
};\r
\r
-EFI_PEI_PPI_DESCRIPTOR mPeiReadyToBootPpi = {\r
+EFI_PEI_PPI_DESCRIPTOR mPeiReadyToBootPpi = {\r
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
&gEfiEventReadyToBootGuid,\r
NULL\r
};\r
\r
-EFI_PEI_PPI_DESCRIPTOR mPeiEndOfFirmwarePpi = {\r
+EFI_PEI_PPI_DESCRIPTOR mPeiEndOfFirmwarePpi = {\r
(EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),\r
&gFspEventEndOfFirmwareGuid,\r
NULL\r
EFI_STATUS\r
EFIAPI\r
FspNotificationHandler (\r
- IN UINT32 NotificationCode\r
+ IN UINT32 NotificationCode\r
)\r
{\r
- EFI_STATUS Status;\r
+ EFI_STATUS Status;\r
\r
- Status = EFI_SUCCESS;\r
+ Status = EFI_SUCCESS;\r
\r
switch (NotificationCode) {\r
- case EnumInitPhaseAfterPciEnumeration:\r
- //\r
- // Do POST PCI initialization if needed\r
- //\r
- DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Post PCI Enumeration ...\n"));\r
- PeiServicesInstallPpi (&mPeiPostPciEnumerationPpi);\r
- break;\r
-\r
- case EnumInitPhaseReadyToBoot:\r
- //\r
- // Ready To Boot\r
- //\r
- DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP Ready To Boot ...\n"));\r
- PeiServicesInstallPpi (&mPeiReadyToBootPpi);\r
- break;\r
-\r
- case EnumInitPhaseEndOfFirmware:\r
- //\r
- // End of Firmware\r
- //\r
- DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP End of Firmware ...\n"));\r
- PeiServicesInstallPpi (&mPeiEndOfFirmwarePpi);\r
- break;\r
-\r
- default:\r
- Status = EFI_INVALID_PARAMETER;\r
- break;\r
+ case EnumInitPhaseAfterPciEnumeration:\r
+ //\r
+ // Do POST PCI initialization if needed\r
+ //\r
+ DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Post PCI Enumeration ...\n"));\r
+ PeiServicesInstallPpi (&mPeiPostPciEnumerationPpi);\r
+ break;\r
+\r
+ case EnumInitPhaseReadyToBoot:\r
+ //\r
+ // Ready To Boot\r
+ //\r
+ DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP Ready To Boot ...\n"));\r
+ PeiServicesInstallPpi (&mPeiReadyToBootPpi);\r
+ break;\r
+\r
+ case EnumInitPhaseEndOfFirmware:\r
+ //\r
+ // End of Firmware\r
+ //\r
+ DEBUG ((DEBUG_INFO| DEBUG_INIT, "FSP End of Firmware ...\n"));\r
+ PeiServicesInstallPpi (&mPeiEndOfFirmwarePpi);\r
+ break;\r
+\r
+ default:\r
+ Status = EFI_INVALID_PARAMETER;\r
+ break;\r
}\r
\r
return Status;\r
VOID\r
EFIAPI\r
FspSiliconInitDone2 (\r
- IN EFI_STATUS Status\r
+ IN EFI_STATUS Status\r
)\r
{\r
- volatile EFI_STATUS FspStatus;\r
+ volatile EFI_STATUS FspStatus;\r
\r
FspStatus = Status;\r
//\r
Status = EFI_DEVICE_ERROR; // Force to known error.\r
break;\r
}\r
+\r
//\r
// This is the end of the FspSiliconInit API\r
// Give control back to the boot loader\r
VOID\r
EFIAPI\r
FspMemoryInitDone2 (\r
- IN EFI_STATUS Status,\r
- IN OUT VOID **HobListPtr\r
+ IN EFI_STATUS Status,\r
+ IN OUT VOID **HobListPtr\r
)\r
{\r
- FSP_GLOBAL_DATA *FspData;\r
- volatile EFI_STATUS FspStatus;\r
+ FSP_GLOBAL_DATA *FspData;\r
+ volatile EFI_STATUS FspStatus;\r
\r
FspStatus = Status;\r
//\r
if (HobListPtr == NULL) {\r
HobListPtr = (VOID **)GetFspApiParameter2 ();\r
}\r
+\r
if (HobListPtr != NULL) {\r
- *HobListPtr = (VOID *) GetHobList ();\r
+ *HobListPtr = (VOID *)GetHobList ();\r
}\r
+\r
//\r
// Convert to FSP EAS defined API return codes\r
//\r
Status = EFI_DEVICE_ERROR; // Force to known error.\r
break;\r
}\r
+\r
//\r
// This is the end of the FspMemoryInit API\r
// Give control back to the boot loader\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspMemoryInitApi() - [Status: 0x%08X] - End\n", Status));\r
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT);\r
FspData = GetFspGlobalDataPointer ();\r
- PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY);\r
- PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
- PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
- PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+ PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[0] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE| FSP_STATUS_CODE_API_ENTRY);\r
+ PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[1] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_TEMP_RAM_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+ PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, (FspData->PerfData[2] & FSP_PERFORMANCE_DATA_TIMER_MASK), FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+ PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_MEMORY_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {\r
do {\r
if (GetFspApiCallingIndex () == TempRamExitApiIndex) {\r
SetPhaseStatusCode (FSP_STATUS_CODE_TEMP_RAM_EXIT);\r
SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY);\r
- PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+ PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - Begin\n"));\r
} else {\r
SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);\r
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);\r
- PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+ PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "FspSiliconInitApi() - Begin\n"));\r
}\r
VOID\r
EFIAPI\r
FspTempRamExitDone2 (\r
- IN EFI_STATUS Status\r
+ IN EFI_STATUS Status\r
)\r
{\r
//\r
- volatile EFI_STATUS FspStatus;\r
+ volatile EFI_STATUS FspStatus;\r
\r
FspStatus = Status;\r
// Convert to FSP EAS defined API return codes\r
Status = EFI_DEVICE_ERROR; // Force to known error.\r
break;\r
}\r
+\r
//\r
// This is the end of the TempRamExit API\r
// Give control back to the boot loader\r
//\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "TempRamExitApi() - [Status: 0x%08X] - End\n", Status));\r
SetFspMeasurePoint (FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT);\r
- PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+ PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_TEMP_RAM_EXIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {\r
do {\r
}\r
} while (FspStatus != EFI_SUCCESS);\r
}\r
+\r
SetPhaseStatusCode (FSP_STATUS_CODE_SILICON_INIT);\r
SetFspMeasurePoint (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY);\r
- PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+ PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_SILICON_INIT | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
DEBUG ((DEBUG_INFO | DEBUG_INIT, "SiliconInitApi() - Begin\n"));\r
}\r
VOID\r
)\r
{\r
- EFI_STATUS Status;\r
- UINT32 NotificationValue;\r
- UINT32 NotificationCount;\r
- UINT8 Count;\r
- volatile EFI_STATUS FspStatus;\r
+ EFI_STATUS Status;\r
+ UINT32 NotificationValue;\r
+ UINT32 NotificationCount;\r
+ UINT8 Count;\r
+ volatile EFI_STATUS FspStatus;\r
\r
NotificationCount = 0;\r
- while (NotificationCount < sizeof(mFspNotifySequence) / sizeof(UINT32)) {\r
-\r
+ while (NotificationCount < sizeof (mFspNotifySequence) / sizeof (UINT32)) {\r
Count = (UINT8)((NotificationCount << 1) & 0x07);\r
SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + Count);\r
\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
} else if (NotificationCount == 1) {\r
SetPhaseStatusCode (FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION);\r
- PERF_START_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
+ PERF_START_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_ENTRY);\r
} else if (NotificationCount == 2) {\r
SetPhaseStatusCode (FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION);\r
// Process Notification and Give control back to the boot loader framework caller\r
//\r
Status = FspNotificationHandler (NotificationValue);\r
- if (!EFI_ERROR(Status)) {\r
+ if (!EFI_ERROR (Status)) {\r
NotificationCount++;\r
}\r
}\r
SetFspMeasurePoint (FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT + Count);\r
\r
if ((NotificationCount - 1) == 0) {\r
- PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+ PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_POST_PCIE_ENUM_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
} else if ((NotificationCount - 1) == 1) {\r
- PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+ PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_READY_TO_BOOT_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
} else if ((NotificationCount - 1) == 2) {\r
- PERF_END_EX(&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
+ PERF_END_EX (&gFspPerformanceDataGuid, "EventRec", NULL, 0, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
REPORT_STATUS_CODE (EFI_PROGRESS_CODE, FSP_STATUS_CODE_END_OF_FIRMWARE_NOTIFICATION | FSP_STATUS_CODE_COMMON_CODE | FSP_STATUS_CODE_API_EXIT);\r
}\r
+\r
if (GetFspGlobalDataPointer ()->FspMode == FSP_IN_API_MODE) {\r
FspStatus = Status;\r
do {\r
- SetFspApiReturnStatus(Status);\r
- Pei2LoaderSwitchStack();\r
+ SetFspApiReturnStatus (Status);\r
+ Pei2LoaderSwitchStack ();\r
if (Status != EFI_SUCCESS) {\r
DEBUG ((DEBUG_ERROR, "!!!ERROR: NotifyPhaseApi() [Phase: %08X] - Failed - [Status: 0x%08X]\n", NotificationValue, Status));\r
}\r
} while (FspStatus != EFI_SUCCESS);\r
}\r
}\r
+\r
//\r
// Control goes back to the PEI Core and it dispatches further PEIMs.\r
// DXEIPL is the final one to transfer control back to the boot loader.\r
VOID\r
EFIAPI\r
FspMemoryInitDone (\r
- IN OUT VOID **HobListPtr\r
+ IN OUT VOID **HobListPtr\r
)\r
{\r
FspMemoryInitDone2 (EFI_SUCCESS, HobListPtr);\r
**/\r
UINT32\r
SwapStack (\r
- IN UINT32 NewStack\r
+ IN UINT32 NewStack\r
)\r
{\r
FSP_GLOBAL_DATA *FspData;\r
- UINT32 OldStack;\r
+ UINT32 OldStack;\r
\r
- FspData = GetFspGlobalDataPointer ();\r
- OldStack = FspData->CoreStack;\r
+ FspData = GetFspGlobalDataPointer ();\r
+ OldStack = FspData->CoreStack;\r
FspData->CoreStack = NewStack;\r
return OldStack;\r
}\r
-\r
EFI_STATUS\r
EFIAPI\r
FspUpdSignatureCheck (\r
- IN UINT32 ApiIdx,\r
- IN VOID *ApiParam\r
+ IN UINT32 ApiIdx,\r
+ IN VOID *ApiParam\r
)\r
{\r
return EFI_SUCCESS;\r
EFI_STATUS\r
EFIAPI\r
FspMultiPhaseSiInitApiHandler (\r
- IN UINT32 ApiIdx,\r
- IN VOID *ApiParam\r
+ IN UINT32 ApiIdx,\r
+ IN VOID *ApiParam\r
)\r
{\r
return EFI_SUCCESS;\r
\r
#pragma pack(1)\r
\r
-#define FSPT_UPD_SIGNATURE 0x545F4450554D4551 /* 'QEMUPD_T' */\r
+#define FSPT_UPD_SIGNATURE 0x545F4450554D4551 /* 'QEMUPD_T' */\r
\r
-#define FSPM_UPD_SIGNATURE 0x4D5F4450554D4551 /* 'QEMUPD_M' */\r
+#define FSPM_UPD_SIGNATURE 0x4D5F4450554D4551 /* 'QEMUPD_M' */\r
\r
-#define FSPS_UPD_SIGNATURE 0x535F4450554D4551 /* 'QEMUPD_S' */\r
+#define FSPS_UPD_SIGNATURE 0x535F4450554D4551 /* 'QEMUPD_S' */\r
\r
#pragma pack()\r
\r
\r
#pragma pack(1)\r
\r
-\r
/** Fsp M Configuration\r
**/\r
typedef struct {\r
-\r
-/** Offset 0x00C8 - Debug Serial Port Base address\r
- Debug serial port base address. This option will be used only when the 'Serial Port\r
- Debug Device' option is set to 'External Device'. 0x00000000(Default).\r
-**/\r
- UINT32 SerialDebugPortAddress;\r
-\r
-/** Offset 0x00CC - Debug Serial Port Type\r
- 16550 compatible debug serial port resource type. NONE means no serial port support.\r
- 0x02:MMIO(Default).\r
- 0:NONE, 1:I/O, 2:MMIO\r
-**/\r
- UINT8 SerialDebugPortType;\r
-\r
-/** Offset 0x00CD - Serial Port Debug Device\r
- Select active serial port device for debug.For SOC UART devices,'Debug Serial Port\r
- Base' options will be ignored. 0x02:SOC UART2(Default).\r
- 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device\r
-**/\r
- UINT8 SerialDebugPortDevice;\r
-\r
-/** Offset 0x00CE - Debug Serial Port Stride Size\r
- Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).\r
- 0:1, 2:4\r
-**/\r
- UINT8 SerialDebugPortStrideSize;\r
-\r
-/** Offset 0x00CF\r
-**/\r
- UINT8 UnusedUpdSpace2[1];\r
-\r
-/** Offset 0x00D0\r
-**/\r
- UINT8 ReservedFspmUpd[4];\r
+ /** Offset 0x00C8 - Debug Serial Port Base address\r
+ Debug serial port base address. This option will be used only when the 'Serial Port\r
+ Debug Device' option is set to 'External Device'. 0x00000000(Default).\r
+ **/\r
+ UINT32 SerialDebugPortAddress;\r
+\r
+ /** Offset 0x00CC - Debug Serial Port Type\r
+ 16550 compatible debug serial port resource type. NONE means no serial port support.\r
+ 0x02:MMIO(Default).\r
+ 0:NONE, 1:I/O, 2:MMIO\r
+ **/\r
+ UINT8 SerialDebugPortType;\r
+\r
+ /** Offset 0x00CD - Serial Port Debug Device\r
+ Select active serial port device for debug.For SOC UART devices,'Debug Serial Port\r
+ Base' options will be ignored. 0x02:SOC UART2(Default).\r
+ 0:SOC UART0, 1:SOC UART1, 2:SOC UART2, 3:External Device\r
+ **/\r
+ UINT8 SerialDebugPortDevice;\r
+\r
+ /** Offset 0x00CE - Debug Serial Port Stride Size\r
+ Debug serial port register map stride size in bytes. 0x00:1, 0x02:4(Default).\r
+ 0:1, 2:4\r
+ **/\r
+ UINT8 SerialDebugPortStrideSize;\r
+\r
+ /** Offset 0x00CF\r
+ **/\r
+ UINT8 UnusedUpdSpace2[1];\r
+\r
+ /** Offset 0x00D0\r
+ **/\r
+ UINT8 ReservedFspmUpd[4];\r
} FSP_M_CONFIG;\r
\r
/** Fsp M UPD Configuration\r
**/\r
typedef struct {\r
+ /** Offset 0x0000\r
+ **/\r
+ FSP_UPD_HEADER FspUpdHeader;\r
\r
-/** Offset 0x0000\r
-**/\r
- FSP_UPD_HEADER FspUpdHeader;\r
+ /** Offset 0x00A8\r
+ **/\r
+ FSPM_ARCH_UPD FspmArchUpd;\r
\r
-/** Offset 0x00A8\r
-**/\r
- FSPM_ARCH_UPD FspmArchUpd;\r
+ /** Offset 0x00C8\r
+ **/\r
+ FSP_M_CONFIG FspmConfig;\r
\r
-/** Offset 0x00C8\r
-**/\r
- FSP_M_CONFIG FspmConfig;\r
-\r
-/** Offset 0x00D4\r
-**/\r
- UINT8 UnusedUpdSpace3[2];\r
+ /** Offset 0x00D4\r
+ **/\r
+ UINT8 UnusedUpdSpace3[2];\r
\r
-/** Offset 0x00D6\r
-**/\r
- UINT16 UpdTerminator;\r
+ /** Offset 0x00D6\r
+ **/\r
+ UINT16 UpdTerminator;\r
} FSPM_UPD;\r
\r
#pragma pack()\r
\r
#pragma pack(1)\r
\r
-\r
/** Fsp S Configuration\r
**/\r
typedef struct {\r
-\r
-/** Offset 0x0118 - BMP Logo Data Size\r
- BMP logo data buffer size. 0x00000000(Default).\r
-**/\r
- UINT32 LogoSize;\r
-\r
-/** Offset 0x011C - BMP Logo Data Pointer\r
- BMP logo data pointer to a BMP format buffer. 0x00000000(Default).\r
-**/\r
- UINT32 LogoPtr;\r
-\r
-/** Offset 0x0120 - Graphics Configuration Data Pointer\r
- Graphics configuration data used for initialization. 0x00000000(Default).\r
-**/\r
- UINT32 GraphicsConfigPtr;\r
-\r
-/** Offset 0x0124 - PCI GFX Temporary MMIO Base\r
- PCI Temporary PCI GFX Base used before full PCI enumeration. 0x80000000(Default).\r
-**/\r
- UINT32 PciTempResourceBase;\r
-\r
-/** Offset 0x0128\r
-**/\r
- UINT8 UnusedUpdSpace1[3];\r
-\r
-/** Offset 0x012B\r
-**/\r
- UINT8 ReservedFspsUpd;\r
+ /** Offset 0x0118 - BMP Logo Data Size\r
+ BMP logo data buffer size. 0x00000000(Default).\r
+ **/\r
+ UINT32 LogoSize;\r
+\r
+ /** Offset 0x011C - BMP Logo Data Pointer\r
+ BMP logo data pointer to a BMP format buffer. 0x00000000(Default).\r
+ **/\r
+ UINT32 LogoPtr;\r
+\r
+ /** Offset 0x0120 - Graphics Configuration Data Pointer\r
+ Graphics configuration data used for initialization. 0x00000000(Default).\r
+ **/\r
+ UINT32 GraphicsConfigPtr;\r
+\r
+ /** Offset 0x0124 - PCI GFX Temporary MMIO Base\r
+ PCI Temporary PCI GFX Base used before full PCI enumeration. 0x80000000(Default).\r
+ **/\r
+ UINT32 PciTempResourceBase;\r
+\r
+ /** Offset 0x0128\r
+ **/\r
+ UINT8 UnusedUpdSpace1[3];\r
+\r
+ /** Offset 0x012B\r
+ **/\r
+ UINT8 ReservedFspsUpd;\r
} FSP_S_CONFIG;\r
\r
/** Fsp S UPD Configuration\r
**/\r
typedef struct {\r
+ /** Offset 0x0000\r
+ **/\r
+ FSP_UPD_HEADER FspUpdHeader;\r
\r
-/** Offset 0x0000\r
-**/\r
- FSP_UPD_HEADER FspUpdHeader;\r
+ /** Offset 0x00F8\r
+ **/\r
+ FSPS_ARCH_UPD FspsArchUpd;\r
\r
-/** Offset 0x00F8\r
-**/\r
- FSPS_ARCH_UPD FspsArchUpd;\r
+ /** Offset 0x0118\r
+ **/\r
+ FSP_S_CONFIG FspsConfig;\r
\r
-/** Offset 0x0118\r
-**/\r
- FSP_S_CONFIG FspsConfig;\r
-\r
-/** Offset 0x012C\r
-**/\r
- UINT8 UnusedUpdSpace2[2];\r
+ /** Offset 0x012C\r
+ **/\r
+ UINT8 UnusedUpdSpace2[2];\r
\r
-/** Offset 0x012E\r
-**/\r
- UINT16 UpdTerminator;\r
+ /** Offset 0x012E\r
+ **/\r
+ UINT16 UpdTerminator;\r
} FSPS_UPD;\r
\r
#pragma pack()\r
\r
#pragma pack(1)\r
\r
-\r
/** Fsp T Common UPD\r
**/\r
typedef struct {\r
+ /** Offset 0x0040\r
+ **/\r
+ UINT8 Revision;\r
\r
-/** Offset 0x0040\r
-**/\r
- UINT8 Revision;\r
+ /** Offset 0x0041\r
+ **/\r
+ UINT8 Reserved[3];\r
\r
-/** Offset 0x0041\r
-**/\r
- UINT8 Reserved[3];\r
-\r
-/** Offset 0x0044\r
-**/\r
- UINT32 MicrocodeRegionBase;\r
+ /** Offset 0x0044\r
+ **/\r
+ UINT32 MicrocodeRegionBase;\r
\r
-/** Offset 0x0048\r
-**/\r
- UINT32 MicrocodeRegionLength;\r
+ /** Offset 0x0048\r
+ **/\r
+ UINT32 MicrocodeRegionLength;\r
\r
-/** Offset 0x004C\r
-**/\r
- UINT32 CodeRegionBase;\r
+ /** Offset 0x004C\r
+ **/\r
+ UINT32 CodeRegionBase;\r
\r
-/** Offset 0x0050\r
-**/\r
- UINT32 CodeRegionLength;\r
+ /** Offset 0x0050\r
+ **/\r
+ UINT32 CodeRegionLength;\r
\r
-/** Offset 0x0054\r
-**/\r
- UINT8 Reserved1[12];\r
+ /** Offset 0x0054\r
+ **/\r
+ UINT8 Reserved1[12];\r
} FSPT_COMMON_UPD;\r
\r
/** Fsp T Configuration\r
**/\r
typedef struct {\r
-\r
-/** Offset 0x0060 - Chicken bytes to test Hex config\r
- This option shows how to present option for 4 bytes data\r
-**/\r
- UINT32 ChickenBytes;\r
-\r
-/** Offset 0x0064\r
-**/\r
- UINT8 ReservedFsptUpd1[28];\r
+ /** Offset 0x0060 - Chicken bytes to test Hex config\r
+ This option shows how to present option for 4 bytes data\r
+ **/\r
+ UINT32 ChickenBytes;\r
+\r
+ /** Offset 0x0064\r
+ **/\r
+ UINT8 ReservedFsptUpd1[28];\r
} FSP_T_CONFIG;\r
\r
/** Fsp T UPD Configuration\r
**/\r
typedef struct {\r
+ /** Offset 0x0000\r
+ **/\r
+ FSP_UPD_HEADER FspUpdHeader;\r
\r
-/** Offset 0x0000\r
-**/\r
- FSP_UPD_HEADER FspUpdHeader;\r
-\r
-/** Offset 0x0020\r
-**/\r
- FSPT_ARCH_UPD FsptArchUpd;\r
+ /** Offset 0x0020\r
+ **/\r
+ FSPT_ARCH_UPD FsptArchUpd;\r
\r
-/** Offset 0x0040\r
-**/\r
- FSPT_COMMON_UPD FsptCommonUpd;\r
+ /** Offset 0x0040\r
+ **/\r
+ FSPT_COMMON_UPD FsptCommonUpd;\r
\r
-/** Offset 0x0060\r
-**/\r
- FSP_T_CONFIG FsptConfig;\r
+ /** Offset 0x0060\r
+ **/\r
+ FSP_T_CONFIG FsptConfig;\r
\r
-/** Offset 0x0080\r
-**/\r
- UINT8 UnusedUpdSpace0[6];\r
+ /** Offset 0x0080\r
+ **/\r
+ UINT8 UnusedUpdSpace0[6];\r
\r
-/** Offset 0x0086\r
-**/\r
- UINT16 UpdTerminator;\r
+ /** Offset 0x0086\r
+ **/\r
+ UINT16 UpdTerminator;\r
} FSPT_UPD;\r
\r
#pragma pack()\r
projects / mirror_edk2.git / commitdiff