projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| cf1d4549 JY |
1 | /** @file\r |
| 2 | \r | |
| 3 | Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r | |
| 9672cd30 | 4 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| cf1d4549 JY |
5 | \r |
| 6 | **/\r | |
| 7 | \r | |
| 8 | #ifndef _FSP_MEASURE_POINT_ID_H_\r | |
| 9 | #define _FSP_MEASURE_POINT_ID_H_\r | |
| 10 | \r | |
| 11 | //\r | |
| 12 | // 0xD0 - 0xEF are reserved for FSP common measure point\r | |
| 13 | //\r | |
| 111f2228 MK |
14 | #define FSP_PERF_ID_MRC_INIT_ENTRY 0xD0\r |
| 15 | #define FSP_PERF_ID_MRC_INIT_EXIT (FSP_PERF_ID_MRC_INIT_ENTRY + 1)\r | |
| cf1d4549 | 16 | \r |
| 111f2228 MK |
17 | #define FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY 0xD8\r |
| 18 | #define FSP_PERF_ID_SYSTEM_AGENT_INIT_EXIT (FSP_PERF_ID_SYSTEM_AGENT_INIT_ENTRY + 1)\r | |
| cf1d4549 | 19 | \r |
| 111f2228 MK |
20 | #define FSP_PERF_ID_PCH_INIT_ENTRY 0xDA\r |
| 21 | #define FSP_PERF_ID_PCH_INIT_EXIT (FSP_PERF_ID_PCH_INIT_ENTRY + 1)\r | |
| cf1d4549 | 22 | \r |
| 111f2228 MK |
23 | #define FSP_PERF_ID_CPU_INIT_ENTRY 0xE0\r |
| 24 | #define FSP_PERF_ID_CPU_INIT_EXIT (FSP_PERF_ID_CPU_INIT_ENTRY + 1)\r | |
| cf1d4549 | 25 | \r |
| 111f2228 MK |
26 | #define FSP_PERF_ID_GFX_INIT_ENTRY 0xE8\r |
| 27 | #define FSP_PERF_ID_GFX_INIT_EXIT (FSP_PERF_ID_GFX_INIT_ENTRY + 1)\r | |
| cf1d4549 | 28 | \r |
| 111f2228 MK |
29 | #define FSP_PERF_ID_ME_INIT_ENTRY 0xEA\r |
| 30 | #define FSP_PERF_ID_ME_INIT_EXIT (FSP_PERF_ID_ME_INIT_ENTRY + 1)\r | |
| cf1d4549 JY |
31 | \r |
| 32 | //\r | |
| 33 | // 0xF0 - 0xFF are reserved for FSP API\r | |
| 34 | //\r | |
| 111f2228 MK |
35 | #define FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY 0xF0\r |
| 36 | #define FSP_PERF_ID_API_TEMP_RAM_INIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_INIT_ENTRY + 1)\r | |
| cf1d4549 | 37 | \r |
| 111f2228 MK |
38 | #define FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY 0xF2\r |
| 39 | #define FSP_PERF_ID_API_FSP_MEMORY_INIT_EXIT (FSP_PERF_ID_API_FSP_MEMORY_INIT_ENTRY + 1)\r | |
| cf1d4549 | 40 | \r |
| 111f2228 MK |
41 | #define FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY 0xF4\r |
| 42 | #define FSP_PERF_ID_API_TEMP_RAM_EXIT_EXIT (FSP_PERF_ID_API_TEMP_RAM_EXIT_ENTRY + 1)\r | |
| cf1d4549 | 43 | \r |
| 111f2228 MK |
44 | #define FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY 0xF6\r |
| 45 | #define FSP_PERF_ID_API_FSP_SILICON_INIT_EXIT (FSP_PERF_ID_API_FSP_SILICON_INIT_ENTRY + 1)\r | |
| cf1d4549 | 46 | \r |
| 111f2228 MK |
47 | #define FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY 0xF8\r |
| 48 | #define FSP_PERF_ID_API_NOTIFY_POST_PCI_EXIT (FSP_PERF_ID_API_NOTIFY_POST_PCI_ENTRY + 1)\r | |
| cf1d4549 | 49 | \r |
| 111f2228 MK |
50 | #define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY 0xFA\r |
| 51 | #define FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_EXIT (FSP_PERF_ID_API_NOTIFY_READY_TO_BOOT_ENTRY + 1)\r | |
| cf1d4549 JY |
52 | \r |
| 53 | #define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY 0xFC\r | |
| 54 | #define FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_EXIT (FSP_PERF_ID_API_NOTIFY_END_OF_FIRMWARE_ENTRY + 1)\r | |
| 55 | \r | |
| 56 | #endif\r |