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a33a2f62 JY |
1 | /** @file\r |
2 | Intel FSP Info Header definition from Intel Firmware Support Package External\r | |
3 | Architecture Specification, April 2014, revision 001.\r | |
4 | \r | |
d5fb1edf | 5 | Copyright (c) 2014 - 2015, Intel Corporation. All rights reserved.<BR>\r |
a33a2f62 JY |
6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php.\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _FSP_INFO_HEADER_H_\r | |
17 | #define _FSP_INFO_HEADER_H_\r | |
18 | \r | |
d5fb1edf JY |
19 | #define FSP_HEADER_REVISION_1 1\r |
20 | #define FSP_HEADER_REVISION_2 2\r | |
21 | \r | |
22 | #define FSPE_HEADER_REVISION_1 1\r | |
23 | #define FSPP_HEADER_REVISION_1 1\r | |
24 | \r | |
a33a2f62 JY |
25 | ///\r |
26 | /// Fixed FSP header offset in the FSP image\r | |
27 | ///\r | |
28 | #define FSP_INFO_HEADER_OFF 0x94\r | |
29 | \r | |
30 | #define OFFSET_IN_FSP_INFO_HEADER(x) (UINT32)&((FSP_INFO_HEADER *)(UINTN)0)->x\r | |
31 | \r | |
32 | #pragma pack(1)\r | |
33 | \r | |
34 | typedef struct {\r | |
35 | ///\r | |
d5fb1edf | 36 | /// Byte 0x00: Signature ('FSPH') for the FSP Information Header\r |
a33a2f62 JY |
37 | ///\r |
38 | UINT32 Signature;\r | |
39 | ///\r | |
d5fb1edf | 40 | /// Byte 0x04: Length of the FSP Information Header\r |
a33a2f62 JY |
41 | ///\r |
42 | UINT32 HeaderLength;\r | |
43 | ///\r | |
d5fb1edf | 44 | /// Byte 0x08: Reserved\r |
a33a2f62 JY |
45 | ///\r |
46 | UINT8 Reserved1[3];\r | |
47 | ///\r | |
d5fb1edf | 48 | /// Byte 0x0B: Revision of the FSP Information Header\r |
a33a2f62 JY |
49 | ///\r |
50 | UINT8 HeaderRevision;\r | |
51 | ///\r | |
d5fb1edf | 52 | /// Byte 0x0C: Revision of the FSP binary\r |
a33a2f62 JY |
53 | ///\r |
54 | UINT32 ImageRevision;\r | |
55 | \r | |
56 | \r | |
57 | ///\r | |
d5fb1edf | 58 | /// Byte 0x10: Signature string that will help match the FSP Binary to a supported\r |
a33a2f62 JY |
59 | /// hardware configuration.\r |
60 | ///\r | |
61 | CHAR8 ImageId[8];\r | |
62 | ///\r | |
d5fb1edf | 63 | /// Byte 0x18: Size of the entire FSP binary\r |
a33a2f62 JY |
64 | ///\r |
65 | UINT32 ImageSize;\r | |
66 | ///\r | |
9da59186 | 67 | /// Byte 0x1C: FSP binary preferred base address\r |
a33a2f62 JY |
68 | ///\r |
69 | UINT32 ImageBase;\r | |
70 | \r | |
71 | \r | |
72 | ///\r | |
d5fb1edf | 73 | /// Byte 0x20: Attribute for the FSP binary\r |
a33a2f62 JY |
74 | ///\r |
75 | UINT32 ImageAttribute;\r | |
76 | ///\r | |
d5fb1edf | 77 | /// Byte 0x24: Offset of the FSP configuration region\r |
a33a2f62 JY |
78 | ///\r |
79 | UINT32 CfgRegionOffset;\r | |
80 | ///\r | |
9da59186 | 81 | /// Byte 0x28: Size of the FSP configuration region\r |
a33a2f62 JY |
82 | ///\r |
83 | UINT32 CfgRegionSize;\r | |
84 | ///\r | |
d5fb1edf | 85 | /// Byte 0x2C: Number of API entries this FSP supports\r |
a33a2f62 JY |
86 | ///\r |
87 | UINT32 ApiEntryNum;\r | |
88 | \r | |
89 | \r | |
90 | ///\r | |
d5fb1edf JY |
91 | /// Byte 0x30: The offset for the API to setup a temporary stack till the memory\r |
92 | /// is initialized.\r | |
a33a2f62 JY |
93 | ///\r |
94 | UINT32 TempRamInitEntryOffset;\r | |
95 | ///\r | |
d5fb1edf | 96 | /// Byte 0x34: The offset for the API to initialize the CPU and the chipset (SOC)\r |
a33a2f62 JY |
97 | ///\r |
98 | UINT32 FspInitEntryOffset;\r | |
99 | ///\r | |
d5fb1edf JY |
100 | /// Byte 0x38: The offset for the API to inform the FSP about the different stages\r |
101 | /// in the boot process\r | |
a33a2f62 JY |
102 | ///\r |
103 | UINT32 NotifyPhaseEntryOffset;\r | |
d5fb1edf | 104 | \r |
a33a2f62 | 105 | ///\r |
9da59186 | 106 | /// Below fields are added in FSP Revision 2\r |
a33a2f62 | 107 | ///\r |
d5fb1edf JY |
108 | \r |
109 | ///\r | |
110 | /// Byte 0x3C: The offset for the API to initialize the memory\r | |
111 | ///\r | |
112 | UINT32 FspMemoryInitEntryOffset;\r | |
113 | ///\r | |
114 | /// Byte 0x40: The offset for the API to tear down temporary RAM\r | |
115 | ///\r | |
116 | UINT32 TempRamExitEntryOffset;\r | |
117 | ///\r | |
118 | /// Byte 0x44: The offset for the API to initialize the CPU and chipset\r | |
119 | ///\r | |
120 | UINT32 FspSiliconInitEntryOffset;\r | |
a33a2f62 JY |
121 | \r |
122 | } FSP_INFO_HEADER;\r | |
123 | \r | |
d5fb1edf | 124 | ///\r |
9da59186 | 125 | /// Below structure is added in FSP version 2\r |
d5fb1edf JY |
126 | ///\r |
127 | typedef struct {\r | |
128 | ///\r | |
129 | /// Byte 0x00: Signature ('FSPE') for the FSP Extended Information Header\r | |
130 | ///\r | |
131 | UINT32 Signature;\r | |
132 | ///\r | |
43bfa527 | 133 | /// Byte 0x04: Length of the table in bytes, including all additional FSP producer defined data.\r |
d5fb1edf | 134 | ///\r |
43bfa527 | 135 | UINT32 Length;\r |
d5fb1edf | 136 | ///\r |
43bfa527 | 137 | /// Byte 0x08: FSP producer defined revision of the table.\r |
d5fb1edf JY |
138 | ///\r |
139 | UINT8 Revision;\r | |
140 | ///\r | |
141 | /// Byte 0x09: Reserved for future use.\r | |
142 | ///\r | |
143 | UINT8 Reserved;\r | |
144 | ///\r | |
43bfa527 JY |
145 | /// Byte 0x0A: FSP producer identification string \r |
146 | ///\r | |
147 | CHAR8 FspProducerId[6];\r | |
148 | ///\r | |
149 | /// Byte 0x10: FSP producer implementation revision number. Larger numbers are assumed to be newer revisions.\r | |
150 | ///\r | |
151 | UINT32 FspProducerRevision;\r | |
152 | ///\r | |
153 | /// Byte 0x14: Size of the FSP producer defined data (n) in bytes.\r | |
d5fb1edf | 154 | ///\r |
43bfa527 | 155 | UINT32 FspProducerDataSize;\r |
d5fb1edf | 156 | ///\r |
43bfa527 | 157 | /// Byte 0x18: FSP producer defined data of size (n) defined by FspProducerDataSize.\r |
d5fb1edf | 158 | ///\r |
d5fb1edf | 159 | \r |
43bfa527 | 160 | } FSP_INFO_EXTENTED_HEADER;\r |
d5fb1edf | 161 | \r |
a33a2f62 JY |
162 | #pragma pack()\r |
163 | \r | |
164 | #endif\r |