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eb290d02 FT |
1 | /** @file\r |
2 | NvmExpressDxe driver is used to manage non-volatile memory subsystem which follows\r | |
3 | NVM Express specification.\r | |
4 | \r | |
35f910f0 | 5 | (C) Copyright 2014 Hewlett-Packard Development Company, L.P.<BR>\r |
769402ef | 6 | Copyright (c) 2013 - 2015, Intel Corporation. All rights reserved.<BR>\r |
eb290d02 FT |
7 | This program and the accompanying materials\r |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php.\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | #include "NvmExpress.h"\r | |
18 | \r | |
eb290d02 FT |
19 | /**\r |
20 | Dump the execution status from a given completion queue entry.\r | |
21 | \r | |
22 | @param[in] Cq A pointer to the NVME_CQ item.\r | |
23 | \r | |
24 | **/\r | |
25 | VOID\r | |
26 | NvmeDumpStatus (\r | |
27 | IN NVME_CQ *Cq\r | |
28 | )\r | |
29 | {\r | |
30 | DEBUG ((EFI_D_VERBOSE, "Dump NVMe Completion Entry Status from [0x%x]:\n", Cq));\r | |
31 | \r | |
32 | DEBUG ((EFI_D_VERBOSE, " SQ Identifier : [0x%x], Phase Tag : [%d], Cmd Identifier : [0x%x]\n", Cq->Sqid, Cq->Pt, Cq->Cid));\r | |
33 | \r | |
34 | DEBUG ((EFI_D_VERBOSE, " NVMe Cmd Execution Result - "));\r | |
35 | \r | |
36 | switch (Cq->Sct) {\r | |
37 | case 0x0:\r | |
38 | switch (Cq->Sc) {\r | |
39 | case 0x0:\r | |
40 | DEBUG ((EFI_D_VERBOSE, "Successful Completion\n"));\r | |
41 | break;\r | |
42 | case 0x1:\r | |
43 | DEBUG ((EFI_D_VERBOSE, "Invalid Command Opcode\n"));\r | |
44 | break;\r | |
45 | case 0x2:\r | |
46 | DEBUG ((EFI_D_VERBOSE, "Invalid Field in Command\n"));\r | |
47 | break;\r | |
48 | case 0x3:\r | |
49 | DEBUG ((EFI_D_VERBOSE, "Command ID Conflict\n"));\r | |
50 | break;\r | |
51 | case 0x4:\r | |
52 | DEBUG ((EFI_D_VERBOSE, "Data Transfer Error\n"));\r | |
53 | break;\r | |
54 | case 0x5:\r | |
55 | DEBUG ((EFI_D_VERBOSE, "Commands Aborted due to Power Loss Notification\n"));\r | |
56 | break;\r | |
57 | case 0x6:\r | |
58 | DEBUG ((EFI_D_VERBOSE, "Internal Device Error\n"));\r | |
59 | break;\r | |
60 | case 0x7:\r | |
61 | DEBUG ((EFI_D_VERBOSE, "Command Abort Requested\n"));\r | |
62 | break;\r | |
63 | case 0x8:\r | |
64 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to SQ Deletion\n"));\r | |
65 | break;\r | |
66 | case 0x9:\r | |
67 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Failed Fused Command\n"));\r | |
68 | break;\r | |
69 | case 0xA:\r | |
70 | DEBUG ((EFI_D_VERBOSE, "Command Aborted due to Missing Fused Command\n"));\r | |
71 | break;\r | |
72 | case 0xB:\r | |
73 | DEBUG ((EFI_D_VERBOSE, "Invalid Namespace or Format\n"));\r | |
74 | break;\r | |
75 | case 0xC:\r | |
76 | DEBUG ((EFI_D_VERBOSE, "Command Sequence Error\n"));\r | |
77 | break;\r | |
78 | case 0xD:\r | |
79 | DEBUG ((EFI_D_VERBOSE, "Invalid SGL Last Segment Descriptor\n"));\r | |
80 | break;\r | |
81 | case 0xE:\r | |
82 | DEBUG ((EFI_D_VERBOSE, "Invalid Number of SGL Descriptors\n"));\r | |
83 | break;\r | |
84 | case 0xF:\r | |
85 | DEBUG ((EFI_D_VERBOSE, "Data SGL Length Invalid\n"));\r | |
86 | break;\r | |
87 | case 0x10:\r | |
88 | DEBUG ((EFI_D_VERBOSE, "Metadata SGL Length Invalid\n"));\r | |
89 | break;\r | |
90 | case 0x11:\r | |
91 | DEBUG ((EFI_D_VERBOSE, "SGL Descriptor Type Invalid\n"));\r | |
92 | break;\r | |
93 | case 0x80:\r | |
94 | DEBUG ((EFI_D_VERBOSE, "LBA Out of Range\n"));\r | |
95 | break;\r | |
96 | case 0x81:\r | |
97 | DEBUG ((EFI_D_VERBOSE, "Capacity Exceeded\n"));\r | |
98 | break;\r | |
99 | case 0x82:\r | |
100 | DEBUG ((EFI_D_VERBOSE, "Namespace Not Ready\n"));\r | |
101 | break;\r | |
102 | case 0x83:\r | |
103 | DEBUG ((EFI_D_VERBOSE, "Reservation Conflict\n"));\r | |
104 | break;\r | |
105 | }\r | |
106 | break;\r | |
107 | \r | |
108 | case 0x1:\r | |
109 | switch (Cq->Sc) {\r | |
110 | case 0x0:\r | |
111 | DEBUG ((EFI_D_VERBOSE, "Completion Queue Invalid\n"));\r | |
112 | break;\r | |
113 | case 0x1:\r | |
114 | DEBUG ((EFI_D_VERBOSE, "Invalid Queue Identifier\n"));\r | |
115 | break;\r | |
116 | case 0x2:\r | |
117 | DEBUG ((EFI_D_VERBOSE, "Maximum Queue Size Exceeded\n"));\r | |
118 | break;\r | |
119 | case 0x3:\r | |
120 | DEBUG ((EFI_D_VERBOSE, "Abort Command Limit Exceeded\n"));\r | |
121 | break;\r | |
122 | case 0x5:\r | |
123 | DEBUG ((EFI_D_VERBOSE, "Asynchronous Event Request Limit Exceeded\n"));\r | |
124 | break;\r | |
125 | case 0x6:\r | |
126 | DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Slot\n"));\r | |
127 | break;\r | |
128 | case 0x7:\r | |
129 | DEBUG ((EFI_D_VERBOSE, "Invalid Firmware Image\n"));\r | |
130 | break;\r | |
131 | case 0x8:\r | |
132 | DEBUG ((EFI_D_VERBOSE, "Invalid Interrupt Vector\n"));\r | |
133 | break;\r | |
134 | case 0x9:\r | |
135 | DEBUG ((EFI_D_VERBOSE, "Invalid Log Page\n"));\r | |
136 | break;\r | |
137 | case 0xA:\r | |
138 | DEBUG ((EFI_D_VERBOSE, "Invalid Format\n"));\r | |
139 | break;\r | |
140 | case 0xB:\r | |
141 | DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires Conventional Reset\n"));\r | |
142 | break;\r | |
143 | case 0xC:\r | |
144 | DEBUG ((EFI_D_VERBOSE, "Invalid Queue Deletion\n"));\r | |
145 | break;\r | |
146 | case 0xD:\r | |
147 | DEBUG ((EFI_D_VERBOSE, "Feature Identifier Not Saveable\n"));\r | |
148 | break;\r | |
149 | case 0xE:\r | |
150 | DEBUG ((EFI_D_VERBOSE, "Feature Not Changeable\n"));\r | |
151 | break;\r | |
152 | case 0xF:\r | |
153 | DEBUG ((EFI_D_VERBOSE, "Feature Not Namespace Specific\n"));\r | |
154 | break;\r | |
155 | case 0x10:\r | |
156 | DEBUG ((EFI_D_VERBOSE, "Firmware Application Requires NVM Subsystem Reset\n"));\r | |
157 | break;\r | |
158 | case 0x80:\r | |
159 | DEBUG ((EFI_D_VERBOSE, "Conflicting Attributes\n"));\r | |
160 | break;\r | |
161 | case 0x81:\r | |
162 | DEBUG ((EFI_D_VERBOSE, "Invalid Protection Information\n"));\r | |
163 | break;\r | |
164 | case 0x82:\r | |
165 | DEBUG ((EFI_D_VERBOSE, "Attempted Write to Read Only Range\n"));\r | |
166 | break;\r | |
167 | }\r | |
168 | break;\r | |
169 | \r | |
170 | case 0x2:\r | |
171 | switch (Cq->Sc) {\r | |
172 | case 0x80:\r | |
173 | DEBUG ((EFI_D_VERBOSE, "Write Fault\n"));\r | |
174 | break;\r | |
175 | case 0x81:\r | |
176 | DEBUG ((EFI_D_VERBOSE, "Unrecovered Read Error\n"));\r | |
177 | break;\r | |
178 | case 0x82:\r | |
179 | DEBUG ((EFI_D_VERBOSE, "End-to-end Guard Check Error\n"));\r | |
180 | break;\r | |
181 | case 0x83:\r | |
182 | DEBUG ((EFI_D_VERBOSE, "End-to-end Application Tag Check Error\n"));\r | |
183 | break;\r | |
184 | case 0x84:\r | |
185 | DEBUG ((EFI_D_VERBOSE, "End-to-end Reference Tag Check Error\n"));\r | |
186 | break;\r | |
187 | case 0x85:\r | |
188 | DEBUG ((EFI_D_VERBOSE, "Compare Failure\n"));\r | |
189 | break;\r | |
190 | case 0x86:\r | |
191 | DEBUG ((EFI_D_VERBOSE, "Access Denied\n"));\r | |
192 | break;\r | |
193 | }\r | |
194 | break;\r | |
195 | \r | |
196 | default:\r | |
197 | break;\r | |
198 | }\r | |
199 | }\r | |
200 | \r | |
201 | /**\r | |
202 | Create PRP lists for data transfer which is larger than 2 memory pages.\r | |
203 | Note here we calcuate the number of required PRP lists and allocate them at one time.\r | |
204 | \r | |
205 | @param[in] PciIo A pointer to the EFI_PCI_IO_PROTOCOL instance.\r | |
206 | @param[in] PhysicalAddr The physical base address of data buffer.\r | |
207 | @param[in] Pages The number of pages to be transfered.\r | |
208 | @param[out] PrpListHost The host base address of PRP lists.\r | |
209 | @param[in,out] PrpListNo The number of PRP List.\r | |
210 | @param[out] Mapping The mapping value returned from PciIo.Map().\r | |
211 | \r | |
212 | @retval The pointer to the first PRP List of the PRP lists.\r | |
213 | \r | |
214 | **/\r | |
215 | VOID*\r | |
216 | NvmeCreatePrpList (\r | |
217 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
218 | IN EFI_PHYSICAL_ADDRESS PhysicalAddr,\r | |
219 | IN UINTN Pages,\r | |
220 | OUT VOID **PrpListHost,\r | |
221 | IN OUT UINTN *PrpListNo,\r | |
222 | OUT VOID **Mapping\r | |
223 | )\r | |
224 | {\r | |
225 | UINTN PrpEntryNo;\r | |
226 | UINT64 PrpListBase;\r | |
227 | UINTN PrpListIndex;\r | |
228 | UINTN PrpEntryIndex;\r | |
229 | UINT64 Remainder;\r | |
230 | EFI_PHYSICAL_ADDRESS PrpListPhyAddr;\r | |
231 | UINTN Bytes;\r | |
232 | EFI_STATUS Status;\r | |
233 | \r | |
234 | //\r | |
235 | // The number of Prp Entry in a memory page.\r | |
236 | //\r | |
237 | PrpEntryNo = EFI_PAGE_SIZE / sizeof (UINT64);\r | |
238 | \r | |
239 | //\r | |
240 | // Calculate total PrpList number.\r | |
241 | //\r | |
769402ef FT |
242 | *PrpListNo = (UINTN)DivU64x64Remainder ((UINT64)Pages, (UINT64)PrpEntryNo - 1, &Remainder);\r |
243 | if (*PrpListNo == 0) {\r | |
244 | *PrpListNo = 1;\r | |
a9ec6d65 | 245 | } else if ((Remainder != 0) && (Remainder != 1)) {\r |
eb290d02 | 246 | *PrpListNo += 1;\r |
769402ef FT |
247 | } else if (Remainder == 1) {\r |
248 | Remainder = PrpEntryNo;\r | |
249 | } else if (Remainder == 0) {\r | |
250 | Remainder = PrpEntryNo - 1;\r | |
eb290d02 FT |
251 | }\r |
252 | \r | |
253 | Status = PciIo->AllocateBuffer (\r | |
254 | PciIo,\r | |
255 | AllocateAnyPages,\r | |
256 | EfiBootServicesData,\r | |
257 | *PrpListNo,\r | |
258 | PrpListHost,\r | |
259 | 0\r | |
260 | );\r | |
261 | \r | |
262 | if (EFI_ERROR (Status)) {\r | |
263 | return NULL;\r | |
264 | }\r | |
265 | \r | |
266 | Bytes = EFI_PAGES_TO_SIZE (*PrpListNo);\r | |
267 | Status = PciIo->Map (\r | |
268 | PciIo,\r | |
269 | EfiPciIoOperationBusMasterCommonBuffer,\r | |
270 | *PrpListHost,\r | |
271 | &Bytes,\r | |
272 | &PrpListPhyAddr,\r | |
273 | Mapping\r | |
274 | );\r | |
275 | \r | |
276 | if (EFI_ERROR (Status) || (Bytes != EFI_PAGES_TO_SIZE (*PrpListNo))) {\r | |
277 | DEBUG ((EFI_D_ERROR, "NvmeCreatePrpList: create PrpList failure!\n"));\r | |
278 | goto EXIT;\r | |
279 | }\r | |
280 | //\r | |
281 | // Fill all PRP lists except of last one.\r | |
282 | //\r | |
283 | ZeroMem (*PrpListHost, Bytes);\r | |
284 | for (PrpListIndex = 0; PrpListIndex < *PrpListNo - 1; ++PrpListIndex) {\r | |
769402ef | 285 | PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r |
eb290d02 FT |
286 | \r |
287 | for (PrpEntryIndex = 0; PrpEntryIndex < PrpEntryNo; ++PrpEntryIndex) {\r | |
288 | if (PrpEntryIndex != PrpEntryNo - 1) {\r | |
289 | //\r | |
290 | // Fill all PRP entries except of last one.\r | |
291 | //\r | |
292 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r | |
293 | PhysicalAddr += EFI_PAGE_SIZE;\r | |
294 | } else {\r | |
295 | //\r | |
296 | // Fill last PRP entries with next PRP List pointer.\r | |
297 | //\r | |
298 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PrpListPhyAddr + (PrpListIndex + 1) * EFI_PAGE_SIZE;\r | |
299 | }\r | |
300 | }\r | |
301 | }\r | |
302 | //\r | |
303 | // Fill last PRP list.\r | |
304 | //\r | |
305 | PrpListBase = *(UINT64*)PrpListHost + PrpListIndex * EFI_PAGE_SIZE;\r | |
769402ef | 306 | for (PrpEntryIndex = 0; PrpEntryIndex < Remainder; ++PrpEntryIndex) {\r |
eb290d02 FT |
307 | *((UINT64*)(UINTN)PrpListBase + PrpEntryIndex) = PhysicalAddr;\r |
308 | PhysicalAddr += EFI_PAGE_SIZE;\r | |
309 | }\r | |
310 | \r | |
311 | return (VOID*)(UINTN)PrpListPhyAddr;\r | |
312 | \r | |
313 | EXIT:\r | |
314 | PciIo->FreeBuffer (PciIo, *PrpListNo, *PrpListHost);\r | |
315 | return NULL;\r | |
316 | }\r | |
317 | \r | |
318 | \r | |
319 | /**\r | |
320 | Sends an NVM Express Command Packet to an NVM Express controller or namespace. This function supports\r | |
d6c55989 | 321 | both blocking I/O and non-blocking I/O. The blocking I/O functionality is required, and the non-blocking\r |
eb290d02 FT |
322 | I/O functionality is optional.\r |
323 | \r | |
d6c55989 FT |
324 | \r |
325 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
326 | @param[in] NamespaceId A 32 bit namespace ID as defined in the NVMe specification to which the NVM Express Command\r | |
327 | Packet will be sent. A value of 0 denotes the NVM Express controller, a value of all 0xFF's\r | |
328 | (all bytes are 0xFF) in the namespace ID specifies that the command packet should be sent to\r | |
329 | all valid namespaces.\r | |
330 | @param[in,out] Packet A pointer to the NVM Express Command Packet.\r | |
331 | @param[in] Event If non-blocking I/O is not supported then Event is ignored, and blocking I/O is performed.\r | |
332 | If Event is NULL, then blocking I/O is performed. If Event is not NULL and non-blocking I/O\r | |
333 | is supported, then non-blocking I/O is performed, and Event will be signaled when the NVM\r | |
eb290d02 FT |
334 | Express Command Packet completes.\r |
335 | \r | |
336 | @retval EFI_SUCCESS The NVM Express Command Packet was sent by the host. TransferLength bytes were transferred\r | |
337 | to, or from DataBuffer.\r | |
338 | @retval EFI_BAD_BUFFER_SIZE The NVM Express Command Packet was not executed. The number of bytes that could be transferred\r | |
339 | is returned in TransferLength.\r | |
340 | @retval EFI_NOT_READY The NVM Express Command Packet could not be sent because the controller is not ready. The caller\r | |
341 | may retry again later.\r | |
342 | @retval EFI_DEVICE_ERROR A device error occurred while attempting to send the NVM Express Command Packet.\r | |
d6c55989 | 343 | @retval EFI_INVALID_PARAMETER NamespaceId or the contents of EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET are invalid. The NVM\r |
eb290d02 | 344 | Express Command Packet was not sent, so no additional status information is available.\r |
d6c55989 FT |
345 | @retval EFI_UNSUPPORTED The command described by the NVM Express Command Packet is not supported by the NVM Express\r |
346 | controller. The NVM Express Command Packet was not sent so no additional status information\r | |
347 | is available.\r | |
eb290d02 FT |
348 | @retval EFI_TIMEOUT A timeout occurred while waiting for the NVM Express Command Packet to execute.\r |
349 | \r | |
350 | **/\r | |
351 | EFI_STATUS\r | |
352 | EFIAPI\r | |
353 | NvmExpressPassThru (\r | |
d6c55989 | 354 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 355 | IN UINT32 NamespaceId,\r |
d6c55989 | 356 | IN OUT EFI_NVM_EXPRESS_PASS_THRU_COMMAND_PACKET *Packet,\r |
eb290d02 FT |
357 | IN EFI_EVENT Event OPTIONAL\r |
358 | )\r | |
359 | {\r | |
360 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r | |
361 | EFI_STATUS Status;\r | |
362 | EFI_PCI_IO_PROTOCOL *PciIo;\r | |
363 | NVME_SQ *Sq;\r | |
364 | NVME_CQ *Cq;\r | |
758ea946 | 365 | UINT16 QueueId;\r |
eb290d02 FT |
366 | UINT32 Bytes;\r |
367 | UINT16 Offset;\r | |
368 | EFI_EVENT TimerEvent;\r | |
369 | EFI_PCI_IO_PROTOCOL_OPERATION Flag;\r | |
370 | EFI_PHYSICAL_ADDRESS PhyAddr;\r | |
371 | VOID *MapData;\r | |
372 | VOID *MapMeta;\r | |
373 | VOID *MapPrpList;\r | |
374 | UINTN MapLength;\r | |
375 | UINT64 *Prp;\r | |
376 | VOID *PrpListHost;\r | |
377 | UINTN PrpListNo;\r | |
7b8883c6 | 378 | UINT32 Data;\r |
758ea946 HW |
379 | NVME_PASS_THRU_ASYNC_REQ *AsyncRequest;\r |
380 | EFI_TPL OldTpl;\r | |
eb290d02 FT |
381 | \r |
382 | //\r | |
383 | // check the data fields in Packet parameter.\r | |
384 | //\r | |
385 | if ((This == NULL) || (Packet == NULL)) {\r | |
386 | return EFI_INVALID_PARAMETER;\r | |
387 | }\r | |
388 | \r | |
d6c55989 | 389 | if ((Packet->NvmeCmd == NULL) || (Packet->NvmeCompletion == NULL)) {\r |
eb290d02 FT |
390 | return EFI_INVALID_PARAMETER;\r |
391 | }\r | |
392 | \r | |
d6c55989 | 393 | if (Packet->QueueType != NVME_ADMIN_QUEUE && Packet->QueueType != NVME_IO_QUEUE) {\r |
eb290d02 FT |
394 | return EFI_INVALID_PARAMETER;\r |
395 | }\r | |
396 | \r | |
397 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
398 | PciIo = Private->PciIo;\r | |
399 | MapData = NULL;\r | |
400 | MapMeta = NULL;\r | |
401 | MapPrpList = NULL;\r | |
402 | PrpListHost = NULL;\r | |
403 | PrpListNo = 0;\r | |
404 | Prp = NULL;\r | |
405 | TimerEvent = NULL;\r | |
406 | Status = EFI_SUCCESS;\r | |
407 | \r | |
758ea946 HW |
408 | if (Packet->QueueType == NVME_ADMIN_QUEUE) {\r |
409 | QueueId = 0;\r | |
410 | } else {\r | |
411 | if (Event == NULL) {\r | |
412 | QueueId = 1;\r | |
413 | } else {\r | |
414 | QueueId = 2;\r | |
415 | \r | |
416 | //\r | |
417 | // Submission queue full check.\r | |
418 | //\r | |
419 | if ((Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1) ==\r | |
420 | Private->AsyncSqHead) {\r | |
421 | return EFI_NOT_READY;\r | |
422 | }\r | |
423 | }\r | |
424 | }\r | |
425 | Sq = Private->SqBuffer[QueueId] + Private->SqTdbl[QueueId].Sqt;\r | |
426 | Cq = Private->CqBuffer[QueueId] + Private->CqHdbl[QueueId].Cqh;\r | |
eb290d02 FT |
427 | \r |
428 | if (Packet->NvmeCmd->Nsid != NamespaceId) {\r | |
429 | return EFI_INVALID_PARAMETER;\r | |
430 | }\r | |
431 | \r | |
432 | ZeroMem (Sq, sizeof (NVME_SQ));\r | |
d6c55989 FT |
433 | Sq->Opc = (UINT8)Packet->NvmeCmd->Cdw0.Opcode;\r |
434 | Sq->Fuse = (UINT8)Packet->NvmeCmd->Cdw0.FusedOperation;\r | |
758ea946 | 435 | Sq->Cid = Private->Cid[QueueId]++;\r |
eb290d02 FT |
436 | Sq->Nsid = Packet->NvmeCmd->Nsid;\r |
437 | \r | |
438 | //\r | |
439 | // Currently we only support PRP for data transfer, SGL is NOT supported.\r | |
440 | //\r | |
7b8883c6 FT |
441 | ASSERT (Sq->Psdt == 0);\r |
442 | if (Sq->Psdt != 0) {\r | |
eb290d02 FT |
443 | DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));\r |
444 | return EFI_UNSUPPORTED;\r | |
445 | }\r | |
446 | \r | |
447 | Sq->Prp[0] = (UINT64)(UINTN)Packet->TransferBuffer;\r | |
448 | //\r | |
449 | // If the NVMe cmd has data in or out, then mapping the user buffer to the PCI controller specific addresses.\r | |
450 | // Note here we don't handle data buffer for CreateIOSubmitionQueue and CreateIOCompletionQueue cmds because\r | |
451 | // these two cmds are special which requires their data buffer must support simultaneous access by both the\r | |
452 | // processor and a PCI Bus Master. It's caller's responsbility to ensure this.\r | |
453 | //\r | |
754b489b | 454 | if (((Sq->Opc & (BIT0 | BIT1)) != 0) && (Sq->Opc != NVME_ADMIN_CRIOCQ_CMD) && (Sq->Opc != NVME_ADMIN_CRIOSQ_CMD)) {\r |
eb290d02 FT |
455 | if ((Sq->Opc & BIT0) != 0) {\r |
456 | Flag = EfiPciIoOperationBusMasterRead;\r | |
457 | } else {\r | |
458 | Flag = EfiPciIoOperationBusMasterWrite;\r | |
459 | }\r | |
460 | \r | |
461 | MapLength = Packet->TransferLength;\r | |
462 | Status = PciIo->Map (\r | |
463 | PciIo,\r | |
464 | Flag,\r | |
465 | Packet->TransferBuffer,\r | |
466 | &MapLength,\r | |
467 | &PhyAddr,\r | |
468 | &MapData\r | |
469 | );\r | |
470 | if (EFI_ERROR (Status) || (Packet->TransferLength != MapLength)) {\r | |
471 | return EFI_OUT_OF_RESOURCES;\r | |
472 | }\r | |
473 | \r | |
474 | Sq->Prp[0] = PhyAddr;\r | |
475 | Sq->Prp[1] = 0;\r | |
476 | \r | |
477 | MapLength = Packet->MetadataLength;\r | |
478 | if(Packet->MetadataBuffer != NULL) {\r | |
479 | MapLength = Packet->MetadataLength;\r | |
480 | Status = PciIo->Map (\r | |
481 | PciIo,\r | |
482 | Flag,\r | |
483 | Packet->MetadataBuffer,\r | |
484 | &MapLength,\r | |
485 | &PhyAddr,\r | |
486 | &MapMeta\r | |
487 | );\r | |
488 | if (EFI_ERROR (Status) || (Packet->MetadataLength != MapLength)) {\r | |
489 | PciIo->Unmap (\r | |
490 | PciIo,\r | |
491 | MapData\r | |
492 | );\r | |
493 | \r | |
494 | return EFI_OUT_OF_RESOURCES;\r | |
495 | }\r | |
496 | Sq->Mptr = PhyAddr;\r | |
497 | }\r | |
498 | }\r | |
499 | //\r | |
500 | // If the buffer size spans more than two memory pages (page size as defined in CC.Mps),\r | |
501 | // then build a PRP list in the second PRP submission queue entry.\r | |
502 | //\r | |
503 | Offset = ((UINT16)Sq->Prp[0]) & (EFI_PAGE_SIZE - 1);\r | |
504 | Bytes = Packet->TransferLength;\r | |
505 | \r | |
506 | if ((Offset + Bytes) > (EFI_PAGE_SIZE * 2)) {\r | |
507 | //\r | |
508 | // Create PrpList for remaining data buffer.\r | |
509 | //\r | |
510 | PhyAddr = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r | |
511 | Prp = NvmeCreatePrpList (PciIo, PhyAddr, EFI_SIZE_TO_PAGES(Offset + Bytes) - 1, &PrpListHost, &PrpListNo, &MapPrpList);\r | |
512 | if (Prp == NULL) {\r | |
513 | goto EXIT;\r | |
514 | }\r | |
515 | \r | |
516 | Sq->Prp[1] = (UINT64)(UINTN)Prp;\r | |
517 | } else if ((Offset + Bytes) > EFI_PAGE_SIZE) {\r | |
518 | Sq->Prp[1] = (Sq->Prp[0] + EFI_PAGE_SIZE) & ~(EFI_PAGE_SIZE - 1);\r | |
519 | }\r | |
520 | \r | |
d6c55989 FT |
521 | if(Packet->NvmeCmd->Flags & CDW2_VALID) {\r |
522 | Sq->Rsvd2 = (UINT64)Packet->NvmeCmd->Cdw2;\r | |
523 | }\r | |
524 | if(Packet->NvmeCmd->Flags & CDW3_VALID) {\r | |
525 | Sq->Rsvd2 |= LShiftU64 ((UINT64)Packet->NvmeCmd->Cdw3, 32);\r | |
526 | }\r | |
eb290d02 FT |
527 | if(Packet->NvmeCmd->Flags & CDW10_VALID) {\r |
528 | Sq->Payload.Raw.Cdw10 = Packet->NvmeCmd->Cdw10;\r | |
529 | }\r | |
530 | if(Packet->NvmeCmd->Flags & CDW11_VALID) {\r | |
531 | Sq->Payload.Raw.Cdw11 = Packet->NvmeCmd->Cdw11;\r | |
532 | }\r | |
533 | if(Packet->NvmeCmd->Flags & CDW12_VALID) {\r | |
534 | Sq->Payload.Raw.Cdw12 = Packet->NvmeCmd->Cdw12;\r | |
535 | }\r | |
536 | if(Packet->NvmeCmd->Flags & CDW13_VALID) {\r | |
537 | Sq->Payload.Raw.Cdw13 = Packet->NvmeCmd->Cdw13;\r | |
538 | }\r | |
539 | if(Packet->NvmeCmd->Flags & CDW14_VALID) {\r | |
540 | Sq->Payload.Raw.Cdw14 = Packet->NvmeCmd->Cdw14;\r | |
541 | }\r | |
542 | if(Packet->NvmeCmd->Flags & CDW15_VALID) {\r | |
543 | Sq->Payload.Raw.Cdw15 = Packet->NvmeCmd->Cdw15;\r | |
544 | }\r | |
545 | \r | |
546 | //\r | |
547 | // Ring the submission queue doorbell.\r | |
548 | //\r | |
758ea946 HW |
549 | if (Event != NULL) {\r |
550 | Private->SqTdbl[QueueId].Sqt =\r | |
551 | (Private->SqTdbl[QueueId].Sqt + 1) % (NVME_ASYNC_CSQ_SIZE + 1);\r | |
552 | } else {\r | |
553 | Private->SqTdbl[QueueId].Sqt ^= 1;\r | |
554 | }\r | |
555 | Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[QueueId]);\r | |
eb290d02 FT |
556 | PciIo->Mem.Write (\r |
557 | PciIo,\r | |
558 | EfiPciIoWidthUint32,\r | |
559 | NVME_BAR,\r | |
758ea946 | 560 | NVME_SQTDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r |
eb290d02 | 561 | 1,\r |
7b8883c6 | 562 | &Data\r |
eb290d02 FT |
563 | );\r |
564 | \r | |
758ea946 HW |
565 | //\r |
566 | // For non-blocking requests, return directly if the command is placed\r | |
567 | // in the submission queue.\r | |
568 | //\r | |
569 | if (Event != NULL) {\r | |
570 | AsyncRequest = AllocateZeroPool (sizeof (NVME_PASS_THRU_ASYNC_REQ));\r | |
571 | if (AsyncRequest == NULL) {\r | |
572 | Status = EFI_DEVICE_ERROR;\r | |
573 | goto EXIT;\r | |
574 | }\r | |
575 | \r | |
576 | AsyncRequest->Signature = NVME_PASS_THRU_ASYNC_REQ_SIG;\r | |
577 | AsyncRequest->Packet = Packet;\r | |
578 | AsyncRequest->CommandId = Sq->Cid;\r | |
579 | AsyncRequest->CallerEvent = Event;\r | |
580 | \r | |
581 | OldTpl = gBS->RaiseTPL (TPL_NOTIFY);\r | |
582 | InsertTailList (&Private->AsyncPassThruQueue, &AsyncRequest->Link);\r | |
583 | gBS->RestoreTPL (OldTpl);\r | |
584 | \r | |
585 | return EFI_SUCCESS;\r | |
586 | }\r | |
587 | \r | |
eb290d02 FT |
588 | Status = gBS->CreateEvent (\r |
589 | EVT_TIMER,\r | |
590 | TPL_CALLBACK,\r | |
591 | NULL,\r | |
592 | NULL,\r | |
593 | &TimerEvent\r | |
594 | );\r | |
595 | if (EFI_ERROR (Status)) {\r | |
596 | goto EXIT;\r | |
597 | }\r | |
598 | \r | |
599 | Status = gBS->SetTimer(TimerEvent, TimerRelative, Packet->CommandTimeout);\r | |
600 | \r | |
601 | if (EFI_ERROR(Status)) {\r | |
eb290d02 FT |
602 | goto EXIT;\r |
603 | }\r | |
604 | \r | |
605 | //\r | |
606 | // Wait for completion queue to get filled in.\r | |
607 | //\r | |
608 | Status = EFI_TIMEOUT;\r | |
eb290d02 | 609 | while (EFI_ERROR (gBS->CheckEvent (TimerEvent))) {\r |
758ea946 | 610 | if (Cq->Pt != Private->Pt[QueueId]) {\r |
eb290d02 | 611 | Status = EFI_SUCCESS;\r |
eb290d02 FT |
612 | break;\r |
613 | }\r | |
614 | }\r | |
615 | \r | |
eb290d02 | 616 | //\r |
754b489b | 617 | // Check the NVMe cmd execution result\r |
eb290d02 | 618 | //\r |
754b489b TF |
619 | if (Status != EFI_TIMEOUT) {\r |
620 | if ((Cq->Sct == 0) && (Cq->Sc == 0)) {\r | |
621 | Status = EFI_SUCCESS;\r | |
622 | } else {\r | |
623 | Status = EFI_DEVICE_ERROR;\r | |
624 | //\r | |
625 | // Copy the Respose Queue entry for this command to the callers response buffer\r | |
626 | //\r | |
627 | CopyMem(Packet->NvmeCompletion, Cq, sizeof(EFI_NVM_EXPRESS_COMPLETION));\r | |
628 | \r | |
629 | //\r | |
630 | // Dump every completion entry status for debugging.\r | |
631 | //\r | |
632 | DEBUG_CODE_BEGIN();\r | |
633 | NvmeDumpStatus(Cq);\r | |
634 | DEBUG_CODE_END();\r | |
635 | }\r | |
636 | }\r | |
eb290d02 | 637 | \r |
758ea946 HW |
638 | if ((Private->CqHdbl[QueueId].Cqh ^= 1) == 0) {\r |
639 | Private->Pt[QueueId] ^= 1;\r | |
754b489b | 640 | }\r |
eb290d02 | 641 | \r |
758ea946 | 642 | Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[QueueId]);\r |
eb290d02 FT |
643 | PciIo->Mem.Write (\r |
644 | PciIo,\r | |
645 | EfiPciIoWidthUint32,\r | |
646 | NVME_BAR,\r | |
758ea946 | 647 | NVME_CQHDBL_OFFSET(QueueId, Private->Cap.Dstrd),\r |
eb290d02 | 648 | 1,\r |
7b8883c6 | 649 | &Data\r |
eb290d02 FT |
650 | );\r |
651 | \r | |
652 | EXIT:\r | |
653 | if (MapData != NULL) {\r | |
654 | PciIo->Unmap (\r | |
655 | PciIo,\r | |
656 | MapData\r | |
657 | );\r | |
658 | }\r | |
659 | \r | |
660 | if (MapMeta != NULL) {\r | |
661 | PciIo->Unmap (\r | |
662 | PciIo,\r | |
663 | MapMeta\r | |
664 | );\r | |
665 | }\r | |
666 | \r | |
667 | if (MapPrpList != NULL) {\r | |
668 | PciIo->Unmap (\r | |
669 | PciIo,\r | |
670 | MapPrpList\r | |
671 | );\r | |
672 | }\r | |
673 | \r | |
674 | if (Prp != NULL) {\r | |
675 | PciIo->FreeBuffer (PciIo, PrpListNo, PrpListHost);\r | |
676 | }\r | |
677 | \r | |
678 | if (TimerEvent != NULL) {\r | |
679 | gBS->CloseEvent (TimerEvent);\r | |
680 | }\r | |
681 | return Status;\r | |
682 | }\r | |
683 | \r | |
684 | /**\r | |
d6c55989 | 685 | Used to retrieve the next namespace ID for this NVM Express controller.\r |
eb290d02 | 686 | \r |
d6c55989 FT |
687 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNextNamespace() function retrieves the next valid\r |
688 | namespace ID on this NVM Express controller.\r | |
eb290d02 | 689 | \r |
d6c55989 FT |
690 | If on input the value pointed to by NamespaceId is 0xFFFFFFFF, then the first valid namespace\r |
691 | ID defined on the NVM Express controller is returned in the location pointed to by NamespaceId\r | |
692 | and a status of EFI_SUCCESS is returned.\r | |
eb290d02 | 693 | \r |
d6c55989 FT |
694 | If on input the value pointed to by NamespaceId is an invalid namespace ID other than 0xFFFFFFFF,\r |
695 | then EFI_INVALID_PARAMETER is returned.\r | |
eb290d02 | 696 | \r |
d6c55989 FT |
697 | If on input the value pointed to by NamespaceId is a valid namespace ID, then the next valid\r |
698 | namespace ID on the NVM Express controller is returned in the location pointed to by NamespaceId,\r | |
699 | and EFI_SUCCESS is returned.\r | |
eb290d02 | 700 | \r |
d6c55989 FT |
701 | If the value pointed to by NamespaceId is the namespace ID of the last namespace on the NVM\r |
702 | Express controller, then EFI_NOT_FOUND is returned.\r | |
703 | \r | |
704 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
eb290d02 FT |
705 | @param[in,out] NamespaceId On input, a pointer to a legal NamespaceId for an NVM Express\r |
706 | namespace present on the NVM Express controller. On output, a\r | |
707 | pointer to the next NamespaceId of an NVM Express namespace on\r | |
708 | an NVM Express controller. An input value of 0xFFFFFFFF retrieves\r | |
709 | the first NamespaceId for an NVM Express namespace present on an\r | |
710 | NVM Express controller.\r | |
eb290d02 | 711 | \r |
d6c55989 | 712 | @retval EFI_SUCCESS The Namespace ID of the next Namespace was returned.\r |
eb290d02 | 713 | @retval EFI_NOT_FOUND There are no more namespaces defined on this controller.\r |
d6c55989 | 714 | @retval EFI_INVALID_PARAMETER NamespaceId is an invalid value other than 0xFFFFFFFF.\r |
eb290d02 FT |
715 | \r |
716 | **/\r | |
717 | EFI_STATUS\r | |
718 | EFIAPI\r | |
719 | NvmExpressGetNextNamespace (\r | |
d6c55989 FT |
720 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
721 | IN OUT UINT32 *NamespaceId\r | |
eb290d02 FT |
722 | )\r |
723 | {\r | |
724 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r | |
725 | NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r | |
726 | UINT32 NextNamespaceId;\r | |
727 | EFI_STATUS Status;\r | |
728 | \r | |
729 | if ((This == NULL) || (NamespaceId == NULL)) {\r | |
730 | return EFI_INVALID_PARAMETER;\r | |
731 | }\r | |
732 | \r | |
733 | NamespaceData = NULL;\r | |
734 | Status = EFI_NOT_FOUND;\r | |
735 | \r | |
736 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
737 | //\r | |
738 | // If the NamespaceId input value is 0xFFFFFFFF, then get the first valid namespace ID\r | |
739 | //\r | |
740 | if (*NamespaceId == 0xFFFFFFFF) {\r | |
741 | //\r | |
742 | // Start with the first namespace ID\r | |
743 | //\r | |
744 | NextNamespaceId = 1;\r | |
745 | //\r | |
746 | // Allocate buffer for Identify Namespace data.\r | |
747 | //\r | |
748 | NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
749 | \r | |
750 | if (NamespaceData == NULL) {\r | |
751 | return EFI_NOT_FOUND;\r | |
752 | }\r | |
753 | \r | |
754 | Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r | |
755 | if (EFI_ERROR(Status)) {\r | |
756 | goto Done;\r | |
757 | }\r | |
758 | \r | |
759 | *NamespaceId = NextNamespaceId;\r | |
eb290d02 FT |
760 | } else {\r |
761 | if (*NamespaceId >= Private->ControllerData->Nn) {\r | |
762 | return EFI_INVALID_PARAMETER;\r | |
763 | }\r | |
764 | \r | |
765 | NextNamespaceId = *NamespaceId + 1;\r | |
766 | //\r | |
767 | // Allocate buffer for Identify Namespace data.\r | |
768 | //\r | |
769 | NamespaceData = (NVME_ADMIN_NAMESPACE_DATA *)AllocateZeroPool (sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
770 | if (NamespaceData == NULL) {\r | |
771 | return EFI_NOT_FOUND;\r | |
772 | }\r | |
773 | \r | |
774 | Status = NvmeIdentifyNamespace (Private, NextNamespaceId, NamespaceData);\r | |
775 | if (EFI_ERROR(Status)) {\r | |
776 | goto Done;\r | |
777 | }\r | |
778 | \r | |
779 | *NamespaceId = NextNamespaceId;\r | |
eb290d02 FT |
780 | }\r |
781 | \r | |
782 | Done:\r | |
783 | if (NamespaceData != NULL) {\r | |
784 | FreePool(NamespaceData);\r | |
785 | }\r | |
786 | \r | |
787 | return Status;\r | |
788 | }\r | |
789 | \r | |
790 | /**\r | |
d6c55989 FT |
791 | Used to translate a device path node to a namespace ID.\r |
792 | \r | |
793 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.GetNamespace() function determines the namespace ID associated with the\r | |
794 | namespace described by DevicePath.\r | |
eb290d02 | 795 | \r |
d6c55989 FT |
796 | If DevicePath is a device path node type that the NVM Express Pass Thru driver supports, then the NVM Express\r |
797 | Pass Thru driver will attempt to translate the contents DevicePath into a namespace ID.\r | |
eb290d02 | 798 | \r |
d6c55989 FT |
799 | If this translation is successful, then that namespace ID is returned in NamespaceId, and EFI_SUCCESS is returned\r |
800 | \r | |
801 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r | |
eb290d02 FT |
802 | @param[in] DevicePath A pointer to the device path node that describes an NVM Express namespace on\r |
803 | the NVM Express controller.\r | |
804 | @param[out] NamespaceId The NVM Express namespace ID contained in the device path node.\r | |
eb290d02 | 805 | \r |
d6c55989 FT |
806 | @retval EFI_SUCCESS DevicePath was successfully translated to NamespaceId.\r |
807 | @retval EFI_INVALID_PARAMETER If DevicePath or NamespaceId are NULL, then EFI_INVALID_PARAMETER is returned.\r | |
eb290d02 FT |
808 | @retval EFI_UNSUPPORTED If DevicePath is not a device path node type that the NVM Express Pass Thru driver\r |
809 | supports, then EFI_UNSUPPORTED is returned.\r | |
d6c55989 FT |
810 | @retval EFI_NOT_FOUND If DevicePath is a device path node type that the NVM Express Pass Thru driver\r |
811 | supports, but there is not a valid translation from DevicePath to a namespace ID,\r | |
812 | then EFI_NOT_FOUND is returned.\r | |
eb290d02 FT |
813 | **/\r |
814 | EFI_STATUS\r | |
815 | EFIAPI\r | |
816 | NvmExpressGetNamespace (\r | |
d6c55989 | 817 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 818 | IN EFI_DEVICE_PATH_PROTOCOL *DevicePath,\r |
d6c55989 | 819 | OUT UINT32 *NamespaceId\r |
eb290d02 FT |
820 | )\r |
821 | {\r | |
822 | NVME_NAMESPACE_DEVICE_PATH *Node;\r | |
823 | \r | |
d6c55989 | 824 | if ((This == NULL) || (DevicePath == NULL) || (NamespaceId == NULL)) {\r |
eb290d02 FT |
825 | return EFI_INVALID_PARAMETER;\r |
826 | }\r | |
827 | \r | |
828 | if (DevicePath->Type != MESSAGING_DEVICE_PATH) {\r | |
829 | return EFI_UNSUPPORTED;\r | |
830 | }\r | |
831 | \r | |
832 | Node = (NVME_NAMESPACE_DEVICE_PATH *)DevicePath;\r | |
833 | \r | |
834 | if (DevicePath->SubType == MSG_NVME_NAMESPACE_DP) {\r | |
835 | if (DevicePathNodeLength(DevicePath) != sizeof(NVME_NAMESPACE_DEVICE_PATH)) {\r | |
836 | return EFI_NOT_FOUND;\r | |
837 | }\r | |
838 | \r | |
d6c55989 | 839 | *NamespaceId = Node->NamespaceId;\r |
eb290d02 FT |
840 | \r |
841 | return EFI_SUCCESS;\r | |
842 | } else {\r | |
843 | return EFI_UNSUPPORTED;\r | |
844 | }\r | |
845 | }\r | |
846 | \r | |
847 | /**\r | |
848 | Used to allocate and build a device path node for an NVM Express namespace on an NVM Express controller.\r | |
849 | \r | |
d6c55989 | 850 | The EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL.BuildDevicePath() function allocates and builds a single device\r |
eb290d02 FT |
851 | path node for the NVM Express namespace specified by NamespaceId.\r |
852 | \r | |
d6c55989 | 853 | If the NamespaceId is not valid, then EFI_NOT_FOUND is returned.\r |
eb290d02 FT |
854 | \r |
855 | If DevicePath is NULL, then EFI_INVALID_PARAMETER is returned.\r | |
856 | \r | |
857 | If there are not enough resources to allocate the device path node, then EFI_OUT_OF_RESOURCES is returned.\r | |
858 | \r | |
859 | Otherwise, DevicePath is allocated with the boot service AllocatePool(), the contents of DevicePath are\r | |
860 | initialized to describe the NVM Express namespace specified by NamespaceId, and EFI_SUCCESS is returned.\r | |
861 | \r | |
d6c55989 | 862 | @param[in] This A pointer to the EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL instance.\r |
eb290d02 FT |
863 | @param[in] NamespaceId The NVM Express namespace ID for which a device path node is to be\r |
864 | allocated and built. Caller must set the NamespaceId to zero if the\r | |
865 | device path node will contain a valid UUID.\r | |
eb290d02 FT |
866 | @param[in,out] DevicePath A pointer to a single device path node that describes the NVM Express\r |
867 | namespace specified by NamespaceId. This function is responsible for\r | |
868 | allocating the buffer DevicePath with the boot service AllocatePool().\r | |
869 | It is the caller's responsibility to free DevicePath when the caller\r | |
870 | is finished with DevicePath.\r | |
871 | @retval EFI_SUCCESS The device path node that describes the NVM Express namespace specified\r | |
872 | by NamespaceId was allocated and returned in DevicePath.\r | |
d6c55989 | 873 | @retval EFI_NOT_FOUND The NamespaceId is not valid.\r |
eb290d02 FT |
874 | @retval EFI_INVALID_PARAMETER DevicePath is NULL.\r |
875 | @retval EFI_OUT_OF_RESOURCES There are not enough resources to allocate the DevicePath node.\r | |
876 | \r | |
877 | **/\r | |
878 | EFI_STATUS\r | |
879 | EFIAPI\r | |
880 | NvmExpressBuildDevicePath (\r | |
d6c55989 | 881 | IN EFI_NVM_EXPRESS_PASS_THRU_PROTOCOL *This,\r |
eb290d02 | 882 | IN UINT32 NamespaceId,\r |
eb290d02 FT |
883 | IN OUT EFI_DEVICE_PATH_PROTOCOL **DevicePath\r |
884 | )\r | |
885 | {\r | |
eb290d02 | 886 | NVME_NAMESPACE_DEVICE_PATH *Node;\r |
d6c55989 FT |
887 | NVME_CONTROLLER_PRIVATE_DATA *Private;\r |
888 | EFI_STATUS Status;\r | |
889 | NVME_ADMIN_NAMESPACE_DATA *NamespaceData;\r | |
eb290d02 FT |
890 | \r |
891 | //\r | |
892 | // Validate parameters\r | |
893 | //\r | |
894 | if ((This == NULL) || (DevicePath == NULL)) {\r | |
895 | return EFI_INVALID_PARAMETER;\r | |
896 | }\r | |
897 | \r | |
eb290d02 FT |
898 | if (NamespaceId == 0) {\r |
899 | return EFI_NOT_FOUND;\r | |
900 | }\r | |
901 | \r | |
d6c55989 FT |
902 | Status = EFI_SUCCESS;\r |
903 | Private = NVME_CONTROLLER_PRIVATE_DATA_FROM_PASS_THRU (This);\r | |
eb290d02 | 904 | \r |
d6c55989 | 905 | Node = (NVME_NAMESPACE_DEVICE_PATH *)AllocateZeroPool (sizeof (NVME_NAMESPACE_DEVICE_PATH));\r |
eb290d02 FT |
906 | if (Node == NULL) {\r |
907 | return EFI_OUT_OF_RESOURCES;\r | |
908 | }\r | |
909 | \r | |
910 | Node->Header.Type = MESSAGING_DEVICE_PATH;\r | |
911 | Node->Header.SubType = MSG_NVME_NAMESPACE_DP;\r | |
912 | SetDevicePathNodeLength (&Node->Header, sizeof (NVME_NAMESPACE_DEVICE_PATH));\r | |
913 | Node->NamespaceId = NamespaceId;\r | |
d6c55989 FT |
914 | \r |
915 | //\r | |
916 | // Allocate a buffer for Identify Namespace data.\r | |
917 | //\r | |
918 | NamespaceData = NULL;\r | |
919 | NamespaceData = AllocateZeroPool(sizeof (NVME_ADMIN_NAMESPACE_DATA));\r | |
920 | if(NamespaceData == NULL) {\r | |
921 | Status = EFI_OUT_OF_RESOURCES;\r | |
922 | goto Exit;\r | |
923 | }\r | |
924 | \r | |
925 | //\r | |
926 | // Get UUID from specified Identify Namespace data.\r | |
927 | //\r | |
928 | Status = NvmeIdentifyNamespace (\r | |
929 | Private,\r | |
930 | NamespaceId,\r | |
931 | (VOID *)NamespaceData\r | |
932 | );\r | |
933 | \r | |
934 | if (EFI_ERROR(Status)) {\r | |
935 | goto Exit;\r | |
936 | }\r | |
937 | \r | |
938 | Node->NamespaceUuid = NamespaceData->Eui64;\r | |
eb290d02 FT |
939 | \r |
940 | *DevicePath = (EFI_DEVICE_PATH_PROTOCOL *)Node;\r | |
d6c55989 FT |
941 | \r |
942 | Exit:\r | |
943 | if(NamespaceData != NULL) {\r | |
944 | FreePool (NamespaceData);\r | |
945 | }\r | |
946 | \r | |
947 | if (EFI_ERROR (Status)) {\r | |
948 | FreePool (Node);\r | |
949 | }\r | |
950 | \r | |
951 | return Status;\r | |
eb290d02 FT |
952 | }\r |
953 | \r |