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9060e3ec 1/** @file\r
2 EFI PCI IO protocol functions declaration for PCI Bus module.\r
3\r
6fbaed1f 4Copyright (c) 2006 - 2017, Intel Corporation. All rights reserved.<BR>\r
cd5ebaa0 5This program and the accompanying materials\r
9060e3ec 6are licensed and made available under the terms and conditions of the BSD License\r
7which accompanies this distribution. The full text of the license may be found at\r
8http://opensource.org/licenses/bsd-license.php\r
9\r
10THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
11WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
12\r
13**/\r
14\r
15#ifndef _EFI_PCI_IO_PROTOCOL_H_\r
16#define _EFI_PCI_IO_PROTOCOL_H_\r
17\r
18/**\r
19 Initializes a PCI I/O Instance.\r
20\r
21 @param PciIoDevice Pci device instance.\r
22\r
23**/\r
24VOID\r
25InitializePciIoInstance (\r
26 IN PCI_IO_DEVICE *PciIoDevice\r
27 );\r
28\r
29/**\r
30 Verifies access to a PCI Base Address Register (BAR).\r
31\r
32 @param PciIoDevice Pci device instance.\r
33 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
34 base address for the memory or I/O operation to perform.\r
35 @param Type Operation type could be memory or I/O.\r
36 @param Width Signifies the width of the memory or I/O operations.\r
37 @param Count The number of memory or I/O operations to perform.\r
38 @param Offset The offset within the PCI configuration space for the PCI controller.\r
39\r
40 @retval EFI_INVALID_PARAMETER Invalid Width/BarIndex or Bar type.\r
41 @retval EFI_SUCCESS Successfully verified.\r
42\r
43**/\r
44EFI_STATUS\r
45PciIoVerifyBarAccess (\r
46 IN PCI_IO_DEVICE *PciIoDevice,\r
47 IN UINT8 BarIndex,\r
48 IN PCI_BAR_TYPE Type,\r
49 IN IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
50 IN IN UINTN Count,\r
51 IN UINT64 *Offset\r
52 );\r
53\r
54/**\r
55 Verifies access to a PCI Configuration Header.\r
56\r
57 @param PciIoDevice Pci device instance.\r
58 @param Width Signifies the width of the memory or I/O operations.\r
59 @param Count The number of memory or I/O operations to perform.\r
60 @param Offset The offset within the PCI configuration space for the PCI controller.\r
61\r
62 @retval EFI_INVALID_PARAMETER Invalid Width\r
63 @retval EFI_UNSUPPORTED Offset overflowed.\r
64 @retval EFI_SUCCESS Successfully verified.\r
65\r
66**/\r
67EFI_STATUS\r
68PciIoVerifyConfigAccess (\r
69 IN PCI_IO_DEVICE *PciIoDevice,\r
70 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
71 IN UINTN Count,\r
72 IN UINT64 *Offset\r
73 );\r
74\r
75/**\r
76 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
77 satisfied or after a defined duration.\r
78\r
79 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
80 @param Width Signifies the width of the memory or I/O operations.\r
81 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
82 base address for the memory operation to perform.\r
83 @param Offset The offset within the selected BAR to start the memory operation.\r
84 @param Mask Mask used for the polling criteria.\r
85 @param Value The comparison value used for the polling exit criteria.\r
86 @param Delay The number of 100 ns units to poll.\r
87 @param Result Pointer to the last value read from the memory location.\r
88\r
89 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
90 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
91 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
92 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
93 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
94 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
95\r
96**/\r
97EFI_STATUS\r
98EFIAPI\r
99PciIoPollMem (\r
100 IN EFI_PCI_IO_PROTOCOL *This,\r
101 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
102 IN UINT8 BarIndex,\r
103 IN UINT64 Offset,\r
104 IN UINT64 Mask,\r
105 IN UINT64 Value,\r
106 IN UINT64 Delay,\r
107 OUT UINT64 *Result\r
108 );\r
109\r
110/**\r
111 Reads from the memory space of a PCI controller. Returns either when the polling exit criteria is\r
112 satisfied or after a defined duration.\r
113\r
114 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
115 @param Width Signifies the width of the memory or I/O operations.\r
116 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
117 base address for the memory operation to perform.\r
118 @param Offset The offset within the selected BAR to start the memory operation.\r
119 @param Mask Mask used for the polling criteria.\r
120 @param Value The comparison value used for the polling exit criteria.\r
121 @param Delay The number of 100 ns units to poll.\r
122 @param Result Pointer to the last value read from the memory location.\r
123\r
124 @retval EFI_SUCCESS The last data returned from the access matched the poll exit criteria.\r
125 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
126 @retval EFI_UNSUPPORTED Offset is not valid for the BarIndex of this PCI controller.\r
127 @retval EFI_TIMEOUT Delay expired before a match occurred.\r
128 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
129 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
130\r
131**/\r
132EFI_STATUS\r
133EFIAPI\r
134PciIoPollIo (\r
135 IN EFI_PCI_IO_PROTOCOL *This,\r
136 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
137 IN UINT8 BarIndex,\r
138 IN UINT64 Offset,\r
139 IN UINT64 Mask,\r
140 IN UINT64 Value,\r
141 IN UINT64 Delay,\r
142 OUT UINT64 *Result\r
143 );\r
144\r
145/**\r
146 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
147\r
148 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
149 @param Width Signifies the width of the memory or I/O operations.\r
150 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
151 base address for the memory or I/O operation to perform.\r
152 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
153 @param Count The number of memory or I/O operations to perform.\r
154 @param Buffer For read operations, the destination buffer to store the results. For write\r
155 operations, the source buffer to write data from.\r
156\r
157 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
158 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
159 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
160 valid for the PCI BAR specified by BarIndex.\r
161 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
162 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
163\r
164**/\r
165EFI_STATUS\r
166EFIAPI\r
167PciIoMemRead (\r
168 IN EFI_PCI_IO_PROTOCOL *This,\r
169 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
170 IN UINT8 BarIndex,\r
171 IN UINT64 Offset,\r
172 IN UINTN Count,\r
173 IN OUT VOID *Buffer\r
174 );\r
175\r
176/**\r
177 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
178\r
179 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
180 @param Width Signifies the width of the memory or I/O operations.\r
181 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
182 base address for the memory or I/O operation to perform.\r
183 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
184 @param Count The number of memory or I/O operations to perform.\r
185 @param Buffer For read operations, the destination buffer to store the results. For write\r
186 operations, the source buffer to write data from.\r
187\r
188 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
189 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
190 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
191 valid for the PCI BAR specified by BarIndex.\r
192 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
193 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
194\r
195**/\r
196EFI_STATUS\r
197EFIAPI\r
198PciIoMemWrite (\r
199 IN EFI_PCI_IO_PROTOCOL *This,\r
200 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
201 IN UINT8 BarIndex,\r
202 IN UINT64 Offset,\r
203 IN UINTN Count,\r
204 IN OUT VOID *Buffer\r
205 );\r
206\r
207/**\r
208 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
209\r
210 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
211 @param Width Signifies the width of the memory or I/O operations.\r
212 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
213 base address for the memory or I/O operation to perform.\r
214 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
215 @param Count The number of memory or I/O operations to perform.\r
216 @param Buffer For read operations, the destination buffer to store the results. For write\r
217 operations, the source buffer to write data from.\r
218\r
219 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
220 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
221 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
222 valid for the PCI BAR specified by BarIndex.\r
223 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
224 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
225\r
226**/\r
227EFI_STATUS\r
228EFIAPI\r
229PciIoIoRead (\r
230 IN EFI_PCI_IO_PROTOCOL *This,\r
231 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
232 IN UINT8 BarIndex,\r
233 IN UINT64 Offset,\r
234 IN UINTN Count,\r
235 IN OUT VOID *Buffer\r
236 );\r
237\r
238/**\r
239 Enable a PCI driver to access PCI controller registers in the PCI memory or I/O space.\r
240\r
241 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
242 @param Width Signifies the width of the memory or I/O operations.\r
243 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
244 base address for the memory or I/O operation to perform.\r
245 @param Offset The offset within the selected BAR to start the memory or I/O operation.\r
246 @param Count The number of memory or I/O operations to perform.\r
247 @param Buffer For read operations, the destination buffer to store the results. For write\r
248 operations, the source buffer to write data from.\r
249\r
250 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
251 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
252 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
253 valid for the PCI BAR specified by BarIndex.\r
254 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
255 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
256\r
257**/\r
258EFI_STATUS\r
259EFIAPI\r
260PciIoIoWrite (\r
261 IN EFI_PCI_IO_PROTOCOL *This,\r
262 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
263 IN UINT8 BarIndex,\r
264 IN UINT64 Offset,\r
265 IN UINTN Count,\r
266 IN OUT VOID *Buffer\r
267 );\r
268\r
269/**\r
270 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
271\r
272 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
273 @param Width Signifies the width of the memory operations.\r
274 @param Offset The offset within the PCI configuration space for the PCI controller.\r
275 @param Count The number of PCI configuration operations to perform.\r
276 @param Buffer For read operations, the destination buffer to store the results. For write\r
277 operations, the source buffer to write data from.\r
278\r
279\r
280 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
281 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
282 valid for the PCI configuration header of the PCI controller.\r
283 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
284 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
285\r
286**/\r
287EFI_STATUS\r
288EFIAPI\r
289PciIoConfigRead (\r
290 IN EFI_PCI_IO_PROTOCOL *This,\r
291 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
292 IN UINT32 Offset,\r
293 IN UINTN Count,\r
294 IN OUT VOID *Buffer\r
295 );\r
296\r
297/**\r
298 Enable a PCI driver to access PCI controller registers in PCI configuration space.\r
299\r
300 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
301 @param Width Signifies the width of the memory operations.\r
302 @param Offset The offset within the PCI configuration space for the PCI controller.\r
303 @param Count The number of PCI configuration operations to perform.\r
304 @param Buffer For read operations, the destination buffer to store the results. For write\r
305 operations, the source buffer to write data from.\r
306\r
307\r
308 @retval EFI_SUCCESS The data was read from or written to the PCI controller.\r
309 @retval EFI_UNSUPPORTED The address range specified by Offset, Width, and Count is not\r
310 valid for the PCI configuration header of the PCI controller.\r
311 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
312 @retval EFI_INVALID_PARAMETER Buffer is NULL or Width is invalid.\r
313\r
314**/\r
315EFI_STATUS\r
316EFIAPI\r
317PciIoConfigWrite (\r
318 IN EFI_PCI_IO_PROTOCOL *This,\r
319 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
320 IN UINT32 Offset,\r
321 IN UINTN Count,\r
322 IN OUT VOID *Buffer\r
323 );\r
324\r
325/**\r
326 Enables a PCI driver to copy one region of PCI memory space to another region of PCI\r
327 memory space.\r
328\r
329 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
330 @param Width Signifies the width of the memory operations.\r
331 @param DestBarIndex The BAR index in the standard PCI Configuration header to use as the\r
332 base address for the memory operation to perform.\r
333 @param DestOffset The destination offset within the BAR specified by DestBarIndex to\r
334 start the memory writes for the copy operation.\r
335 @param SrcBarIndex The BAR index in the standard PCI Configuration header to use as the\r
336 base address for the memory operation to perform.\r
337 @param SrcOffset The source offset within the BAR specified by SrcBarIndex to start\r
338 the memory reads for the copy operation.\r
339 @param Count The number of memory operations to perform. Bytes moved is Width\r
340 size * Count, starting at DestOffset and SrcOffset.\r
341\r
342 @retval EFI_SUCCESS The data was copied from one memory region to another memory region.\r
343 @retval EFI_UNSUPPORTED DestBarIndex not valid for this PCI controller.\r
344 @retval EFI_UNSUPPORTED SrcBarIndex not valid for this PCI controller.\r
345 @retval EFI_UNSUPPORTED The address range specified by DestOffset, Width, and Count\r
346 is not valid for the PCI BAR specified by DestBarIndex.\r
347 @retval EFI_UNSUPPORTED The address range specified by SrcOffset, Width, and Count is\r
348 not valid for the PCI BAR specified by SrcBarIndex.\r
349 @retval EFI_INVALID_PARAMETER Width is invalid.\r
350 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
351\r
352**/\r
353EFI_STATUS\r
354EFIAPI\r
355PciIoCopyMem (\r
356 IN EFI_PCI_IO_PROTOCOL *This,\r
357 IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
358 IN UINT8 DestBarIndex,\r
359 IN UINT64 DestOffset,\r
360 IN UINT8 SrcBarIndex,\r
361 IN UINT64 SrcOffset,\r
362 IN UINTN Count\r
363 );\r
364\r
365/**\r
366 Provides the PCI controller-specific addresses needed to access system memory.\r
367\r
368 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
369 @param Operation Indicates if the bus master is going to read or write to system memory.\r
370 @param HostAddress The system memory address to map to the PCI controller.\r
371 @param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
372 that were mapped.\r
373 @param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
374 access the hosts HostAddress.\r
375 @param Mapping A resulting value to pass to Unmap().\r
376\r
377 @retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
378 @retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
379 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
380 @retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
381 @retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
382\r
383**/\r
384EFI_STATUS\r
385EFIAPI\r
386PciIoMap (\r
387 IN EFI_PCI_IO_PROTOCOL *This,\r
388 IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
389 IN VOID *HostAddress,\r
390 IN OUT UINTN *NumberOfBytes,\r
391 OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
392 OUT VOID **Mapping\r
393 );\r
394\r
395/**\r
396 Completes the Map() operation and releases any corresponding resources.\r
397\r
398 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
399 @param Mapping The mapping value returned from Map().\r
400\r
401 @retval EFI_SUCCESS The range was unmapped.\r
402 @retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
403\r
404**/\r
405EFI_STATUS\r
406EFIAPI\r
407PciIoUnmap (\r
408 IN EFI_PCI_IO_PROTOCOL *This,\r
409 IN VOID *Mapping\r
410 );\r
411\r
412/**\r
413 Allocates pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
414 mapping.\r
415\r
416 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
417 @param Type This parameter is not used and must be ignored.\r
418 @param MemoryType The type of memory to allocate, EfiBootServicesData or\r
419 EfiRuntimeServicesData.\r
420 @param Pages The number of pages to allocate.\r
421 @param HostAddress A pointer to store the base system memory address of the\r
422 allocated range.\r
423 @param Attributes The requested bit mask of attributes for the allocated range.\r
424\r
425 @retval EFI_SUCCESS The requested memory pages were allocated.\r
426 @retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
427 MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
428 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
429 @retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
430\r
431**/\r
432EFI_STATUS\r
433EFIAPI\r
434PciIoAllocateBuffer (\r
435 IN EFI_PCI_IO_PROTOCOL *This,\r
436 IN EFI_ALLOCATE_TYPE Type,\r
437 IN EFI_MEMORY_TYPE MemoryType,\r
438 IN UINTN Pages,\r
439 OUT VOID **HostAddress,\r
440 IN UINT64 Attributes\r
441 );\r
442\r
443/**\r
444 Frees memory that was allocated with AllocateBuffer().\r
445\r
446 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
447 @param Pages The number of pages to free.\r
448 @param HostAddress The base system memory address of the allocated range.\r
449\r
450 @retval EFI_SUCCESS The requested memory pages were freed.\r
451 @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
452 was not allocated with AllocateBuffer().\r
453\r
454**/\r
455EFI_STATUS\r
456EFIAPI\r
457PciIoFreeBuffer (\r
458 IN EFI_PCI_IO_PROTOCOL *This,\r
459 IN UINTN Pages,\r
460 IN VOID *HostAddress\r
461 );\r
462\r
463/**\r
464 Flushes all PCI posted write transactions from a PCI host bridge to system memory.\r
465\r
466 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
467\r
468 @retval EFI_SUCCESS The PCI posted write transactions were flushed from the PCI host\r
469 bridge to system memory.\r
470 @retval EFI_DEVICE_ERROR The PCI posted write transactions were not flushed from the PCI\r
471 host bridge due to a hardware error.\r
472\r
473**/\r
474EFI_STATUS\r
475EFIAPI\r
476PciIoFlush (\r
477 IN EFI_PCI_IO_PROTOCOL *This\r
478 );\r
479\r
480/**\r
481 Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
482\r
483 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
484 @param SegmentNumber The PCI controller's current PCI segment number.\r
485 @param BusNumber The PCI controller's current PCI bus number.\r
486 @param DeviceNumber The PCI controller's current PCI device number.\r
487 @param FunctionNumber The PCI controller's current PCI function number.\r
488\r
489 @retval EFI_SUCCESS The PCI controller location was returned.\r
490 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
491\r
492**/\r
493EFI_STATUS\r
494EFIAPI\r
495PciIoGetLocation (\r
496 IN EFI_PCI_IO_PROTOCOL *This,\r
497 OUT UINTN *Segment,\r
498 OUT UINTN *Bus,\r
499 OUT UINTN *Device,\r
500 OUT UINTN *Function\r
501 );\r
502\r
503/**\r
504 Check BAR type for PCI resource.\r
505\r
506 @param PciIoDevice PCI device instance.\r
507 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
508 base address for the memory or I/O operation to perform.\r
509 @param BarType Memory or I/O.\r
510\r
511 @retval TRUE Pci device's bar type is same with input BarType.\r
512 @retval TRUE Pci device's bar type is not same with input BarType.\r
513\r
514**/\r
515BOOLEAN\r
516CheckBarType (\r
517 IN PCI_IO_DEVICE *PciIoDevice,\r
518 IN UINT8 BarIndex,\r
519 IN PCI_BAR_TYPE BarType\r
520 );\r
521\r
522/**\r
523 Set/Disable new attributes to a Root Bridge.\r
524\r
525 @param PciIoDevice Pci device instance.\r
526 @param Attributes New attribute want to be set.\r
527 @param Operation Set or Disable.\r
528\r
529 @retval EFI_UNSUPPORTED If root bridge does not support change attribute.\r
530 @retval EFI_SUCCESS Successfully set new attributs.\r
531\r
532**/\r
533EFI_STATUS\r
534ModifyRootBridgeAttributes (\r
535 IN PCI_IO_DEVICE *PciIoDevice,\r
536 IN UINT64 Attributes,\r
537 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
538 );\r
539\r
540/**\r
541 Check whether this device can be enable/disable to snoop.\r
542\r
543 @param PciIoDevice Pci device instance.\r
544 @param Operation Enable/Disable.\r
545\r
546 @retval EFI_UNSUPPORTED Pci device is not GFX device or not support snoop.\r
547 @retval EFI_SUCCESS Snoop can be supported.\r
548\r
549**/\r
550EFI_STATUS\r
551SupportPaletteSnoopAttributes (\r
552 IN PCI_IO_DEVICE *PciIoDevice,\r
553 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation\r
554 );\r
555\r
556/**\r
557 Performs an operation on the attributes that this PCI controller supports. The operations include\r
558 getting the set of supported attributes, retrieving the current attributes, setting the current\r
559 attributes, enabling attributes, and disabling attributes.\r
560\r
561 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
562 @param Operation The operation to perform on the attributes for this PCI controller.\r
563 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
564 operations.\r
565 @param Result A pointer to the result mask of attributes that are returned for the Get\r
566 and Supported operations.\r
567\r
568 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
569 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
570 @retval EFI_UNSUPPORTED one or more of the bits set in\r
571 Attributes are not supported by this PCI controller or one of\r
572 its parent bridges when Operation is Set, Enable or Disable.\r
573\r
574**/\r
575EFI_STATUS\r
576EFIAPI\r
577PciIoAttributes (\r
578 IN EFI_PCI_IO_PROTOCOL * This,\r
579 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
580 IN UINT64 Attributes,\r
581 OUT UINT64 *Result OPTIONAL\r
582 );\r
583\r
584/**\r
585 Gets the attributes that this PCI controller supports setting on a BAR using\r
586 SetBarAttributes(), and retrieves the list of resource descriptors for a BAR.\r
587\r
588 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
589 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
590 base address for resource range. The legal range for this field is 0..5.\r
591 @param Supports A pointer to the mask of attributes that this PCI controller supports\r
592 setting for this BAR with SetBarAttributes().\r
6fbaed1f 593 @param Resources A pointer to the resource descriptors that describe the current\r
9060e3ec 594 configuration of this BAR of the PCI controller.\r
595\r
596 @retval EFI_SUCCESS If Supports is not NULL, then the attributes that the PCI\r
597 controller supports are returned in Supports. If Resources\r
6fbaed1f 598 is not NULL, then the resource descriptors that the PCI\r
9060e3ec 599 controller is currently using are returned in Resources.\r
600 @retval EFI_INVALID_PARAMETER Both Supports and Attributes are NULL.\r
601 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
602 @retval EFI_OUT_OF_RESOURCES There are not enough resources available to allocate\r
603 Resources.\r
604\r
605**/\r
606EFI_STATUS\r
607EFIAPI\r
608PciIoGetBarAttributes (\r
609 IN EFI_PCI_IO_PROTOCOL * This,\r
610 IN UINT8 BarIndex,\r
611 OUT UINT64 *Supports, OPTIONAL\r
612 OUT VOID **Resources OPTIONAL\r
613 );\r
614\r
615/**\r
616 Sets the attributes for a range of a BAR on a PCI controller.\r
617\r
618 @param This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
619 @param Attributes The mask of attributes to set for the resource range specified by\r
620 BarIndex, Offset, and Length.\r
621 @param BarIndex The BAR index of the standard PCI Configuration header to use as the\r
622 base address for resource range. The legal range for this field is 0..5.\r
623 @param Offset A pointer to the BAR relative base address of the resource range to be\r
624 modified by the attributes specified by Attributes.\r
625 @param Length A pointer to the length of the resource range to be modified by the\r
626 attributes specified by Attributes.\r
627\r
628 @retval EFI_SUCCESS The set of attributes specified by Attributes for the resource\r
629 range specified by BarIndex, Offset, and Length were\r
630 set on the PCI controller, and the actual resource range is returned\r
631 in Offset and Length.\r
632 @retval EFI_INVALID_PARAMETER Offset or Length is NULL.\r
633 @retval EFI_UNSUPPORTED BarIndex not valid for this PCI controller.\r
634 @retval EFI_OUT_OF_RESOURCES There are not enough resources to set the attributes on the\r
635 resource range specified by BarIndex, Offset, and\r
636 Length.\r
637\r
638**/\r
639EFI_STATUS\r
640EFIAPI\r
641PciIoSetBarAttributes (\r
642 IN EFI_PCI_IO_PROTOCOL *This,\r
643 IN UINT64 Attributes,\r
644 IN UINT8 BarIndex,\r
645 IN OUT UINT64 *Offset,\r
646 IN OUT UINT64 *Length\r
647 );\r
648\r
649/**\r
650 Program parent bridge's attribute recurrently.\r
651\r
652 @param PciIoDevice Child Pci device instance\r
653 @param Operation The operation to perform on the attributes for this PCI controller.\r
654 @param Attributes The mask of attributes that are used for Set, Enable, and Disable\r
655 operations.\r
656\r
657 @retval EFI_SUCCESS The operation on the PCI controller's attributes was completed.\r
658 @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
659 @retval EFI_UNSUPPORTED one or more of the bits set in\r
660 Attributes are not supported by this PCI controller or one of\r
661 its parent bridges when Operation is Set, Enable or Disable.\r
662\r
663**/\r
664EFI_STATUS\r
665UpStreamBridgesAttributes (\r
666 IN PCI_IO_DEVICE *PciIoDevice,\r
667 IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
668 IN UINT64 Attributes\r
669 );\r
670\r
671/**\r
672 Test whether two Pci devices has same parent bridge.\r
673\r
674 @param PciDevice1 The first pci device for testing.\r
675 @param PciDevice2 The second pci device for testing.\r
676\r
677 @retval TRUE Two Pci device has the same parent bridge.\r
678 @retval FALSE Two Pci device has not the same parent bridge.\r
679\r
680**/\r
681BOOLEAN\r
682PciDevicesOnTheSamePath (\r
683 IN PCI_IO_DEVICE *PciDevice1,\r
684 IN PCI_IO_DEVICE *PciDevice2\r
685 );\r
686\r
687#endif\r