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913cb9dc | 1 | /** @file\r |
2 | \r | |
ab6495ea | 3 | The definition for UHCI register operation routines.\r |
4 | \r | |
b4c24e2d | 5 | Copyright (c) 2007 - 2008, Intel Corporation\r |
913cb9dc | 6 | All rights reserved. This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
913cb9dc | 14 | **/\r |
15 | \r | |
16 | #ifndef _EFI_UHCI_REG_H_\r | |
17 | #define _EFI_UHCI_REG_H_\r | |
18 | \r | |
ab6495ea | 19 | typedef enum {\r |
913cb9dc | 20 | UHCI_FRAME_NUM = 1024,\r |
21 | \r | |
22 | //\r | |
23 | // Register offset and PCI related staff\r | |
24 | //\r | |
913cb9dc | 25 | USB_BAR_INDEX = 4,\r |
913cb9dc | 26 | \r |
27 | USBCMD_OFFSET = 0,\r | |
28 | USBSTS_OFFSET = 2,\r | |
29 | USBINTR_OFFSET = 4,\r | |
30 | USBPORTSC_OFFSET = 0x10,\r | |
31 | USB_FRAME_NO_OFFSET = 6,\r | |
32 | USB_FRAME_BASE_OFFSET = 8,\r | |
33 | USB_EMULATION_OFFSET = 0xC0,\r | |
34 | \r | |
35 | //\r | |
36 | // Packet IDs\r | |
37 | //\r | |
38 | SETUP_PACKET_ID = 0x2D,\r | |
39 | INPUT_PACKET_ID = 0x69,\r | |
40 | OUTPUT_PACKET_ID = 0xE1,\r | |
41 | ERROR_PACKET_ID = 0x55,\r | |
42 | \r | |
43 | //\r | |
44 | // USB port status and control bit definition.\r | |
45 | //\r | |
a261044c | 46 | USBPORTSC_CCS = BIT0, // Current Connect Status\r |
47 | USBPORTSC_CSC = BIT1, // Connect Status Change\r | |
48 | USBPORTSC_PED = BIT2, // Port Enable / Disable\r | |
49 | USBPORTSC_PEDC = BIT3, // Port Enable / Disable Change\r | |
50 | USBPORTSC_LSL = BIT4, // Line Status Low BIT\r | |
51 | USBPORTSC_LSH = BIT5, // Line Status High BIT\r | |
52 | USBPORTSC_RD = BIT6, // Resume Detect\r | |
53 | USBPORTSC_LSDA = BIT8, // Low Speed Device Attached\r | |
54 | USBPORTSC_PR = BIT9, // Port Reset\r | |
55 | USBPORTSC_SUSP = BIT12, // Suspend\r | |
913cb9dc | 56 | \r |
b4c24e2d | 57 | //\r |
58 | // UHCI Spec said it must implement 2 ports each host at least,\r | |
59 | // and if more, check whether the bit7 of PORTSC is always 1.\r | |
60 | // So here assume the max of port number each host is 16.\r | |
61 | //\r | |
62 | USB_MAX_ROOTHUB_PORT = 0x0F,\r | |
63 | \r | |
913cb9dc | 64 | //\r |
65 | // Command register bit definitions\r | |
66 | //\r | |
a261044c | 67 | USBCMD_RS = BIT0, // Run/Stop\r |
68 | USBCMD_HCRESET = BIT1, // Host reset\r | |
69 | USBCMD_GRESET = BIT2, // Global reset\r | |
70 | USBCMD_EGSM = BIT3, // Global Suspend Mode\r | |
71 | USBCMD_FGR = BIT4, // Force Global Resume\r | |
72 | USBCMD_SWDBG = BIT5, // SW Debug mode\r | |
73 | USBCMD_CF = BIT6, // Config Flag (sw only)\r | |
74 | USBCMD_MAXP = BIT7, // Max Packet (0 = 32, 1 = 64)\r | |
913cb9dc | 75 | \r |
76 | //\r | |
77 | // USB Status register bit definitions\r | |
78 | //\r | |
a261044c | 79 | USBSTS_USBINT = BIT0, // Interrupt due to IOC\r |
80 | USBSTS_ERROR = BIT1, // Interrupt due to error\r | |
81 | USBSTS_RD = BIT2, // Resume Detect\r | |
82 | USBSTS_HSE = BIT3, // Host System Error\r | |
83 | USBSTS_HCPE = BIT4, // Host Controller Process Error\r | |
84 | USBSTS_HCH = BIT5, // HC Halted\r | |
85 | \r | |
86 | USBTD_ACTIVE = BIT7, // TD is still active\r | |
87 | USBTD_STALLED = BIT6, // TD is stalled\r | |
88 | USBTD_BUFFERR = BIT5, // Buffer underflow or overflow\r | |
89 | USBTD_BABBLE = BIT4, // Babble condition\r | |
90 | USBTD_NAK = BIT3, // NAK is received\r | |
91 | USBTD_CRC = BIT2, // CRC/Time out error\r | |
92 | USBTD_BITSTUFF = BIT1 // Bit stuff error\r | |
ab6495ea | 93 | }UHCI_REGISTER_OFFSET;\r |
913cb9dc | 94 | \r |
95 | \r | |
96 | /**\r | |
ab6495ea | 97 | Read a UHCI register.\r |
913cb9dc | 98 | \r |
ab6495ea | 99 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
100 | @param Offset Register offset to USB_BAR_INDEX.\r | |
913cb9dc | 101 | \r |
ab6495ea | 102 | @return Content of register.\r |
913cb9dc | 103 | \r |
104 | **/\r | |
105 | UINT16\r | |
106 | UhciReadReg (\r | |
107 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
108 | IN UINT32 Offset\r | |
ed66e1bc | 109 | );\r |
913cb9dc | 110 | \r |
111 | \r | |
112 | \r | |
113 | /**\r | |
ab6495ea | 114 | Write data to UHCI register.\r |
913cb9dc | 115 | \r |
ab6495ea | 116 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
117 | @param Offset Register offset to USB_BAR_INDEX.\r | |
118 | @param Data Data to write.\r | |
913cb9dc | 119 | \r |
ab6495ea | 120 | @return None.\r |
913cb9dc | 121 | \r |
122 | **/\r | |
123 | VOID\r | |
124 | UhciWriteReg (\r | |
125 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
126 | IN UINT32 Offset,\r | |
127 | IN UINT16 Data\r | |
ed66e1bc | 128 | );\r |
913cb9dc | 129 | \r |
130 | \r | |
131 | \r | |
132 | /**\r | |
ab6495ea | 133 | Set a bit of the UHCI Register.\r |
913cb9dc | 134 | \r |
ab6495ea | 135 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
136 | @param Offset Register offset to USB_BAR_INDEX.\r | |
137 | @param Bit The bit to set.\r | |
913cb9dc | 138 | \r |
ab6495ea | 139 | @return None.\r |
913cb9dc | 140 | \r |
141 | **/\r | |
142 | VOID\r | |
143 | UhciSetRegBit (\r | |
144 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
145 | IN UINT32 Offset,\r | |
146 | IN UINT16 Bit\r | |
ed66e1bc | 147 | );\r |
913cb9dc | 148 | \r |
149 | \r | |
150 | \r | |
151 | /**\r | |
ab6495ea | 152 | Clear a bit of the UHCI Register.\r |
913cb9dc | 153 | \r |
ab6495ea | 154 | @param PciIo The PCI_IO protocol to access the PCI.\r |
155 | @param Offset Register offset to USB_BAR_INDEX.\r | |
156 | @param Bit The bit to clear.\r | |
913cb9dc | 157 | \r |
ab6495ea | 158 | @return None.\r |
913cb9dc | 159 | \r |
160 | **/\r | |
161 | VOID\r | |
162 | UhciClearRegBit (\r | |
163 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
164 | IN UINT32 Offset,\r | |
165 | IN UINT16 Bit\r | |
ed66e1bc | 166 | );\r |
913cb9dc | 167 | \r |
168 | \r | |
169 | /**\r | |
170 | Clear all the interrutp status bits, these bits\r | |
ab6495ea | 171 | are Write-Clean.\r |
913cb9dc | 172 | \r |
ab6495ea | 173 | @param Uhc The UHCI device.\r |
913cb9dc | 174 | \r |
ab6495ea | 175 | @return None.\r |
913cb9dc | 176 | \r |
177 | **/\r | |
178 | VOID\r | |
179 | UhciAckAllInterrupt (\r | |
180 | IN USB_HC_DEV *Uhc\r | |
ed66e1bc | 181 | );\r |
913cb9dc | 182 | \r |
183 | \r | |
184 | /**\r | |
ab6495ea | 185 | Stop the host controller.\r |
913cb9dc | 186 | \r |
ab6495ea | 187 | @param Uhc The UHCI device.\r |
188 | @param Timeout Max time allowed.\r | |
913cb9dc | 189 | \r |
ab6495ea | 190 | @retval EFI_SUCCESS The host controller is stopped.\r |
191 | @retval EFI_TIMEOUT Failed to stop the host controller.\r | |
913cb9dc | 192 | \r |
193 | **/\r | |
194 | EFI_STATUS\r | |
195 | UhciStopHc (\r | |
196 | IN USB_HC_DEV *Uhc,\r | |
197 | IN UINTN Timeout\r | |
ed66e1bc | 198 | );\r |
913cb9dc | 199 | \r |
200 | \r | |
201 | \r | |
202 | /**\r | |
ab6495ea | 203 | Check whether the host controller operates well.\r |
913cb9dc | 204 | \r |
ab6495ea | 205 | @param PciIo The PCI_IO protocol to use.\r |
913cb9dc | 206 | \r |
ab6495ea | 207 | @retval TRUE Host controller is working.\r |
208 | @retval FALSE Host controller is halted or system error.\r | |
913cb9dc | 209 | \r |
210 | **/\r | |
211 | BOOLEAN\r | |
212 | UhciIsHcWorking (\r | |
213 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 214 | );\r |
913cb9dc | 215 | \r |
216 | \r | |
217 | /**\r | |
218 | Set the UHCI frame list base address. It can't use\r | |
219 | UhciWriteReg which access memory in UINT16.\r | |
220 | \r | |
ab6495ea | 221 | @param PciIo The EFI_PCI_IO_PROTOCOL to use.\r |
222 | @param Addr Address to set.\r | |
913cb9dc | 223 | \r |
ab6495ea | 224 | @return None.\r |
913cb9dc | 225 | \r |
226 | **/\r | |
227 | VOID\r | |
228 | UhciSetFrameListBaseAddr (\r | |
229 | IN EFI_PCI_IO_PROTOCOL *PciIo,\r | |
230 | IN VOID *Addr\r | |
ed66e1bc | 231 | );\r |
913cb9dc | 232 | \r |
233 | \r | |
234 | /**\r | |
ab6495ea | 235 | Disable USB Emulation.\r |
913cb9dc | 236 | \r |
ab6495ea | 237 | @param PciIo The EFI_PCI_IO_PROTOCOL protocol to use.\r |
913cb9dc | 238 | \r |
ab6495ea | 239 | @return None.\r |
913cb9dc | 240 | \r |
241 | **/\r | |
242 | VOID\r | |
243 | UhciTurnOffUsbEmulation (\r | |
244 | IN EFI_PCI_IO_PROTOCOL *PciIo\r | |
ed66e1bc | 245 | );\r |
913cb9dc | 246 | #endif\r |