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92870c98 | 1 | /** @file\r |
2 | \r | |
3 | XHCI transfer scheduling routines.\r | |
4 | \r | |
16d718a5 | 5 | Copyright (c) 2011 - 2012, Intel Corporation. All rights reserved.<BR>\r |
92870c98 | 6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include "Xhci.h"\r | |
17 | \r | |
92870c98 | 18 | /**\r |
19 | Create a command transfer TRB to support XHCI command interfaces.\r | |
20 | \r | |
a9292c13 | 21 | @param Xhc The XHCI Instance.\r |
92870c98 | 22 | @param CmdTrb The cmd TRB to be executed.\r |
23 | \r | |
24 | @return Created URB or NULL.\r | |
25 | \r | |
26 | **/\r | |
27 | URB*\r | |
28 | XhcCreateCmdTrb (\r | |
a9292c13 | 29 | IN USB_XHCI_INSTANCE *Xhc,\r |
30 | IN TRB_TEMPLATE *CmdTrb\r | |
92870c98 | 31 | )\r |
32 | {\r | |
33 | URB *Urb;\r | |
34 | \r | |
35 | Urb = AllocateZeroPool (sizeof (URB));\r | |
36 | if (Urb == NULL) {\r | |
37 | return NULL;\r | |
38 | }\r | |
39 | \r | |
40 | Urb->Signature = XHC_URB_SIG;\r | |
41 | \r | |
42 | Urb->Ring = &Xhc->CmdRing;\r | |
43 | XhcSyncTrsRing (Xhc, Urb->Ring);\r | |
44 | Urb->TrbNum = 1;\r | |
45 | Urb->TrbStart = Urb->Ring->RingEnqueue;\r | |
a9292c13 | 46 | CopyMem (Urb->TrbStart, CmdTrb, sizeof (TRB_TEMPLATE));\r |
92870c98 | 47 | Urb->TrbStart->CycleBit = Urb->Ring->RingPCS & BIT0;\r |
48 | Urb->TrbEnd = Urb->TrbStart;\r | |
49 | \r | |
92870c98 | 50 | return Urb;\r |
51 | }\r | |
52 | \r | |
53 | /**\r | |
54 | Execute a XHCI cmd TRB pointed by CmdTrb.\r | |
55 | \r | |
a9292c13 | 56 | @param Xhc The XHCI Instance.\r |
92870c98 | 57 | @param CmdTrb The cmd TRB to be executed.\r |
a9292c13 | 58 | @param Timeout Indicates the maximum time, in millisecond, which the\r |
92870c98 | 59 | transfer is allowed to complete.\r |
60 | @param EvtTrb The event TRB corresponding to the cmd TRB.\r | |
61 | \r | |
62 | @retval EFI_SUCCESS The transfer was completed successfully.\r | |
63 | @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r | |
64 | @retval EFI_TIMEOUT The transfer failed due to timeout.\r | |
65 | @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r | |
66 | \r | |
67 | **/\r | |
68 | EFI_STATUS\r | |
69 | EFIAPI\r | |
70 | XhcCmdTransfer (\r | |
a9292c13 | 71 | IN USB_XHCI_INSTANCE *Xhc,\r |
72 | IN TRB_TEMPLATE *CmdTrb,\r | |
73 | IN UINTN Timeout,\r | |
74 | OUT TRB_TEMPLATE **EvtTrb\r | |
92870c98 | 75 | )\r |
76 | {\r | |
77 | EFI_STATUS Status;\r | |
78 | URB *Urb;\r | |
79 | \r | |
80 | //\r | |
81 | // Validate the parameters\r | |
82 | //\r | |
83 | if ((Xhc == NULL) || (CmdTrb == NULL)) {\r | |
84 | return EFI_INVALID_PARAMETER;\r | |
85 | }\r | |
86 | \r | |
87 | Status = EFI_DEVICE_ERROR;\r | |
88 | \r | |
89 | if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r | |
90 | DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: HC is halted\n"));\r | |
91 | goto ON_EXIT;\r | |
92 | }\r | |
93 | \r | |
94 | //\r | |
95 | // Create a new URB, then poll the execution status.\r | |
96 | //\r | |
97 | Urb = XhcCreateCmdTrb (Xhc, CmdTrb);\r | |
98 | \r | |
99 | if (Urb == NULL) {\r | |
100 | DEBUG ((EFI_D_ERROR, "XhcCmdTransfer: failed to create URB\n"));\r | |
101 | Status = EFI_OUT_OF_RESOURCES;\r | |
102 | goto ON_EXIT;\r | |
103 | }\r | |
104 | \r | |
a9292c13 | 105 | Status = XhcExecTransfer (Xhc, TRUE, Urb, Timeout);\r |
a50f7c4c | 106 | *EvtTrb = Urb->EvtTrb;\r |
92870c98 | 107 | \r |
108 | if (Urb->Result == EFI_USB_NOERROR) {\r | |
109 | Status = EFI_SUCCESS;\r | |
110 | }\r | |
111 | \r | |
112 | FreePool (Urb);\r | |
113 | \r | |
114 | ON_EXIT:\r | |
115 | return Status;\r | |
116 | }\r | |
117 | \r | |
118 | /**\r | |
119 | Create a new URB for a new transaction.\r | |
120 | \r | |
a9292c13 | 121 | @param Xhc The XHCI Instance\r |
6b4483cd | 122 | @param BusAddr The logical device address assigned by UsbBus driver\r |
92870c98 | 123 | @param EpAddr Endpoint addrress\r |
124 | @param DevSpeed The device speed\r | |
125 | @param MaxPacket The max packet length of the endpoint\r | |
126 | @param Type The transaction type\r | |
127 | @param Request The standard USB request for control transfer\r | |
128 | @param Data The user data to transfer\r | |
129 | @param DataLen The length of data buffer\r | |
130 | @param Callback The function to call when data is transferred\r | |
131 | @param Context The context to the callback\r | |
132 | \r | |
133 | @return Created URB or NULL\r | |
134 | \r | |
135 | **/\r | |
136 | URB*\r | |
137 | XhcCreateUrb (\r | |
a9292c13 | 138 | IN USB_XHCI_INSTANCE *Xhc,\r |
6b4483cd | 139 | IN UINT8 BusAddr,\r |
92870c98 | 140 | IN UINT8 EpAddr,\r |
141 | IN UINT8 DevSpeed,\r | |
142 | IN UINTN MaxPacket,\r | |
143 | IN UINTN Type,\r | |
144 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
145 | IN VOID *Data,\r | |
146 | IN UINTN DataLen,\r | |
147 | IN EFI_ASYNC_USB_TRANSFER_CALLBACK Callback,\r | |
148 | IN VOID *Context\r | |
149 | )\r | |
150 | {\r | |
151 | USB_ENDPOINT *Ep;\r | |
152 | EFI_STATUS Status;\r | |
153 | URB *Urb;\r | |
154 | \r | |
155 | Urb = AllocateZeroPool (sizeof (URB));\r | |
156 | if (Urb == NULL) {\r | |
157 | return NULL;\r | |
158 | }\r | |
159 | \r | |
160 | Urb->Signature = XHC_URB_SIG;\r | |
161 | InitializeListHead (&Urb->UrbList);\r | |
162 | \r | |
163 | Ep = &Urb->Ep;\r | |
6b4483cd | 164 | Ep->BusAddr = BusAddr;\r |
ce9b5900 | 165 | Ep->EpAddr = (UINT8)(EpAddr & 0x0F);\r |
92870c98 | 166 | Ep->Direction = ((EpAddr & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r |
167 | Ep->DevSpeed = DevSpeed;\r | |
168 | Ep->MaxPacket = MaxPacket;\r | |
169 | Ep->Type = Type;\r | |
170 | \r | |
171 | Urb->Request = Request;\r | |
172 | Urb->Data = Data;\r | |
173 | Urb->DataLen = DataLen;\r | |
174 | Urb->Callback = Callback;\r | |
175 | Urb->Context = Context;\r | |
176 | \r | |
177 | Status = XhcCreateTransferTrb (Xhc, Urb);\r | |
7538d536 | 178 | ASSERT_EFI_ERROR (Status);\r |
92870c98 | 179 | \r |
180 | return Urb;\r | |
181 | }\r | |
182 | \r | |
183 | /**\r | |
184 | Create a transfer TRB.\r | |
185 | \r | |
a9292c13 | 186 | @param Xhc The XHCI Instance\r |
92870c98 | 187 | @param Urb The urb used to construct the transfer TRB.\r |
188 | \r | |
189 | @return Created TRB or NULL\r | |
190 | \r | |
191 | **/\r | |
192 | EFI_STATUS\r | |
92870c98 | 193 | XhcCreateTransferTrb (\r |
a9292c13 | 194 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 195 | IN URB *Urb\r |
196 | )\r | |
197 | {\r | |
6b4483cd | 198 | VOID *OutputContext;\r |
92870c98 | 199 | TRANSFER_RING *EPRing;\r |
200 | UINT8 EPType;\r | |
201 | UINT8 SlotId;\r | |
202 | UINT8 Dci;\r | |
203 | TRB *TrbStart;\r | |
204 | UINTN TotalLen;\r | |
205 | UINTN Len;\r | |
206 | UINTN TrbNum;\r | |
207 | \r | |
6b4483cd | 208 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
209 | if (SlotId == 0) {\r | |
210 | return EFI_DEVICE_ERROR;\r | |
211 | }\r | |
212 | \r | |
a50f7c4c | 213 | Urb->Finished = FALSE;\r |
214 | Urb->StartDone = FALSE;\r | |
215 | Urb->EndDone = FALSE;\r | |
216 | Urb->Completed = 0;\r | |
217 | Urb->Result = EFI_USB_NOERROR;\r | |
218 | \r | |
ce9b5900 | 219 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r |
a9292c13 | 220 | ASSERT (Dci < 32);\r |
221 | EPRing = (TRANSFER_RING *)(UINTN) Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1];\r | |
92870c98 | 222 | Urb->Ring = EPRing;\r |
6b4483cd | 223 | OutputContext = (VOID *)(UINTN)Xhc->DCBAA[SlotId];\r |
224 | if (Xhc->HcCParams.Data.Csz == 0) {\r | |
225 | EPType = (UINT8) ((DEVICE_CONTEXT *)OutputContext)->EP[Dci-1].EPType;\r | |
226 | } else {\r | |
227 | EPType = (UINT8) ((DEVICE_CONTEXT_64 *)OutputContext)->EP[Dci-1].EPType;\r | |
228 | }\r | |
92870c98 | 229 | \r |
230 | //\r | |
231 | // Construct the TRB\r | |
232 | //\r | |
233 | XhcSyncTrsRing (Xhc, EPRing);\r | |
234 | Urb->TrbStart = EPRing->RingEnqueue;\r | |
235 | switch (EPType) {\r | |
236 | case ED_CONTROL_BIDIR:\r | |
92870c98 | 237 | //\r |
238 | // For control transfer, create SETUP_STAGE_TRB first.\r | |
239 | //\r | |
a9292c13 | 240 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
241 | TrbStart->TrbCtrSetup.bmRequestType = Urb->Request->RequestType;\r | |
242 | TrbStart->TrbCtrSetup.bRequest = Urb->Request->Request;\r | |
243 | TrbStart->TrbCtrSetup.wValue = Urb->Request->Value;\r | |
244 | TrbStart->TrbCtrSetup.wIndex = Urb->Request->Index;\r | |
245 | TrbStart->TrbCtrSetup.wLength = Urb->Request->Length;\r | |
246 | TrbStart->TrbCtrSetup.Lenth = 8;\r | |
6b4483cd | 247 | TrbStart->TrbCtrSetup.IntTarget = 0;\r |
a9292c13 | 248 | TrbStart->TrbCtrSetup.IOC = 1;\r |
249 | TrbStart->TrbCtrSetup.IDT = 1;\r | |
250 | TrbStart->TrbCtrSetup.Type = TRB_TYPE_SETUP_STAGE;\r | |
92870c98 | 251 | if (Urb->Ep.Direction == EfiUsbDataIn) {\r |
a9292c13 | 252 | TrbStart->TrbCtrSetup.TRT = 3;\r |
92870c98 | 253 | } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r |
a9292c13 | 254 | TrbStart->TrbCtrSetup.TRT = 2;\r |
92870c98 | 255 | } else {\r |
a9292c13 | 256 | TrbStart->TrbCtrSetup.TRT = 0;\r |
92870c98 | 257 | }\r |
258 | //\r | |
259 | // Update the cycle bit\r | |
260 | //\r | |
a9292c13 | 261 | TrbStart->TrbCtrSetup.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 262 | Urb->TrbNum++;\r |
263 | \r | |
264 | //\r | |
265 | // For control transfer, create DATA_STAGE_TRB.\r | |
266 | //\r | |
267 | if (Urb->DataLen > 0) {\r | |
268 | XhcSyncTrsRing (Xhc, EPRing);\r | |
a9292c13 | 269 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
270 | TrbStart->TrbCtrData.TRBPtrLo = XHC_LOW_32BIT(Urb->Data);\r | |
271 | TrbStart->TrbCtrData.TRBPtrHi = XHC_HIGH_32BIT(Urb->Data);\r | |
272 | TrbStart->TrbCtrData.Lenth = (UINT32) Urb->DataLen;\r | |
273 | TrbStart->TrbCtrData.TDSize = 0;\r | |
6b4483cd | 274 | TrbStart->TrbCtrData.IntTarget = 0;\r |
a9292c13 | 275 | TrbStart->TrbCtrData.ISP = 1;\r |
276 | TrbStart->TrbCtrData.IOC = 1;\r | |
277 | TrbStart->TrbCtrData.IDT = 0;\r | |
278 | TrbStart->TrbCtrData.CH = 0;\r | |
279 | TrbStart->TrbCtrData.Type = TRB_TYPE_DATA_STAGE;\r | |
92870c98 | 280 | if (Urb->Ep.Direction == EfiUsbDataIn) {\r |
a9292c13 | 281 | TrbStart->TrbCtrData.DIR = 1;\r |
92870c98 | 282 | } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r |
a9292c13 | 283 | TrbStart->TrbCtrData.DIR = 0;\r |
92870c98 | 284 | } else {\r |
a9292c13 | 285 | TrbStart->TrbCtrData.DIR = 0;\r |
92870c98 | 286 | }\r |
287 | //\r | |
288 | // Update the cycle bit\r | |
289 | //\r | |
a9292c13 | 290 | TrbStart->TrbCtrData.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 291 | Urb->TrbNum++;\r |
292 | }\r | |
293 | //\r | |
294 | // For control transfer, create STATUS_STAGE_TRB.\r | |
295 | // Get the pointer to next TRB for status stage use\r | |
296 | //\r | |
297 | XhcSyncTrsRing (Xhc, EPRing);\r | |
a9292c13 | 298 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
6b4483cd | 299 | TrbStart->TrbCtrStatus.IntTarget = 0;\r |
a9292c13 | 300 | TrbStart->TrbCtrStatus.IOC = 1;\r |
301 | TrbStart->TrbCtrStatus.CH = 0;\r | |
302 | TrbStart->TrbCtrStatus.Type = TRB_TYPE_STATUS_STAGE;\r | |
92870c98 | 303 | if (Urb->Ep.Direction == EfiUsbDataIn) {\r |
a9292c13 | 304 | TrbStart->TrbCtrStatus.DIR = 0;\r |
92870c98 | 305 | } else if (Urb->Ep.Direction == EfiUsbDataOut) {\r |
a9292c13 | 306 | TrbStart->TrbCtrStatus.DIR = 1;\r |
92870c98 | 307 | } else {\r |
a9292c13 | 308 | TrbStart->TrbCtrStatus.DIR = 0;\r |
92870c98 | 309 | }\r |
310 | //\r | |
311 | // Update the cycle bit\r | |
312 | //\r | |
a9292c13 | 313 | TrbStart->TrbCtrStatus.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 314 | //\r |
315 | // Update the enqueue pointer\r | |
316 | //\r | |
317 | XhcSyncTrsRing (Xhc, EPRing);\r | |
318 | Urb->TrbNum++;\r | |
a9292c13 | 319 | Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r |
92870c98 | 320 | \r |
321 | break;\r | |
322 | \r | |
323 | case ED_BULK_OUT:\r | |
324 | case ED_BULK_IN:\r | |
92870c98 | 325 | TotalLen = 0;\r |
326 | Len = 0;\r | |
327 | TrbNum = 0;\r | |
a9292c13 | 328 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
92870c98 | 329 | while (TotalLen < Urb->DataLen) {\r |
330 | if ((TotalLen + 0x10000) >= Urb->DataLen) {\r | |
331 | Len = Urb->DataLen - TotalLen;\r | |
332 | } else {\r | |
333 | Len = 0x10000;\r | |
334 | }\r | |
a9292c13 | 335 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
336 | TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);\r | |
337 | TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);\r | |
338 | TrbStart->TrbNormal.Lenth = (UINT32) Len;\r | |
339 | TrbStart->TrbNormal.TDSize = 0;\r | |
6b4483cd | 340 | TrbStart->TrbNormal.IntTarget = 0;\r |
a9292c13 | 341 | TrbStart->TrbNormal.ISP = 1;\r |
342 | TrbStart->TrbNormal.IOC = 1;\r | |
343 | TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;\r | |
92870c98 | 344 | //\r |
345 | // Update the cycle bit\r | |
346 | //\r | |
a9292c13 | 347 | TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 348 | \r |
349 | XhcSyncTrsRing (Xhc, EPRing);\r | |
350 | TrbNum++;\r | |
351 | TotalLen += Len;\r | |
352 | }\r | |
353 | \r | |
354 | Urb->TrbNum = TrbNum;\r | |
a9292c13 | 355 | Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r |
92870c98 | 356 | break;\r |
357 | \r | |
358 | case ED_INTERRUPT_OUT:\r | |
359 | case ED_INTERRUPT_IN:\r | |
92870c98 | 360 | TotalLen = 0;\r |
361 | Len = 0;\r | |
362 | TrbNum = 0;\r | |
a9292c13 | 363 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
92870c98 | 364 | while (TotalLen < Urb->DataLen) {\r |
365 | if ((TotalLen + 0x10000) >= Urb->DataLen) {\r | |
366 | Len = Urb->DataLen - TotalLen;\r | |
367 | } else {\r | |
368 | Len = 0x10000;\r | |
369 | }\r | |
a9292c13 | 370 | TrbStart = (TRB *)(UINTN)EPRing->RingEnqueue;\r |
371 | TrbStart->TrbNormal.TRBPtrLo = XHC_LOW_32BIT((UINT8 *) Urb->Data + TotalLen);\r | |
372 | TrbStart->TrbNormal.TRBPtrHi = XHC_HIGH_32BIT((UINT8 *) Urb->Data + TotalLen);\r | |
373 | TrbStart->TrbNormal.Lenth = (UINT32) Len;\r | |
374 | TrbStart->TrbNormal.TDSize = 0;\r | |
6b4483cd | 375 | TrbStart->TrbNormal.IntTarget = 0;\r |
a9292c13 | 376 | TrbStart->TrbNormal.ISP = 1;\r |
377 | TrbStart->TrbNormal.IOC = 1;\r | |
378 | TrbStart->TrbNormal.Type = TRB_TYPE_NORMAL;\r | |
92870c98 | 379 | //\r |
380 | // Update the cycle bit\r | |
381 | //\r | |
a9292c13 | 382 | TrbStart->TrbNormal.CycleBit = EPRing->RingPCS & BIT0;\r |
92870c98 | 383 | \r |
384 | XhcSyncTrsRing (Xhc, EPRing);\r | |
385 | TrbNum++;\r | |
386 | TotalLen += Len;\r | |
387 | }\r | |
388 | \r | |
389 | Urb->TrbNum = TrbNum;\r | |
a9292c13 | 390 | Urb->TrbEnd = (TRB_TEMPLATE *)(UINTN)TrbStart;\r |
92870c98 | 391 | break;\r |
392 | \r | |
393 | default:\r | |
394 | DEBUG ((EFI_D_INFO, "Not supported EPType 0x%x!\n",EPType));\r | |
395 | ASSERT (FALSE);\r | |
396 | break;\r | |
397 | }\r | |
398 | \r | |
399 | return EFI_SUCCESS;\r | |
400 | }\r | |
401 | \r | |
402 | \r | |
403 | /**\r | |
404 | Initialize the XHCI host controller for schedule.\r | |
405 | \r | |
a9292c13 | 406 | @param Xhc The XHCI Instance to be initialized.\r |
92870c98 | 407 | \r |
408 | **/\r | |
409 | VOID\r | |
410 | XhcInitSched (\r | |
a9292c13 | 411 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 412 | )\r |
413 | {\r | |
414 | VOID *Dcbaa;\r | |
415 | UINT64 CmdRing;\r | |
416 | UINTN Entries;\r | |
417 | UINT32 MaxScratchpadBufs;\r | |
418 | UINT64 *ScratchBuf;\r | |
419 | UINT64 *ScratchEntryBuf;\r | |
420 | UINT32 Index;\r | |
421 | \r | |
422 | //\r | |
423 | // Program the Max Device Slots Enabled (MaxSlotsEn) field in the CONFIG register (5.4.7)\r | |
424 | // to enable the device slots that system software is going to use.\r | |
425 | //\r | |
426 | Xhc->MaxSlotsEn = Xhc->HcSParams1.Data.MaxSlots;\r | |
427 | ASSERT (Xhc->MaxSlotsEn >= 1 && Xhc->MaxSlotsEn <= 255);\r | |
428 | XhcWriteOpReg (Xhc, XHC_CONFIG_OFFSET, Xhc->MaxSlotsEn);\r | |
429 | \r | |
430 | //\r | |
431 | // The Device Context Base Address Array entry associated with each allocated Device Slot\r | |
432 | // shall contain a 64-bit pointer to the base of the associated Device Context.\r | |
433 | // The Device Context Base Address Array shall contain MaxSlotsEn + 1 entries.\r | |
434 | // Software shall set Device Context Base Address Array entries for unallocated Device Slots to '0'.\r | |
435 | //\r | |
436 | Entries = (Xhc->MaxSlotsEn + 1) * sizeof(UINT64);\r | |
a9292c13 | 437 | Dcbaa = AllocatePages (EFI_SIZE_TO_PAGES (Entries));\r |
92870c98 | 438 | ASSERT (Dcbaa != NULL);\r |
a9292c13 | 439 | ZeroMem (Dcbaa, Entries);\r |
92870c98 | 440 | \r |
441 | //\r | |
442 | // A Scratchpad Buffer is a PAGESIZE block of system memory located on a PAGESIZE boundary.\r | |
443 | // System software shall allocate the Scratchpad Buffer(s) before placing the xHC in to Run\r | |
444 | // mode (Run/Stop(R/S) ='1').\r | |
445 | //\r | |
446 | MaxScratchpadBufs = ((Xhc->HcSParams2.Data.ScratchBufHi) << 5) | (Xhc->HcSParams2.Data.ScratchBufLo);\r | |
447 | Xhc->MaxScratchpadBufs = MaxScratchpadBufs;\r | |
ce9b5900 | 448 | ASSERT (MaxScratchpadBufs <= 1023);\r |
92870c98 | 449 | if (MaxScratchpadBufs != 0) {\r |
a9292c13 | 450 | ScratchBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (MaxScratchpadBufs * sizeof (UINT64)), Xhc->PageSize);\r |
92870c98 | 451 | ASSERT (ScratchBuf != NULL);\r |
a9292c13 | 452 | ZeroMem (ScratchBuf, MaxScratchpadBufs * sizeof (UINT64));\r |
92870c98 | 453 | Xhc->ScratchBuf = ScratchBuf;\r |
454 | \r | |
455 | for (Index = 0; Index < MaxScratchpadBufs; Index++) {\r | |
a9292c13 | 456 | ScratchEntryBuf = AllocateAlignedPages (EFI_SIZE_TO_PAGES (Xhc->PageSize), Xhc->PageSize);\r |
457 | ASSERT (ScratchEntryBuf != NULL);\r | |
458 | ZeroMem (ScratchEntryBuf, Xhc->PageSize);\r | |
92870c98 | 459 | *ScratchBuf++ = (UINT64)(UINTN)ScratchEntryBuf;\r |
460 | }\r | |
461 | \r | |
462 | //\r | |
463 | // The Scratchpad Buffer Array contains pointers to the Scratchpad Buffers. Entry 0 of the\r | |
464 | // Device Context Base Address Array points to the Scratchpad Buffer Array.\r | |
465 | //\r | |
466 | *(UINT64 *)Dcbaa = (UINT64)(UINTN)Xhc->ScratchBuf;\r | |
467 | }\r | |
468 | \r | |
469 | //\r | |
470 | // Program the Device Context Base Address Array Pointer (DCBAAP) register (5.4.6) with\r | |
471 | // a 64-bit address pointing to where the Device Context Base Address Array is located.\r | |
472 | //\r | |
a9292c13 | 473 | Xhc->DCBAA = (UINT64 *)(UINTN)Dcbaa;\r |
6b4483cd | 474 | //\r |
475 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
476 | // So divide it to two 32-bytes width register access.\r | |
477 | //\r | |
478 | XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET, XHC_LOW_32BIT(Xhc->DCBAA));\r | |
479 | XhcWriteOpReg (Xhc, XHC_DCBAAP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->DCBAA));\r | |
ce9b5900 | 480 | DEBUG ((EFI_D_INFO, "XhcInitSched:DCBAA=0x%x\n", (UINT64)(UINTN)Xhc->DCBAA));\r |
92870c98 | 481 | \r |
482 | //\r | |
483 | // Define the Command Ring Dequeue Pointer by programming the Command Ring Control Register\r | |
484 | // (5.4.5) with a 64-bit address pointing to the starting address of the first TRB of the Command Ring.\r | |
485 | // Note: The Command Ring is 64 byte aligned, so the low order 6 bits of the Command Ring Pointer shall\r | |
486 | // always be '0'.\r | |
487 | //\r | |
488 | CreateTransferRing (Xhc, CMD_RING_TRB_NUMBER, &Xhc->CmdRing);\r | |
489 | //\r | |
490 | // The xHC uses the Enqueue Pointer to determine when a Transfer Ring is empty. As it fetches TRBs from a\r | |
491 | // Transfer Ring it checks for a Cycle bit transition. If a transition detected, the ring is empty.\r | |
492 | // So we set RCS as inverted PCS init value to let Command Ring empty\r | |
493 | //\r | |
494 | CmdRing = (UINT64)(UINTN)Xhc->CmdRing.RingSeg0;\r | |
495 | ASSERT ((CmdRing & 0x3F) == 0);\r | |
496 | CmdRing |= XHC_CRCR_RCS;\r | |
6b4483cd | 497 | //\r |
498 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
499 | // So divide it to two 32-bytes width register access.\r | |
500 | //\r | |
501 | XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET, XHC_LOW_32BIT(CmdRing));\r | |
502 | XhcWriteOpReg (Xhc, XHC_CRCR_OFFSET + 4, XHC_HIGH_32BIT (CmdRing));\r | |
92870c98 | 503 | \r |
504 | DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_CRCR=0x%x\n", Xhc->CmdRing.RingSeg0));\r | |
505 | \r | |
506 | //\r | |
507 | // Disable the 'interrupter enable' bit in USB_CMD\r | |
508 | // and clear IE & IP bit in all Interrupter X Management Registers.\r | |
509 | //\r | |
510 | XhcClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_INTE);\r | |
511 | for (Index = 0; Index < (UINT16)(Xhc->HcSParams1.Data.MaxIntrs); Index++) {\r | |
512 | XhcClearRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IE);\r | |
513 | XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET + (Index * 32), XHC_IMAN_IP);\r | |
514 | }\r | |
515 | \r | |
516 | //\r | |
517 | // Allocate EventRing for Cmd, Ctrl, Bulk, Interrupt, AsynInterrupt transfer\r | |
518 | //\r | |
6b4483cd | 519 | CreateEventRing (Xhc, &Xhc->EventRing);\r |
520 | DEBUG ((EFI_D_INFO, "XhcInitSched:XHC_EVENTRING=0x%x\n", Xhc->EventRing.EventRingSeg0));\r | |
92870c98 | 521 | }\r |
522 | \r | |
523 | /**\r | |
524 | System software shall use a Reset Endpoint Command (section 4.11.4.7) to remove the Halted\r | |
525 | condition in the xHC. After the successful completion of the Reset Endpoint Command, the Endpoint\r | |
526 | Context is transitioned from the Halted to the Stopped state and the Transfer Ring of the endpoint is\r | |
527 | reenabled. The next write to the Doorbell of the Endpoint will transition the Endpoint Context from the\r | |
528 | Stopped to the Running state.\r | |
529 | \r | |
a9292c13 | 530 | @param Xhc The XHCI Instance.\r |
92870c98 | 531 | @param Urb The urb which makes the endpoint halted.\r |
532 | \r | |
533 | @retval EFI_SUCCESS The recovery is successful.\r | |
534 | @retval Others Failed to recovery halted endpoint.\r | |
535 | \r | |
536 | **/\r | |
537 | EFI_STATUS\r | |
538 | EFIAPI\r | |
539 | XhcRecoverHaltedEndpoint (\r | |
a9292c13 | 540 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 541 | IN URB *Urb\r |
542 | )\r | |
543 | {\r | |
a9292c13 | 544 | EFI_STATUS Status;\r |
545 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
546 | CMD_TRB_RESET_ENDPOINT CmdTrbResetED;\r | |
547 | CMD_SET_TR_DEQ_POINTER CmdSetTRDeq;\r | |
548 | UINT8 Dci;\r | |
549 | UINT8 SlotId;\r | |
92870c98 | 550 | \r |
6b4483cd | 551 | Status = EFI_SUCCESS;\r |
552 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r | |
553 | if (SlotId == 0) {\r | |
554 | return EFI_DEVICE_ERROR;\r | |
555 | }\r | |
556 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r | |
557 | ASSERT (Dci < 32);\r | |
558 | \r | |
92870c98 | 559 | DEBUG ((EFI_D_INFO, "Recovery Halted Slot = %x,Dci = %x\n", SlotId, Dci));\r |
560 | \r | |
561 | //\r | |
562 | // 1) Send Reset endpoint command to transit from halt to stop state\r | |
563 | //\r | |
564 | ZeroMem (&CmdTrbResetED, sizeof (CmdTrbResetED));\r | |
565 | CmdTrbResetED.CycleBit = 1;\r | |
566 | CmdTrbResetED.Type = TRB_TYPE_RESET_ENDPOINT;\r | |
567 | CmdTrbResetED.EDID = Dci;\r | |
568 | CmdTrbResetED.SlotId = SlotId;\r | |
569 | Status = XhcCmdTransfer (\r | |
570 | Xhc,\r | |
a9292c13 | 571 | (TRB_TEMPLATE *) (UINTN) &CmdTrbResetED,\r |
92870c98 | 572 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 573 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 574 | );\r |
575 | ASSERT (!EFI_ERROR(Status));\r | |
576 | \r | |
577 | //\r | |
578 | // 2)Set dequeue pointer\r | |
579 | //\r | |
580 | ZeroMem (&CmdSetTRDeq, sizeof (CmdSetTRDeq));\r | |
581 | CmdSetTRDeq.PtrLo = XHC_LOW_32BIT (Urb->Ring->RingEnqueue) | Urb->Ring->RingPCS;\r | |
582 | CmdSetTRDeq.PtrHi = XHC_HIGH_32BIT (Urb->Ring->RingEnqueue);\r | |
583 | CmdSetTRDeq.CycleBit = 1;\r | |
584 | CmdSetTRDeq.Type = TRB_TYPE_SET_TR_DEQUE;\r | |
585 | CmdSetTRDeq.Endpoint = Dci;\r | |
586 | CmdSetTRDeq.SlotId = SlotId;\r | |
587 | Status = XhcCmdTransfer (\r | |
588 | Xhc,\r | |
a9292c13 | 589 | (TRB_TEMPLATE *) (UINTN) &CmdSetTRDeq,\r |
92870c98 | 590 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 591 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 592 | );\r |
593 | ASSERT (!EFI_ERROR(Status));\r | |
594 | \r | |
595 | //\r | |
596 | // 3)Ring the doorbell to transit from stop to active\r | |
597 | //\r | |
598 | XhcRingDoorBell (Xhc, SlotId, Dci);\r | |
599 | \r | |
600 | return Status;\r | |
601 | }\r | |
602 | \r | |
603 | /**\r | |
604 | Create XHCI event ring.\r | |
605 | \r | |
a9292c13 | 606 | @param Xhc The XHCI Instance.\r |
92870c98 | 607 | @param EventRing The created event ring.\r |
608 | \r | |
609 | **/\r | |
610 | VOID\r | |
92870c98 | 611 | CreateEventRing (\r |
a9292c13 | 612 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 613 | OUT EVENT_RING *EventRing\r |
614 | )\r | |
615 | {\r | |
616 | VOID *Buf;\r | |
617 | EVENT_RING_SEG_TABLE_ENTRY *ERSTBase;\r | |
618 | \r | |
619 | ASSERT (EventRing != NULL);\r | |
620 | \r | |
a9292c13 | 621 | Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));\r |
92870c98 | 622 | ASSERT (Buf != NULL);\r |
623 | ASSERT (((UINTN) Buf & 0x3F) == 0);\r | |
a9292c13 | 624 | ZeroMem (Buf, sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER);\r |
92870c98 | 625 | \r |
626 | EventRing->EventRingSeg0 = Buf;\r | |
92870c98 | 627 | EventRing->TrbNumber = EVENT_RING_TRB_NUMBER;\r |
a9292c13 | 628 | EventRing->EventRingDequeue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r |
629 | EventRing->EventRingEnqueue = (TRB_TEMPLATE *) EventRing->EventRingSeg0;\r | |
92870c98 | 630 | //\r |
631 | // Software maintains an Event Ring Consumer Cycle State (CCS) bit, initializing it to '1'\r | |
632 | // and toggling it every time the Event Ring Dequeue Pointer wraps back to the beginning of the Event Ring.\r | |
633 | //\r | |
634 | EventRing->EventRingCCS = 1;\r | |
635 | \r | |
a9292c13 | 636 | Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));\r |
92870c98 | 637 | ASSERT (Buf != NULL);\r |
638 | ASSERT (((UINTN) Buf & 0x3F) == 0);\r | |
a9292c13 | 639 | ZeroMem (Buf, sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER);\r |
92870c98 | 640 | \r |
641 | ERSTBase = (EVENT_RING_SEG_TABLE_ENTRY *) Buf;\r | |
642 | EventRing->ERSTBase = ERSTBase;\r | |
643 | ERSTBase->PtrLo = XHC_LOW_32BIT (EventRing->EventRingSeg0);\r | |
644 | ERSTBase->PtrHi = XHC_HIGH_32BIT (EventRing->EventRingSeg0);\r | |
645 | ERSTBase->RingTrbSize = EVENT_RING_TRB_NUMBER;\r | |
646 | \r | |
647 | //\r | |
648 | // Program the Interrupter Event Ring Segment Table Size (ERSTSZ) register (5.5.2.3.1)\r | |
649 | //\r | |
650 | XhcWriteRuntimeReg (\r | |
651 | Xhc,\r | |
6b4483cd | 652 | XHC_ERSTSZ_OFFSET,\r |
92870c98 | 653 | ERST_NUMBER\r |
654 | );\r | |
655 | //\r | |
656 | // Program the Interrupter Event Ring Dequeue Pointer (ERDP) register (5.5.2.3.3)\r | |
657 | //\r | |
6b4483cd | 658 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r |
659 | // So divide it to two 32-bytes width register access.\r | |
660 | //\r | |
661 | XhcWriteRuntimeReg (\r | |
662 | Xhc,\r | |
663 | XHC_ERDP_OFFSET,\r | |
664 | XHC_LOW_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)\r | |
665 | );\r | |
666 | XhcWriteRuntimeReg (\r | |
92870c98 | 667 | Xhc,\r |
6b4483cd | 668 | XHC_ERDP_OFFSET + 4,\r |
669 | XHC_HIGH_32BIT((UINT64)(UINTN)EventRing->EventRingDequeue)\r | |
92870c98 | 670 | );\r |
671 | //\r | |
672 | // Program the Interrupter Event Ring Segment Table Base Address (ERSTBA) register(5.5.2.3.2)\r | |
673 | //\r | |
6b4483cd | 674 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r |
675 | // So divide it to two 32-bytes width register access.\r | |
676 | //\r | |
677 | XhcWriteRuntimeReg (\r | |
678 | Xhc,\r | |
679 | XHC_ERSTBA_OFFSET,\r | |
680 | XHC_LOW_32BIT((UINT64)(UINTN)ERSTBase)\r | |
681 | );\r | |
682 | XhcWriteRuntimeReg (\r | |
92870c98 | 683 | Xhc,\r |
6b4483cd | 684 | XHC_ERSTBA_OFFSET + 4,\r |
685 | XHC_HIGH_32BIT((UINT64)(UINTN)ERSTBase)\r | |
92870c98 | 686 | );\r |
687 | //\r | |
688 | // Need set IMAN IE bit to enble the ring interrupt\r | |
689 | //\r | |
6b4483cd | 690 | XhcSetRuntimeRegBit (Xhc, XHC_IMAN_OFFSET, XHC_IMAN_IE);\r |
92870c98 | 691 | }\r |
692 | \r | |
693 | /**\r | |
694 | Create XHCI transfer ring.\r | |
695 | \r | |
a9292c13 | 696 | @param Xhc The XHCI Instance.\r |
92870c98 | 697 | @param TrbNum The number of TRB in the ring.\r |
698 | @param TransferRing The created transfer ring.\r | |
699 | \r | |
700 | **/\r | |
701 | VOID\r | |
92870c98 | 702 | CreateTransferRing (\r |
a9292c13 | 703 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 704 | IN UINTN TrbNum,\r |
705 | OUT TRANSFER_RING *TransferRing\r | |
706 | )\r | |
707 | {\r | |
708 | VOID *Buf;\r | |
a9292c13 | 709 | LINK_TRB *EndTrb;\r |
92870c98 | 710 | \r |
a9292c13 | 711 | Buf = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TrbNum));\r |
92870c98 | 712 | ASSERT (Buf != NULL);\r |
713 | ASSERT (((UINTN) Buf & 0x3F) == 0);\r | |
a9292c13 | 714 | ZeroMem (Buf, sizeof (TRB_TEMPLATE) * TrbNum);\r |
92870c98 | 715 | \r |
716 | TransferRing->RingSeg0 = Buf;\r | |
717 | TransferRing->TrbNumber = TrbNum;\r | |
a9292c13 | 718 | TransferRing->RingEnqueue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r |
719 | TransferRing->RingDequeue = (TRB_TEMPLATE *) TransferRing->RingSeg0;\r | |
92870c98 | 720 | TransferRing->RingPCS = 1;\r |
721 | //\r | |
722 | // 4.9.2 Transfer Ring Management\r | |
723 | // To form a ring (or circular queue) a Link TRB may be inserted at the end of a ring to\r | |
724 | // point to the first TRB in the ring.\r | |
725 | //\r | |
a9292c13 | 726 | EndTrb = (LINK_TRB *) ((UINTN)Buf + sizeof (TRB_TEMPLATE) * (TrbNum - 1));\r |
92870c98 | 727 | EndTrb->Type = TRB_TYPE_LINK;\r |
728 | EndTrb->PtrLo = XHC_LOW_32BIT (Buf);\r | |
729 | EndTrb->PtrHi = XHC_HIGH_32BIT (Buf);\r | |
730 | //\r | |
731 | // Toggle Cycle (TC). When set to '1', the xHC shall toggle its interpretation of the Cycle bit.\r | |
732 | //\r | |
733 | EndTrb->TC = 1;\r | |
734 | //\r | |
735 | // Set Cycle bit as other TRB PCS init value\r | |
736 | //\r | |
737 | EndTrb->CycleBit = 0;\r | |
738 | }\r | |
739 | \r | |
740 | /**\r | |
741 | Free XHCI event ring.\r | |
742 | \r | |
a9292c13 | 743 | @param Xhc The XHCI Instance.\r |
92870c98 | 744 | @param EventRing The event ring to be freed.\r |
745 | \r | |
746 | **/\r | |
747 | EFI_STATUS\r | |
748 | EFIAPI\r | |
749 | XhcFreeEventRing (\r | |
a9292c13 | 750 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 751 | IN EVENT_RING *EventRing\r |
752 | )\r | |
753 | {\r | |
754 | UINT8 Index;\r | |
755 | EVENT_RING_SEG_TABLE_ENTRY *TablePtr;\r | |
756 | VOID *RingBuf;\r | |
757 | EVENT_RING_SEG_TABLE_ENTRY *EventRingPtr;\r | |
92870c98 | 758 | \r |
759 | if(EventRing->EventRingSeg0 == NULL) {\r | |
760 | return EFI_SUCCESS;\r | |
761 | }\r | |
762 | \r | |
92870c98 | 763 | //\r |
764 | // Get the Event Ring Segment Table base address\r | |
765 | //\r | |
766 | TablePtr = (EVENT_RING_SEG_TABLE_ENTRY *)(EventRing->ERSTBase);\r | |
767 | \r | |
768 | //\r | |
769 | // Get all the TRBs Ring and release\r | |
770 | //\r | |
771 | for (Index = 0; Index < ERST_NUMBER; Index++) {\r | |
772 | EventRingPtr = TablePtr + Index;\r | |
e0e7f80c | 773 | RingBuf = (VOID *)(UINTN)(EventRingPtr->PtrLo | LShiftU64 ((UINT64)EventRingPtr->PtrHi, 32));\r |
92870c98 | 774 | \r |
775 | if(RingBuf != NULL) {\r | |
a9292c13 | 776 | FreePages (RingBuf, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * EVENT_RING_TRB_NUMBER));\r |
92870c98 | 777 | ZeroMem (EventRingPtr, sizeof (EVENT_RING_SEG_TABLE_ENTRY));\r |
778 | }\r | |
779 | }\r | |
780 | \r | |
a9292c13 | 781 | FreePages (TablePtr, EFI_SIZE_TO_PAGES (sizeof (EVENT_RING_SEG_TABLE_ENTRY) * ERST_NUMBER));\r |
92870c98 | 782 | return EFI_SUCCESS;\r |
783 | }\r | |
784 | \r | |
785 | /**\r | |
786 | Free the resouce allocated at initializing schedule.\r | |
787 | \r | |
a9292c13 | 788 | @param Xhc The XHCI Instance.\r |
92870c98 | 789 | \r |
790 | **/\r | |
791 | VOID\r | |
792 | XhcFreeSched (\r | |
a9292c13 | 793 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 794 | )\r |
795 | {\r | |
796 | UINT32 Index;\r | |
a9292c13 | 797 | UINT64 *ScratchBuf;\r |
92870c98 | 798 | \r |
799 | if (Xhc->ScratchBuf != NULL) {\r | |
a9292c13 | 800 | ScratchBuf = Xhc->ScratchBuf;\r |
92870c98 | 801 | for (Index = 0; Index < Xhc->MaxScratchpadBufs; Index++) {\r |
a9292c13 | 802 | FreeAlignedPages ((VOID*)(UINTN)*ScratchBuf++, EFI_SIZE_TO_PAGES (Xhc->PageSize));\r |
92870c98 | 803 | }\r |
a9292c13 | 804 | FreeAlignedPages (Xhc->ScratchBuf, EFI_SIZE_TO_PAGES (Xhc->MaxScratchpadBufs * sizeof (UINT64)));\r |
92870c98 | 805 | }\r |
806 | \r | |
807 | if (Xhc->DCBAA != NULL) {\r | |
a9292c13 | 808 | FreePages (Xhc->DCBAA, EFI_SIZE_TO_PAGES((Xhc->MaxSlotsEn + 1) * sizeof(UINT64)));\r |
92870c98 | 809 | Xhc->DCBAA = NULL;\r |
810 | }\r | |
811 | \r | |
812 | if (Xhc->CmdRing.RingSeg0 != NULL){\r | |
a9292c13 | 813 | FreePages (Xhc->CmdRing.RingSeg0, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * CMD_RING_TRB_NUMBER));\r |
92870c98 | 814 | Xhc->CmdRing.RingSeg0 = NULL;\r |
815 | }\r | |
a9292c13 | 816 | \r |
6b4483cd | 817 | XhcFreeEventRing (Xhc,&Xhc->EventRing);\r |
92870c98 | 818 | }\r |
819 | \r | |
820 | /**\r | |
a50f7c4c | 821 | Check if the Trb is a transaction of the URBs in XHCI's asynchronous transfer list.\r |
822 | \r | |
823 | @param Xhc The XHCI Instance.\r | |
824 | @param Trb The TRB to be checked.\r | |
825 | @param Urb The pointer to the matched Urb.\r | |
826 | \r | |
827 | @retval TRUE The Trb is matched with a transaction of the URBs in the async list.\r | |
828 | @retval FALSE The Trb is not matched with any URBs in the async list.\r | |
829 | \r | |
830 | **/\r | |
831 | BOOLEAN\r | |
832 | IsAsyncIntTrb (\r | |
833 | IN USB_XHCI_INSTANCE *Xhc,\r | |
834 | IN TRB_TEMPLATE *Trb,\r | |
835 | OUT URB **Urb\r | |
836 | )\r | |
837 | {\r | |
838 | LIST_ENTRY *Entry;\r | |
839 | LIST_ENTRY *Next;\r | |
840 | TRB_TEMPLATE *CheckedTrb;\r | |
841 | URB *CheckedUrb;\r | |
842 | UINTN Index;\r | |
843 | \r | |
844 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r | |
845 | CheckedUrb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
846 | CheckedTrb = CheckedUrb->TrbStart;\r | |
847 | for (Index = 0; Index < CheckedUrb->TrbNum; Index++) {\r | |
848 | if (Trb == CheckedTrb) {\r | |
849 | *Urb = CheckedUrb;\r | |
850 | return TRUE;\r | |
851 | }\r | |
852 | CheckedTrb++;\r | |
853 | if ((UINTN)CheckedTrb >= ((UINTN) CheckedUrb->Ring->RingSeg0 + sizeof (TRB_TEMPLATE) * CheckedUrb->Ring->TrbNumber)) {\r | |
854 | CheckedTrb = (TRB_TEMPLATE*) CheckedUrb->Ring->RingSeg0;\r | |
855 | }\r | |
856 | }\r | |
857 | }\r | |
858 | \r | |
859 | return FALSE;\r | |
860 | }\r | |
861 | \r | |
862 | /**\r | |
863 | Check if the Trb is a transaction of the URB.\r | |
92870c98 | 864 | \r |
a50f7c4c | 865 | @param Trb The TRB to be checked\r |
866 | @param Urb The transfer ring to be checked.\r | |
92870c98 | 867 | \r |
a50f7c4c | 868 | @retval TRUE It is a transaction of the URB.\r |
869 | @retval FALSE It is not any transaction of the URB.\r | |
92870c98 | 870 | \r |
871 | **/\r | |
872 | BOOLEAN\r | |
873 | IsTransferRingTrb (\r | |
a50f7c4c | 874 | IN TRB_TEMPLATE *Trb,\r |
875 | IN URB *Urb\r | |
92870c98 | 876 | )\r |
877 | {\r | |
a50f7c4c | 878 | TRB_TEMPLATE *CheckedTrb;\r |
92870c98 | 879 | UINTN Index;\r |
880 | \r | |
a50f7c4c | 881 | CheckedTrb = Urb->Ring->RingSeg0;\r |
92870c98 | 882 | \r |
a50f7c4c | 883 | ASSERT (Urb->Ring->TrbNumber == CMD_RING_TRB_NUMBER || Urb->Ring->TrbNumber == TR_RING_TRB_NUMBER);\r |
92870c98 | 884 | \r |
a50f7c4c | 885 | for (Index = 0; Index < Urb->Ring->TrbNumber; Index++) {\r |
886 | if (Trb == CheckedTrb) {\r | |
887 | return TRUE;\r | |
92870c98 | 888 | }\r |
a50f7c4c | 889 | CheckedTrb++;\r |
92870c98 | 890 | }\r |
891 | \r | |
a50f7c4c | 892 | return FALSE;\r |
92870c98 | 893 | }\r |
894 | \r | |
895 | /**\r | |
896 | Check the URB's execution result and update the URB's\r | |
897 | result accordingly.\r | |
898 | \r | |
a9292c13 | 899 | @param Xhc The XHCI Instance.\r |
92870c98 | 900 | @param Urb The URB to check result.\r |
901 | \r | |
902 | @return Whether the result of URB transfer is finialized.\r | |
903 | \r | |
904 | **/\r | |
905 | EFI_STATUS\r | |
906 | XhcCheckUrbResult (\r | |
a9292c13 | 907 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 908 | IN URB *Urb\r |
909 | )\r | |
910 | {\r | |
92870c98 | 911 | EVT_TRB_TRANSFER *EvtTrb;\r |
a9292c13 | 912 | TRB_TEMPLATE *TRBPtr;\r |
92870c98 | 913 | UINTN Index;\r |
914 | UINT8 TRBType;\r | |
915 | EFI_STATUS Status;\r | |
a50f7c4c | 916 | URB *AsyncUrb;\r |
917 | URB *CheckedUrb;\r | |
918 | UINT64 XhcDequeue;\r | |
919 | UINT32 High;\r | |
920 | UINT32 Low;\r | |
92870c98 | 921 | \r |
922 | ASSERT ((Xhc != NULL) && (Urb != NULL));\r | |
923 | \r | |
09e4dbeb | 924 | Status = EFI_SUCCESS;\r |
925 | AsyncUrb = NULL;\r | |
a50f7c4c | 926 | \r |
927 | if (Urb->Finished) {\r | |
928 | goto EXIT;\r | |
929 | }\r | |
930 | \r | |
931 | EvtTrb = NULL;\r | |
92870c98 | 932 | \r |
933 | if (XhcIsHalt (Xhc) || XhcIsSysError (Xhc)) {\r | |
934 | Urb->Result |= EFI_USB_ERR_SYSTEM;\r | |
935 | Status = EFI_DEVICE_ERROR;\r | |
936 | goto EXIT;\r | |
937 | }\r | |
938 | \r | |
939 | //\r | |
a50f7c4c | 940 | // Traverse the event ring to find out all new events from the previous check.\r |
92870c98 | 941 | //\r |
a50f7c4c | 942 | XhcSyncEventRing (Xhc, &Xhc->EventRing);\r |
943 | for (Index = 0; Index < Xhc->EventRing.TrbNumber; Index++) {\r | |
944 | Status = XhcCheckNewEvent (Xhc, &Xhc->EventRing, ((TRB_TEMPLATE **)&EvtTrb));\r | |
92870c98 | 945 | if (Status == EFI_NOT_READY) {\r |
a50f7c4c | 946 | //\r |
947 | // All new events are handled, return directly.\r | |
948 | //\r | |
92870c98 | 949 | goto EXIT;\r |
950 | }\r | |
951 | \r | |
6b4483cd | 952 | //\r |
953 | // Only handle COMMAND_COMPLETETION_EVENT and TRANSFER_EVENT.\r | |
954 | //\r | |
955 | if ((EvtTrb->Type != TRB_TYPE_COMMAND_COMPLT_EVENT) && (EvtTrb->Type != TRB_TYPE_TRANS_EVENT)) {\r | |
956 | continue;\r | |
957 | }\r | |
92870c98 | 958 | \r |
e0e7f80c | 959 | TRBPtr = (TRB_TEMPLATE *)(UINTN)(EvtTrb->TRBPtrLo | LShiftU64 ((UINT64) EvtTrb->TRBPtrHi, 32));\r |
92870c98 | 960 | \r |
a50f7c4c | 961 | //\r |
962 | // Update the status of Urb according to the finished event regardless of whether\r | |
963 | // the urb is current checked one or in the XHCI's async transfer list.\r | |
964 | // This way is used to avoid that those completed async transfer events don't get\r | |
965 | // handled in time and are flushed by newer coming events.\r | |
966 | //\r | |
967 | if (IsTransferRingTrb (TRBPtr, Urb)) {\r | |
968 | CheckedUrb = Urb;\r | |
969 | } else if (IsAsyncIntTrb (Xhc, TRBPtr, &AsyncUrb)) { \r | |
970 | CheckedUrb = AsyncUrb;\r | |
971 | } else {\r | |
972 | continue;\r | |
973 | }\r | |
974 | \r | |
975 | switch (EvtTrb->Completecode) {\r | |
976 | case TRB_COMPLETION_STALL_ERROR:\r | |
977 | CheckedUrb->Result |= EFI_USB_ERR_STALL;\r | |
978 | CheckedUrb->Finished = TRUE;\r | |
979 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: STALL_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r | |
980 | break;\r | |
92870c98 | 981 | \r |
a50f7c4c | 982 | case TRB_COMPLETION_BABBLE_ERROR:\r |
983 | CheckedUrb->Result |= EFI_USB_ERR_BABBLE;\r | |
984 | CheckedUrb->Finished = TRUE;\r | |
985 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: BABBLE_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r | |
986 | break;\r | |
6b4483cd | 987 | \r |
a50f7c4c | 988 | case TRB_COMPLETION_DATA_BUFFER_ERROR:\r |
989 | CheckedUrb->Result |= EFI_USB_ERR_BUFFER;\r | |
990 | CheckedUrb->Finished = TRUE;\r | |
991 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: ERR_BUFFER! Completecode = %x\n",EvtTrb->Completecode));\r | |
6b4483cd | 992 | break;\r |
a50f7c4c | 993 | \r |
994 | case TRB_COMPLETION_USB_TRANSACTION_ERROR:\r | |
995 | CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r | |
996 | CheckedUrb->Finished = TRUE;\r | |
997 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: TRANSACTION_ERROR! Completecode = %x\n",EvtTrb->Completecode));\r | |
998 | break;\r | |
999 | \r | |
1000 | case TRB_COMPLETION_SHORT_PACKET:\r | |
1001 | case TRB_COMPLETION_SUCCESS:\r | |
1002 | if (EvtTrb->Completecode == TRB_COMPLETION_SHORT_PACKET) {\r | |
1003 | DEBUG ((EFI_D_ERROR, "XhcCheckUrbResult: short packet happens!\n"));\r | |
1004 | }\r | |
1005 | \r | |
1006 | TRBType = (UINT8) (TRBPtr->Type);\r | |
1007 | if ((TRBType == TRB_TYPE_DATA_STAGE) ||\r | |
1008 | (TRBType == TRB_TYPE_NORMAL) ||\r | |
1009 | (TRBType == TRB_TYPE_ISOCH)) {\r | |
1010 | CheckedUrb->Completed += (CheckedUrb->DataLen - EvtTrb->Lenth);\r | |
1011 | }\r | |
1012 | \r | |
1013 | break;\r | |
1014 | \r | |
1015 | default:\r | |
1016 | DEBUG ((EFI_D_ERROR, "Transfer Default Error Occur! Completecode = 0x%x!\n",EvtTrb->Completecode));\r | |
1017 | CheckedUrb->Result |= EFI_USB_ERR_TIMEOUT;\r | |
1018 | CheckedUrb->Finished = TRUE;\r | |
1019 | break;\r | |
1020 | }\r | |
1021 | \r | |
1022 | //\r | |
1023 | // Only check first and end Trb event address\r | |
1024 | //\r | |
1025 | if (TRBPtr == CheckedUrb->TrbStart) {\r | |
1026 | CheckedUrb->StartDone = TRUE;\r | |
1027 | }\r | |
1028 | \r | |
1029 | if (TRBPtr == CheckedUrb->TrbEnd) {\r | |
1030 | CheckedUrb->EndDone = TRUE;\r | |
1031 | }\r | |
1032 | \r | |
1033 | if (CheckedUrb->StartDone && CheckedUrb->EndDone) {\r | |
1034 | CheckedUrb->Finished = TRUE;\r | |
1035 | CheckedUrb->EvtTrb = (TRB_TEMPLATE *)EvtTrb;\r | |
92870c98 | 1036 | }\r |
1037 | }\r | |
1038 | \r | |
1039 | EXIT:\r | |
a50f7c4c | 1040 | \r |
1041 | //\r | |
1042 | // Advance event ring to last available entry\r | |
1043 | //\r | |
1044 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
1045 | // So divide it to two 32-bytes width register access.\r | |
1046 | //\r | |
1047 | Low = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET);\r | |
1048 | High = XhcReadRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4);\r | |
1049 | XhcDequeue = (UINT64)(LShiftU64((UINT64)High, 32) | Low);\r | |
1050 | \r | |
1051 | if ((XhcDequeue & (~0x0F)) != ((UINT64)(UINTN)Xhc->EventRing.EventRingDequeue & (~0x0F))) {\r | |
1052 | //\r | |
1053 | // Some 3rd party XHCI external cards don't support single 64-bytes width register access,\r | |
1054 | // So divide it to two 32-bytes width register access.\r | |
1055 | //\r | |
1056 | XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET, XHC_LOW_32BIT (Xhc->EventRing.EventRingDequeue) | BIT3);\r | |
1057 | XhcWriteRuntimeReg (Xhc, XHC_ERDP_OFFSET + 4, XHC_HIGH_32BIT (Xhc->EventRing.EventRingDequeue));\r | |
1058 | }\r | |
1059 | \r | |
92870c98 | 1060 | return Status;\r |
1061 | }\r | |
1062 | \r | |
1063 | \r | |
1064 | /**\r | |
1065 | Execute the transfer by polling the URB. This is a synchronous operation.\r | |
1066 | \r | |
a9292c13 | 1067 | @param Xhc The XHCI Instance.\r |
92870c98 | 1068 | @param CmdTransfer The executed URB is for cmd transfer or not.\r |
1069 | @param Urb The URB to execute.\r | |
a9292c13 | 1070 | @param Timeout The time to wait before abort, in millisecond.\r |
92870c98 | 1071 | \r |
1072 | @return EFI_DEVICE_ERROR The transfer failed due to transfer error.\r | |
1073 | @return EFI_TIMEOUT The transfer failed due to time out.\r | |
1074 | @return EFI_SUCCESS The transfer finished OK.\r | |
1075 | \r | |
1076 | **/\r | |
1077 | EFI_STATUS\r | |
1078 | XhcExecTransfer (\r | |
a9292c13 | 1079 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1080 | IN BOOLEAN CmdTransfer,\r |
1081 | IN URB *Urb,\r | |
a9292c13 | 1082 | IN UINTN Timeout\r |
92870c98 | 1083 | )\r |
1084 | {\r | |
1085 | EFI_STATUS Status;\r | |
1086 | UINTN Index;\r | |
1087 | UINTN Loop;\r | |
1088 | UINT8 SlotId;\r | |
1089 | UINT8 Dci;\r | |
1090 | \r | |
1091 | if (CmdTransfer) {\r | |
1092 | SlotId = 0;\r | |
1093 | Dci = 0;\r | |
1094 | } else {\r | |
6b4483cd | 1095 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
1096 | if (SlotId == 0) {\r | |
1097 | return EFI_DEVICE_ERROR;\r | |
1098 | }\r | |
1099 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r | |
1100 | ASSERT (Dci < 32);\r | |
92870c98 | 1101 | }\r |
1102 | \r | |
1103 | Status = EFI_SUCCESS;\r | |
a9292c13 | 1104 | Loop = (Timeout * XHC_1_MILLISECOND / XHC_POLL_DELAY) + 1;\r |
1105 | if (Timeout == 0) {\r | |
92870c98 | 1106 | Loop = 0xFFFFFFFF;\r |
1107 | }\r | |
1108 | \r | |
1109 | XhcRingDoorBell (Xhc, SlotId, Dci);\r | |
1110 | \r | |
1111 | for (Index = 0; Index < Loop; Index++) {\r | |
1112 | Status = XhcCheckUrbResult (Xhc, Urb);\r | |
a50f7c4c | 1113 | if (Urb->Finished) {\r |
92870c98 | 1114 | break;\r |
1115 | }\r | |
a9292c13 | 1116 | gBS->Stall (XHC_POLL_DELAY);\r |
92870c98 | 1117 | }\r |
1118 | \r | |
a50f7c4c | 1119 | if (Index == Loop) {\r |
1120 | Urb->Result = EFI_USB_ERR_TIMEOUT;\r | |
1121 | }\r | |
1122 | \r | |
92870c98 | 1123 | return Status;\r |
1124 | }\r | |
1125 | \r | |
1126 | /**\r | |
1127 | Delete a single asynchronous interrupt transfer for\r | |
1128 | the device and endpoint.\r | |
1129 | \r | |
a9292c13 | 1130 | @param Xhc The XHCI Instance.\r |
6b4483cd | 1131 | @param BusAddr The logical device address assigned by UsbBus driver.\r |
92870c98 | 1132 | @param EpNum The endpoint of the target.\r |
1133 | \r | |
1134 | @retval EFI_SUCCESS An asynchronous transfer is removed.\r | |
1135 | @retval EFI_NOT_FOUND No transfer for the device is found.\r | |
1136 | \r | |
1137 | **/\r | |
1138 | EFI_STATUS\r | |
1139 | XhciDelAsyncIntTransfer (\r | |
a9292c13 | 1140 | IN USB_XHCI_INSTANCE *Xhc,\r |
6b4483cd | 1141 | IN UINT8 BusAddr,\r |
92870c98 | 1142 | IN UINT8 EpNum\r |
1143 | )\r | |
1144 | {\r | |
1145 | LIST_ENTRY *Entry;\r | |
1146 | LIST_ENTRY *Next;\r | |
1147 | URB *Urb;\r | |
1148 | EFI_USB_DATA_DIRECTION Direction;\r | |
92870c98 | 1149 | \r |
1150 | Direction = ((EpNum & 0x80) != 0) ? EfiUsbDataIn : EfiUsbDataOut;\r | |
1151 | EpNum &= 0x0F;\r | |
1152 | \r | |
6b4483cd | 1153 | Urb = NULL;\r |
92870c98 | 1154 | \r |
1155 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r | |
1156 | Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
6b4483cd | 1157 | if ((Urb->Ep.BusAddr == BusAddr) &&\r |
92870c98 | 1158 | (Urb->Ep.EpAddr == EpNum) &&\r |
1159 | (Urb->Ep.Direction == Direction)) {\r | |
1160 | RemoveEntryList (&Urb->UrbList);\r | |
1161 | FreePool (Urb->Data);\r | |
1162 | FreePool (Urb);\r | |
1163 | return EFI_SUCCESS;\r | |
1164 | }\r | |
1165 | }\r | |
1166 | \r | |
1167 | return EFI_NOT_FOUND;\r | |
1168 | }\r | |
1169 | \r | |
1170 | /**\r | |
1171 | Remove all the asynchronous interrutp transfers.\r | |
1172 | \r | |
a9292c13 | 1173 | @param Xhc The XHCI Instance.\r |
92870c98 | 1174 | \r |
1175 | **/\r | |
1176 | VOID\r | |
1177 | XhciDelAllAsyncIntTransfers (\r | |
a9292c13 | 1178 | IN USB_XHCI_INSTANCE *Xhc\r |
92870c98 | 1179 | )\r |
1180 | {\r | |
1181 | LIST_ENTRY *Entry;\r | |
1182 | LIST_ENTRY *Next;\r | |
1183 | URB *Urb;\r | |
1184 | \r | |
1185 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r | |
1186 | Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
1187 | RemoveEntryList (&Urb->UrbList);\r | |
1188 | FreePool (Urb->Data);\r | |
1189 | FreePool (Urb);\r | |
1190 | }\r | |
1191 | }\r | |
1192 | \r | |
1193 | /**\r | |
1194 | Update the queue head for next round of asynchronous transfer\r | |
1195 | \r | |
a9292c13 | 1196 | @param Xhc The XHCI Instance.\r |
92870c98 | 1197 | @param Urb The URB to update\r |
1198 | \r | |
1199 | **/\r | |
1200 | VOID\r | |
1201 | XhcUpdateAsyncRequest (\r | |
a9292c13 | 1202 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1203 | IN URB *Urb\r |
1204 | )\r | |
1205 | {\r | |
1206 | EFI_STATUS Status;\r | |
1207 | \r | |
1208 | if (Urb->Result == EFI_USB_NOERROR) {\r | |
1209 | Status = XhcCreateTransferTrb (Xhc, Urb);\r | |
6b4483cd | 1210 | if (EFI_ERROR (Status)) {\r |
1211 | return;\r | |
1212 | }\r | |
92870c98 | 1213 | Status = RingIntTransferDoorBell (Xhc, Urb);\r |
6b4483cd | 1214 | if (EFI_ERROR (Status)) {\r |
1215 | return;\r | |
1216 | }\r | |
92870c98 | 1217 | }\r |
1218 | }\r | |
1219 | \r | |
1220 | \r | |
1221 | /**\r | |
1222 | Interrupt transfer periodic check handler.\r | |
1223 | \r | |
1224 | @param Event Interrupt event.\r | |
a9292c13 | 1225 | @param Context Pointer to USB_XHCI_INSTANCE.\r |
92870c98 | 1226 | \r |
1227 | **/\r | |
1228 | VOID\r | |
1229 | EFIAPI\r | |
1230 | XhcMonitorAsyncRequests (\r | |
1231 | IN EFI_EVENT Event,\r | |
1232 | IN VOID *Context\r | |
1233 | )\r | |
1234 | {\r | |
a9292c13 | 1235 | USB_XHCI_INSTANCE *Xhc;\r |
92870c98 | 1236 | LIST_ENTRY *Entry;\r |
1237 | LIST_ENTRY *Next;\r | |
1238 | UINT8 *ProcBuf;\r | |
1239 | URB *Urb;\r | |
1240 | UINT8 SlotId;\r | |
1241 | EFI_STATUS Status;\r | |
1242 | EFI_TPL OldTpl;\r | |
1243 | \r | |
1244 | OldTpl = gBS->RaiseTPL (XHC_TPL);\r | |
1245 | \r | |
a9292c13 | 1246 | Xhc = (USB_XHCI_INSTANCE*) Context;\r |
92870c98 | 1247 | \r |
1248 | EFI_LIST_FOR_EACH_SAFE (Entry, Next, &Xhc->AsyncIntTransfers) {\r | |
1249 | Urb = EFI_LIST_CONTAINER (Entry, URB, UrbList);\r | |
1250 | \r | |
1251 | //\r | |
1252 | // Make sure that the device is available before every check.\r | |
1253 | //\r | |
6b4483cd | 1254 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
92870c98 | 1255 | if (SlotId == 0) {\r |
1256 | continue;\r | |
1257 | }\r | |
1258 | \r | |
1259 | //\r | |
1260 | // Check the result of URB execution. If it is still\r | |
1261 | // active, check the next one.\r | |
1262 | //\r | |
1263 | Status = XhcCheckUrbResult (Xhc, Urb);\r | |
1264 | \r | |
a50f7c4c | 1265 | if (!Urb->Finished) {\r |
92870c98 | 1266 | continue;\r |
1267 | }\r | |
1268 | \r | |
1269 | //\r | |
1270 | // Allocate a buffer then copy the transferred data for user.\r | |
1271 | // If failed to allocate the buffer, update the URB for next\r | |
1272 | // round of transfer. Ignore the data of this round.\r | |
1273 | //\r | |
1274 | ProcBuf = NULL;\r | |
1275 | if (Urb->Result == EFI_USB_NOERROR) {\r | |
1276 | ASSERT (Urb->Completed <= Urb->DataLen);\r | |
1277 | \r | |
a9292c13 | 1278 | ProcBuf = AllocateZeroPool (Urb->Completed);\r |
92870c98 | 1279 | \r |
1280 | if (ProcBuf == NULL) {\r | |
1281 | XhcUpdateAsyncRequest (Xhc, Urb);\r | |
1282 | continue;\r | |
1283 | }\r | |
1284 | \r | |
1285 | CopyMem (ProcBuf, Urb->Data, Urb->Completed);\r | |
1286 | }\r | |
1287 | \r | |
92870c98 | 1288 | //\r |
1289 | // Leave error recovery to its related device driver. A\r | |
1290 | // common case of the error recovery is to re-submit the\r | |
1291 | // interrupt transfer which is linked to the head of the\r | |
1292 | // list. This function scans from head to tail. So the\r | |
1293 | // re-submitted interrupt transfer's callback function\r | |
1294 | // will not be called again in this round. Don't touch this\r | |
1295 | // URB after the callback, it may have been removed by the\r | |
1296 | // callback.\r | |
1297 | //\r | |
1298 | if (Urb->Callback != NULL) {\r | |
1299 | //\r | |
1300 | // Restore the old TPL, USB bus maybe connect device in\r | |
1301 | // his callback. Some drivers may has a lower TPL restriction.\r | |
1302 | //\r | |
1303 | gBS->RestoreTPL (OldTpl);\r | |
1304 | (Urb->Callback) (ProcBuf, Urb->Completed, Urb->Context, Urb->Result);\r | |
1305 | OldTpl = gBS->RaiseTPL (XHC_TPL);\r | |
1306 | }\r | |
1307 | \r | |
1308 | if (ProcBuf != NULL) {\r | |
1309 | gBS->FreePool (ProcBuf);\r | |
1310 | }\r | |
a50f7c4c | 1311 | \r |
1312 | XhcUpdateAsyncRequest (Xhc, Urb);\r | |
92870c98 | 1313 | }\r |
1314 | gBS->RestoreTPL (OldTpl);\r | |
1315 | }\r | |
1316 | \r | |
1317 | /**\r | |
1318 | Monitor the port status change. Enable/Disable device slot if there is a device attached/detached.\r | |
1319 | \r | |
a9292c13 | 1320 | @param Xhc The XHCI Instance.\r |
92870c98 | 1321 | @param ParentRouteChart The route string pointed to the parent device if it exists.\r |
1322 | @param Port The port to be polled.\r | |
1323 | @param PortState The port state.\r | |
1324 | \r | |
1325 | @retval EFI_SUCCESS Successfully enable/disable device slot according to port state.\r | |
1326 | @retval Others Should not appear.\r | |
1327 | \r | |
1328 | **/\r | |
1329 | EFI_STATUS\r | |
1330 | EFIAPI\r | |
1331 | XhcPollPortStatusChange (\r | |
a9292c13 | 1332 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1333 | IN USB_DEV_ROUTE ParentRouteChart,\r |
1334 | IN UINT8 Port,\r | |
1335 | IN EFI_USB_PORT_STATUS *PortState\r | |
1336 | )\r | |
1337 | {\r | |
1338 | EFI_STATUS Status;\r | |
1339 | UINT8 Speed;\r | |
1340 | UINT8 SlotId;\r | |
1341 | USB_DEV_ROUTE RouteChart;\r | |
1342 | \r | |
1343 | Status = EFI_SUCCESS;\r | |
1344 | \r | |
1345 | if (ParentRouteChart.Dword == 0) {\r | |
a9292c13 | 1346 | RouteChart.Route.RouteString = 0;\r |
1347 | RouteChart.Route.RootPortNum = Port + 1;\r | |
1348 | RouteChart.Route.TierNum = 1;\r | |
92870c98 | 1349 | } else {\r |
1350 | if(Port < 14) {\r | |
a9292c13 | 1351 | RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (Port << (4 * (ParentRouteChart.Route.TierNum - 1)));\r |
92870c98 | 1352 | } else {\r |
a9292c13 | 1353 | RouteChart.Route.RouteString = ParentRouteChart.Route.RouteString | (15 << (4 * (ParentRouteChart.Route.TierNum - 1)));\r |
92870c98 | 1354 | }\r |
a9292c13 | 1355 | RouteChart.Route.RootPortNum = ParentRouteChart.Route.RootPortNum;\r |
1356 | RouteChart.Route.TierNum = ParentRouteChart.Route.TierNum + 1;\r | |
92870c98 | 1357 | }\r |
1358 | \r | |
1359 | if (((PortState->PortStatus & USB_PORT_STAT_ENABLE) != 0) &&\r | |
1360 | ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) != 0)) {\r | |
1361 | //\r | |
1362 | // Has a device attached, Identify device speed after port is enabled.\r | |
1363 | //\r | |
1364 | Speed = EFI_USB_SPEED_FULL;\r | |
1365 | if ((PortState->PortStatus & USB_PORT_STAT_LOW_SPEED) != 0) {\r | |
1366 | Speed = EFI_USB_SPEED_LOW;\r | |
1367 | } else if ((PortState->PortStatus & USB_PORT_STAT_HIGH_SPEED) != 0) {\r | |
1368 | Speed = EFI_USB_SPEED_HIGH;\r | |
1369 | } else if ((PortState->PortStatus & USB_PORT_STAT_SUPER_SPEED) != 0) {\r | |
1370 | Speed = EFI_USB_SPEED_SUPER;\r | |
1371 | }\r | |
1372 | //\r | |
1373 | // Execute Enable_Slot cmd for attached device, initialize device context and assign device address.\r | |
1374 | //\r | |
a9292c13 | 1375 | SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r |
92870c98 | 1376 | if (SlotId == 0) {\r |
6b4483cd | 1377 | if (Xhc->HcCParams.Data.Csz == 0) {\r |
1378 | Status = XhcInitializeDeviceSlot (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r | |
1379 | } else {\r | |
1380 | Status = XhcInitializeDeviceSlot64 (Xhc, ParentRouteChart, Port, RouteChart, Speed);\r | |
1381 | }\r | |
92870c98 | 1382 | ASSERT_EFI_ERROR (Status);\r |
1383 | }\r | |
1384 | } else if ((PortState->PortStatus & USB_PORT_STAT_CONNECTION) == 0) {\r | |
1385 | //\r | |
1386 | // Device is detached. Disable the allocated device slot and release resource.\r | |
1387 | //\r | |
a9292c13 | 1388 | SlotId = XhcRouteStringToSlotId (Xhc, RouteChart);\r |
92870c98 | 1389 | if (SlotId != 0) {\r |
6b4483cd | 1390 | if (Xhc->HcCParams.Data.Csz == 0) {\r |
1391 | Status = XhcDisableSlotCmd (Xhc, SlotId);\r | |
1392 | } else {\r | |
1393 | Status = XhcDisableSlotCmd64 (Xhc, SlotId);\r | |
1394 | }\r | |
92870c98 | 1395 | ASSERT_EFI_ERROR (Status);\r |
1396 | }\r | |
1397 | }\r | |
1398 | return Status;\r | |
1399 | }\r | |
1400 | \r | |
1401 | \r | |
1402 | /**\r | |
1403 | Calculate the device context index by endpoint address and direction.\r | |
1404 | \r | |
1405 | @param EpAddr The target endpoint number.\r | |
1406 | @param Direction The direction of the target endpoint.\r | |
1407 | \r | |
1408 | @return The device context index of endpoint.\r | |
1409 | \r | |
1410 | **/\r | |
1411 | UINT8\r | |
1412 | XhcEndpointToDci (\r | |
1413 | IN UINT8 EpAddr,\r | |
1414 | IN UINT8 Direction\r | |
1415 | )\r | |
1416 | {\r | |
1417 | UINT8 Index;\r | |
1418 | \r | |
1419 | if (EpAddr == 0) {\r | |
1420 | return 1;\r | |
1421 | } else {\r | |
ce9b5900 | 1422 | Index = (UINT8) (2 * EpAddr);\r |
92870c98 | 1423 | if (Direction == EfiUsbDataIn) {\r |
1424 | Index += 1;\r | |
1425 | }\r | |
1426 | return Index;\r | |
1427 | }\r | |
1428 | }\r | |
1429 | \r | |
92870c98 | 1430 | /**\r |
1431 | Find out the actual device address according to the requested device address from UsbBus.\r | |
1432 | \r | |
a9292c13 | 1433 | @param Xhc The XHCI Instance.\r |
1434 | @param BusDevAddr The requested device address by UsbBus upper driver.\r | |
92870c98 | 1435 | \r |
1436 | @return The actual device address assigned to the device.\r | |
1437 | \r | |
1438 | **/\r | |
1439 | UINT8\r | |
1440 | EFIAPI\r | |
1441 | XhcBusDevAddrToSlotId (\r | |
a9292c13 | 1442 | IN USB_XHCI_INSTANCE *Xhc,\r |
1443 | IN UINT8 BusDevAddr\r | |
92870c98 | 1444 | )\r |
1445 | {\r | |
1446 | UINT8 Index;\r | |
1447 | \r | |
1448 | for (Index = 0; Index < 255; Index++) {\r | |
a9292c13 | 1449 | if (Xhc->UsbDevContext[Index + 1].Enabled &&\r |
1450 | (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r | |
1451 | (Xhc->UsbDevContext[Index + 1].BusDevAddr == BusDevAddr)) {\r | |
92870c98 | 1452 | break;\r |
1453 | }\r | |
1454 | }\r | |
1455 | \r | |
1456 | if (Index == 255) {\r | |
1457 | return 0;\r | |
1458 | }\r | |
1459 | \r | |
a9292c13 | 1460 | return Xhc->UsbDevContext[Index + 1].SlotId;\r |
92870c98 | 1461 | }\r |
1462 | \r | |
1463 | /**\r | |
1464 | Find out the slot id according to the device's route string.\r | |
1465 | \r | |
a9292c13 | 1466 | @param Xhc The XHCI Instance.\r |
1467 | @param RouteString The route string described the device location.\r | |
92870c98 | 1468 | \r |
1469 | @return The slot id used by the device.\r | |
1470 | \r | |
1471 | **/\r | |
1472 | UINT8\r | |
1473 | EFIAPI\r | |
1474 | XhcRouteStringToSlotId (\r | |
a9292c13 | 1475 | IN USB_XHCI_INSTANCE *Xhc,\r |
1476 | IN USB_DEV_ROUTE RouteString\r | |
92870c98 | 1477 | )\r |
1478 | {\r | |
1479 | UINT8 Index;\r | |
1480 | \r | |
1481 | for (Index = 0; Index < 255; Index++) {\r | |
a9292c13 | 1482 | if (Xhc->UsbDevContext[Index + 1].Enabled &&\r |
1483 | (Xhc->UsbDevContext[Index + 1].SlotId != 0) &&\r | |
1484 | (Xhc->UsbDevContext[Index + 1].RouteString.Dword == RouteString.Dword)) {\r | |
92870c98 | 1485 | break;\r |
1486 | }\r | |
1487 | }\r | |
1488 | \r | |
1489 | if (Index == 255) {\r | |
1490 | return 0;\r | |
1491 | }\r | |
1492 | \r | |
a9292c13 | 1493 | return Xhc->UsbDevContext[Index + 1].SlotId;\r |
92870c98 | 1494 | }\r |
1495 | \r | |
1496 | /**\r | |
1497 | Synchronize the specified event ring to update the enqueue and dequeue pointer.\r | |
1498 | \r | |
a9292c13 | 1499 | @param Xhc The XHCI Instance.\r |
92870c98 | 1500 | @param EvtRing The event ring to sync.\r |
1501 | \r | |
1502 | @retval EFI_SUCCESS The event ring is synchronized successfully.\r | |
1503 | \r | |
1504 | **/\r | |
1505 | EFI_STATUS\r | |
1506 | EFIAPI\r | |
1507 | XhcSyncEventRing (\r | |
a9292c13 | 1508 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1509 | IN EVENT_RING *EvtRing\r |
1510 | )\r | |
1511 | {\r | |
1512 | UINTN Index;\r | |
a9292c13 | 1513 | TRB_TEMPLATE *EvtTrb1;\r |
92870c98 | 1514 | \r |
1515 | ASSERT (EvtRing != NULL);\r | |
1516 | \r | |
1517 | //\r | |
1518 | // Calculate the EventRingEnqueue and EventRingCCS.\r | |
1519 | // Note: only support single Segment\r | |
1520 | //\r | |
a50f7c4c | 1521 | EvtTrb1 = EvtRing->EventRingDequeue;\r |
92870c98 | 1522 | \r |
1523 | for (Index = 0; Index < EvtRing->TrbNumber; Index++) {\r | |
a50f7c4c | 1524 | if (EvtTrb1->CycleBit != EvtRing->EventRingCCS) {\r |
92870c98 | 1525 | break;\r |
1526 | }\r | |
a50f7c4c | 1527 | \r |
92870c98 | 1528 | EvtTrb1++;\r |
a50f7c4c | 1529 | \r |
1530 | if ((UINTN)EvtTrb1 >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r | |
1531 | EvtTrb1 = EvtRing->EventRingSeg0;\r | |
1532 | EvtRing->EventRingCCS = (EvtRing->EventRingCCS) ? 0 : 1;\r | |
1533 | }\r | |
92870c98 | 1534 | }\r |
1535 | \r | |
1536 | if (Index < EvtRing->TrbNumber) {\r | |
1537 | EvtRing->EventRingEnqueue = EvtTrb1;\r | |
92870c98 | 1538 | } else {\r |
a50f7c4c | 1539 | ASSERT (FALSE);\r |
92870c98 | 1540 | }\r |
1541 | \r | |
1542 | return EFI_SUCCESS;\r | |
1543 | }\r | |
1544 | \r | |
1545 | /**\r | |
1546 | Synchronize the specified transfer ring to update the enqueue and dequeue pointer.\r | |
1547 | \r | |
a9292c13 | 1548 | @param Xhc The XHCI Instance.\r |
92870c98 | 1549 | @param TrsRing The transfer ring to sync.\r |
1550 | \r | |
1551 | @retval EFI_SUCCESS The transfer ring is synchronized successfully.\r | |
1552 | \r | |
1553 | **/\r | |
1554 | EFI_STATUS\r | |
1555 | EFIAPI\r | |
1556 | XhcSyncTrsRing (\r | |
a9292c13 | 1557 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1558 | IN TRANSFER_RING *TrsRing\r |
1559 | )\r | |
1560 | {\r | |
1561 | UINTN Index;\r | |
a9292c13 | 1562 | TRB_TEMPLATE *TrsTrb;\r |
92870c98 | 1563 | \r |
1564 | ASSERT (TrsRing != NULL);\r | |
1565 | //\r | |
1566 | // Calculate the latest RingEnqueue and RingPCS\r | |
1567 | //\r | |
1568 | TrsTrb = TrsRing->RingEnqueue;\r | |
1569 | ASSERT (TrsTrb != NULL);\r | |
1570 | \r | |
1571 | for (Index = 0; Index < TrsRing->TrbNumber; Index++) {\r | |
1572 | if (TrsTrb->CycleBit != (TrsRing->RingPCS & BIT0)) {\r | |
1573 | break;\r | |
1574 | }\r | |
1575 | TrsTrb++;\r | |
1576 | if ((UINT8) TrsTrb->Type == TRB_TYPE_LINK) {\r | |
a9292c13 | 1577 | ASSERT (((LINK_TRB*)TrsTrb)->TC != 0);\r |
92870c98 | 1578 | //\r |
1579 | // set cycle bit in Link TRB as normal\r | |
1580 | //\r | |
a9292c13 | 1581 | ((LINK_TRB*)TrsTrb)->CycleBit = TrsRing->RingPCS & BIT0;\r |
92870c98 | 1582 | //\r |
1583 | // Toggle PCS maintained by software\r | |
1584 | //\r | |
1585 | TrsRing->RingPCS = (TrsRing->RingPCS & BIT0) ? 0 : 1;\r | |
e0e7f80c | 1586 | TrsTrb = (TRB_TEMPLATE *)(UINTN)((TrsTrb->Parameter1 | LShiftU64 ((UINT64)TrsTrb->Parameter2, 32)) & ~0x0F);\r |
92870c98 | 1587 | }\r |
1588 | }\r | |
1589 | \r | |
1590 | ASSERT (Index != TrsRing->TrbNumber);\r | |
1591 | \r | |
1592 | if (TrsTrb != TrsRing->RingEnqueue) {\r | |
1593 | TrsRing->RingEnqueue = TrsTrb;\r | |
1594 | }\r | |
1595 | \r | |
1596 | //\r | |
1597 | // Clear the Trb context for enqueue, but reserve the PCS bit\r | |
1598 | //\r | |
a9292c13 | 1599 | TrsTrb->Parameter1 = 0;\r |
1600 | TrsTrb->Parameter2 = 0;\r | |
1601 | TrsTrb->Status = 0;\r | |
1602 | TrsTrb->RsvdZ1 = 0;\r | |
1603 | TrsTrb->Type = 0;\r | |
1604 | TrsTrb->Control = 0;\r | |
92870c98 | 1605 | \r |
1606 | return EFI_SUCCESS;\r | |
1607 | }\r | |
1608 | \r | |
1609 | /**\r | |
1610 | Check if there is a new generated event.\r | |
1611 | \r | |
a9292c13 | 1612 | @param Xhc The XHCI Instance.\r |
92870c98 | 1613 | @param EvtRing The event ring to check.\r |
1614 | @param NewEvtTrb The new event TRB found.\r | |
1615 | \r | |
1616 | @retval EFI_SUCCESS Found a new event TRB at the event ring.\r | |
1617 | @retval EFI_NOT_READY The event ring has no new event.\r | |
1618 | \r | |
1619 | **/\r | |
1620 | EFI_STATUS\r | |
1621 | EFIAPI\r | |
1622 | XhcCheckNewEvent (\r | |
a9292c13 | 1623 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1624 | IN EVENT_RING *EvtRing,\r |
a9292c13 | 1625 | OUT TRB_TEMPLATE **NewEvtTrb\r |
92870c98 | 1626 | )\r |
1627 | {\r | |
a50f7c4c | 1628 | EFI_STATUS Status;\r |
1629 | TRB_TEMPLATE *EvtTrb;\r | |
92870c98 | 1630 | \r |
1631 | ASSERT (EvtRing != NULL);\r | |
1632 | \r | |
1633 | EvtTrb = EvtRing->EventRingDequeue;\r | |
1634 | *NewEvtTrb = EvtRing->EventRingDequeue;\r | |
1635 | \r | |
1636 | if (EvtRing->EventRingDequeue == EvtRing->EventRingEnqueue) {\r | |
1637 | return EFI_NOT_READY;\r | |
1638 | }\r | |
1639 | \r | |
1640 | Status = EFI_SUCCESS;\r | |
1641 | \r | |
92870c98 | 1642 | EvtRing->EventRingDequeue++;\r |
1643 | //\r | |
1644 | // If the dequeue pointer is beyond the ring, then roll-back it to the begining of the ring.\r | |
1645 | //\r | |
a50f7c4c | 1646 | if ((UINTN)EvtRing->EventRingDequeue >= ((UINTN) EvtRing->EventRingSeg0 + sizeof (TRB_TEMPLATE) * EvtRing->TrbNumber)) {\r |
92870c98 | 1647 | EvtRing->EventRingDequeue = EvtRing->EventRingSeg0;\r |
1648 | }\r | |
1649 | \r | |
1650 | return Status;\r | |
1651 | }\r | |
1652 | \r | |
1653 | /**\r | |
1654 | Ring the door bell to notify XHCI there is a transaction to be executed.\r | |
1655 | \r | |
a9292c13 | 1656 | @param Xhc The XHCI Instance.\r |
92870c98 | 1657 | @param SlotId The slot id of the target device.\r |
1658 | @param Dci The device context index of the target slot or endpoint.\r | |
1659 | \r | |
1660 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
1661 | \r | |
1662 | **/\r | |
1663 | EFI_STATUS\r | |
1664 | EFIAPI\r | |
1665 | XhcRingDoorBell (\r | |
a9292c13 | 1666 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1667 | IN UINT8 SlotId,\r |
1668 | IN UINT8 Dci\r | |
1669 | )\r | |
1670 | {\r | |
1671 | if (SlotId == 0) {\r | |
1672 | XhcWriteDoorBellReg (Xhc, 0, 0);\r | |
1673 | } else {\r | |
1674 | XhcWriteDoorBellReg (Xhc, SlotId * sizeof (UINT32), Dci);\r | |
1675 | }\r | |
1676 | \r | |
1677 | return EFI_SUCCESS;\r | |
1678 | }\r | |
1679 | \r | |
1680 | /**\r | |
1681 | Ring the door bell to notify XHCI there is a transaction to be executed through URB.\r | |
1682 | \r | |
a9292c13 | 1683 | @param Xhc The XHCI Instance.\r |
92870c98 | 1684 | @param Urb The URB to be rung.\r |
1685 | \r | |
1686 | @retval EFI_SUCCESS Successfully ring the door bell.\r | |
1687 | \r | |
1688 | **/\r | |
1689 | EFI_STATUS\r | |
1690 | RingIntTransferDoorBell (\r | |
a9292c13 | 1691 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1692 | IN URB *Urb\r |
1693 | )\r | |
1694 | {\r | |
1695 | UINT8 SlotId;\r | |
1696 | UINT8 Dci;\r | |
1697 | \r | |
6b4483cd | 1698 | SlotId = XhcBusDevAddrToSlotId (Xhc, Urb->Ep.BusAddr);\r |
1699 | Dci = XhcEndpointToDci (Urb->Ep.EpAddr, (UINT8)(Urb->Ep.Direction));\r | |
92870c98 | 1700 | XhcRingDoorBell (Xhc, SlotId, Dci);\r |
1701 | return EFI_SUCCESS;\r | |
1702 | }\r | |
1703 | \r | |
1704 | /**\r | |
1705 | Assign and initialize the device slot for a new device.\r | |
1706 | \r | |
a9292c13 | 1707 | @param Xhc The XHCI Instance.\r |
92870c98 | 1708 | @param ParentRouteChart The route string pointed to the parent device.\r |
1709 | @param ParentPort The port at which the device is located.\r | |
1710 | @param RouteChart The route string pointed to the device.\r | |
1711 | @param DeviceSpeed The device speed.\r | |
1712 | \r | |
1713 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r | |
1714 | \r | |
1715 | **/\r | |
1716 | EFI_STATUS\r | |
1717 | EFIAPI\r | |
1718 | XhcInitializeDeviceSlot (\r | |
a9292c13 | 1719 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 1720 | IN USB_DEV_ROUTE ParentRouteChart,\r |
1721 | IN UINT16 ParentPort,\r | |
1722 | IN USB_DEV_ROUTE RouteChart,\r | |
1723 | IN UINT8 DeviceSpeed\r | |
1724 | )\r | |
1725 | {\r | |
a9292c13 | 1726 | EFI_STATUS Status;\r |
1727 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
1728 | INPUT_CONTEXT *InputContext;\r | |
1729 | DEVICE_CONTEXT *OutputContext;\r | |
1730 | TRANSFER_RING *EndpointTransferRing;\r | |
1731 | CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r | |
1732 | UINT8 DeviceAddress;\r | |
1733 | CMD_TRB_ENABLE_SLOT CmdTrb;\r | |
1734 | UINT8 SlotId;\r | |
1735 | UINT8 ParentSlotId;\r | |
1736 | DEVICE_CONTEXT *ParentDeviceContext;\r | |
1737 | \r | |
1738 | ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r | |
92870c98 | 1739 | CmdTrb.CycleBit = 1;\r |
1740 | CmdTrb.Type = TRB_TYPE_EN_SLOT;\r | |
1741 | \r | |
1742 | Status = XhcCmdTransfer (\r | |
1743 | Xhc,\r | |
a9292c13 | 1744 | (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r |
92870c98 | 1745 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 1746 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 1747 | );\r |
1748 | ASSERT_EFI_ERROR (Status);\r | |
1749 | ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r | |
1750 | DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r | |
1751 | SlotId = (UINT8)EvtTrb->SlotId;\r | |
1752 | ASSERT (SlotId != 0);\r | |
1753 | \r | |
a9292c13 | 1754 | ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r |
1755 | Xhc->UsbDevContext[SlotId].Enabled = TRUE;\r | |
1756 | Xhc->UsbDevContext[SlotId].SlotId = SlotId;\r | |
1757 | Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;\r | |
1758 | Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r | |
92870c98 | 1759 | \r |
1760 | //\r | |
1761 | // 4.3.3 Device Slot Initialization\r | |
1762 | // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r | |
1763 | //\r | |
a9292c13 | 1764 | InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));\r |
92870c98 | 1765 | ASSERT (InputContext != NULL);\r |
1766 | ASSERT (((UINTN) InputContext & 0x3F) == 0);\r | |
a9292c13 | 1767 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r |
92870c98 | 1768 | \r |
a9292c13 | 1769 | Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r |
92870c98 | 1770 | \r |
1771 | //\r | |
1772 | // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r | |
1773 | // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r | |
1774 | // Context are affected by the command.\r | |
1775 | //\r | |
1776 | InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r | |
1777 | \r | |
1778 | //\r | |
1779 | // 3) Initialize the Input Slot Context data structure\r | |
1780 | //\r | |
a9292c13 | 1781 | InputContext->Slot.RouteString = RouteChart.Route.RouteString;\r |
92870c98 | 1782 | InputContext->Slot.Speed = DeviceSpeed + 1;\r |
1783 | InputContext->Slot.ContextEntries = 1;\r | |
a9292c13 | 1784 | InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r |
92870c98 | 1785 | \r |
a9292c13 | 1786 | if (RouteChart.Route.RouteString) {\r |
92870c98 | 1787 | //\r |
1788 | // The device is behind of hub device.\r | |
1789 | //\r | |
a9292c13 | 1790 | ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r |
92870c98 | 1791 | ASSERT (ParentSlotId != 0);\r |
1792 | //\r | |
1793 | //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r | |
1794 | //\r | |
a9292c13 | 1795 | ParentDeviceContext = (DEVICE_CONTEXT *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r |
92870c98 | 1796 | if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r |
1797 | (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r | |
1798 | if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r | |
1799 | //\r | |
1800 | // Full/Low device attached to High speed hub port that isolates the high speed signaling\r | |
1801 | // environment from Full/Low speed signaling environment for a device\r | |
1802 | //\r | |
1803 | InputContext->Slot.TTPortNum = ParentPort;\r | |
1804 | InputContext->Slot.TTHubSlotId = ParentSlotId;\r | |
1805 | }\r | |
1806 | } else {\r | |
1807 | //\r | |
1808 | // Inherit the TT parameters from parent device.\r | |
1809 | //\r | |
1810 | InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;\r | |
1811 | InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r | |
1812 | //\r | |
1813 | // If the device is a High speed device then down the speed to be the same as its parent Hub\r | |
1814 | //\r | |
1815 | if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
1816 | InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r | |
1817 | }\r | |
1818 | }\r | |
1819 | }\r | |
1820 | \r | |
1821 | //\r | |
1822 | // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r | |
1823 | //\r | |
a9292c13 | 1824 | EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r |
1825 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r | |
1826 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r | |
92870c98 | 1827 | //\r |
1828 | // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r | |
1829 | //\r | |
1830 | InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r | |
1831 | \r | |
1832 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
1833 | InputContext->EP[0].MaxPacketSize = 512;\r | |
1834 | } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
1835 | InputContext->EP[0].MaxPacketSize = 64;\r | |
1836 | } else {\r | |
1837 | InputContext->EP[0].MaxPacketSize = 8;\r | |
1838 | }\r | |
1839 | //\r | |
1840 | // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r | |
1841 | // 1KB, and Bulk and Isoch endpoints 3KB.\r | |
1842 | //\r | |
1843 | InputContext->EP[0].AverageTRBLength = 8;\r | |
1844 | InputContext->EP[0].MaxBurstSize = 0;\r | |
1845 | InputContext->EP[0].Interval = 0;\r | |
1846 | InputContext->EP[0].MaxPStreams = 0;\r | |
1847 | InputContext->EP[0].Mult = 0;\r | |
1848 | InputContext->EP[0].CErr = 3;\r | |
1849 | \r | |
1850 | //\r | |
1851 | // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r | |
1852 | //\r | |
a9292c13 | 1853 | InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;\r |
1854 | InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);\r | |
92870c98 | 1855 | \r |
1856 | //\r | |
1857 | // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r | |
1858 | //\r | |
a9292c13 | 1859 | OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));\r |
1860 | ASSERT (OutputContext != NULL);\r | |
1861 | ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r | |
1862 | ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT));\r | |
92870c98 | 1863 | \r |
a9292c13 | 1864 | Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r |
92870c98 | 1865 | //\r |
1866 | // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r | |
1867 | // a pointer to the Output Device Context data structure (6.2.1).\r | |
1868 | //\r | |
a9292c13 | 1869 | Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;\r |
92870c98 | 1870 | \r |
1871 | //\r | |
1872 | // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r | |
1873 | // Context data structure described above.\r | |
1874 | //\r | |
1875 | ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r | |
a9292c13 | 1876 | CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r |
1877 | CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r | |
92870c98 | 1878 | CmdTrbAddr.CycleBit = 1;\r |
1879 | CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r | |
a9292c13 | 1880 | CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 1881 | Status = XhcCmdTransfer (\r |
1882 | Xhc,\r | |
a9292c13 | 1883 | (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r |
92870c98 | 1884 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 1885 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 1886 | );\r |
1887 | ASSERT (!EFI_ERROR(Status));\r | |
1888 | \r | |
a9292c13 | 1889 | DeviceAddress = (UINT8) ((DEVICE_CONTEXT *) OutputContext)->Slot.DeviceAddress;\r |
a50f7c4c | 1890 | DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));\r |
92870c98 | 1891 | \r |
a9292c13 | 1892 | Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r |
92870c98 | 1893 | \r |
1894 | return Status;\r | |
1895 | }\r | |
1896 | \r | |
1897 | /**\r | |
6b4483cd | 1898 | Assign and initialize the device slot for a new device.\r |
92870c98 | 1899 | \r |
6b4483cd | 1900 | @param Xhc The XHCI Instance.\r |
1901 | @param ParentRouteChart The route string pointed to the parent device.\r | |
1902 | @param ParentPort The port at which the device is located.\r | |
1903 | @param RouteChart The route string pointed to the device.\r | |
1904 | @param DeviceSpeed The device speed.\r | |
92870c98 | 1905 | \r |
6b4483cd | 1906 | @retval EFI_SUCCESS Successfully assign a slot to the device and assign an address to it.\r |
92870c98 | 1907 | \r |
1908 | **/\r | |
1909 | EFI_STATUS\r | |
1910 | EFIAPI\r | |
6b4483cd | 1911 | XhcInitializeDeviceSlot64 (\r |
1912 | IN USB_XHCI_INSTANCE *Xhc,\r | |
1913 | IN USB_DEV_ROUTE ParentRouteChart,\r | |
1914 | IN UINT16 ParentPort,\r | |
1915 | IN USB_DEV_ROUTE RouteChart,\r | |
1916 | IN UINT8 DeviceSpeed\r | |
92870c98 | 1917 | )\r |
1918 | {\r | |
6b4483cd | 1919 | EFI_STATUS Status;\r |
1920 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
1921 | INPUT_CONTEXT_64 *InputContext;\r | |
1922 | DEVICE_CONTEXT_64 *OutputContext;\r | |
1923 | TRANSFER_RING *EndpointTransferRing;\r | |
1924 | CMD_TRB_ADDRESS_DEVICE CmdTrbAddr;\r | |
1925 | UINT8 DeviceAddress;\r | |
1926 | CMD_TRB_ENABLE_SLOT CmdTrb;\r | |
1927 | UINT8 SlotId;\r | |
1928 | UINT8 ParentSlotId;\r | |
1929 | DEVICE_CONTEXT_64 *ParentDeviceContext;\r | |
92870c98 | 1930 | \r |
6b4483cd | 1931 | ZeroMem (&CmdTrb, sizeof (CMD_TRB_ENABLE_SLOT));\r |
1932 | CmdTrb.CycleBit = 1;\r | |
1933 | CmdTrb.Type = TRB_TYPE_EN_SLOT;\r | |
92870c98 | 1934 | \r |
6b4483cd | 1935 | Status = XhcCmdTransfer (\r |
1936 | Xhc,\r | |
1937 | (TRB_TEMPLATE *) (UINTN) &CmdTrb,\r | |
1938 | XHC_GENERIC_TIMEOUT,\r | |
1939 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
1940 | );\r | |
1941 | ASSERT_EFI_ERROR (Status);\r | |
1942 | ASSERT (EvtTrb->SlotId <= Xhc->MaxSlotsEn);\r | |
1943 | DEBUG ((EFI_D_INFO, "Enable Slot Successfully, The Slot ID = 0x%x\n", EvtTrb->SlotId));\r | |
1944 | SlotId = (UINT8)EvtTrb->SlotId;\r | |
1945 | ASSERT (SlotId != 0);\r | |
92870c98 | 1946 | \r |
6b4483cd | 1947 | ZeroMem (&Xhc->UsbDevContext[SlotId], sizeof (USB_DEV_CONTEXT));\r |
1948 | Xhc->UsbDevContext[SlotId].Enabled = TRUE;\r | |
1949 | Xhc->UsbDevContext[SlotId].SlotId = SlotId;\r | |
1950 | Xhc->UsbDevContext[SlotId].RouteString.Dword = RouteChart.Dword;\r | |
1951 | Xhc->UsbDevContext[SlotId].ParentRouteString.Dword = ParentRouteChart.Dword;\r | |
92870c98 | 1952 | \r |
1953 | //\r | |
6b4483cd | 1954 | // 4.3.3 Device Slot Initialization\r |
1955 | // 1) Allocate an Input Context data structure (6.2.5) and initialize all fields to '0'.\r | |
92870c98 | 1956 | //\r |
6b4483cd | 1957 | InputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));\r |
1958 | ASSERT (InputContext != NULL);\r | |
1959 | ASSERT (((UINTN) InputContext & 0x3F) == 0);\r | |
1960 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r | |
1961 | \r | |
1962 | Xhc->UsbDevContext[SlotId].InputContext = (VOID *) InputContext;\r | |
92870c98 | 1963 | \r |
92870c98 | 1964 | //\r |
6b4483cd | 1965 | // 2) Initialize the Input Control Context (6.2.5.1) of the Input Context by setting the A0 and A1\r |
1966 | // flags to '1'. These flags indicate that the Slot Context and the Endpoint 0 Context of the Input\r | |
1967 | // Context are affected by the command.\r | |
92870c98 | 1968 | //\r |
6b4483cd | 1969 | InputContext->InputControlContext.Dword2 |= (BIT0 | BIT1);\r |
92870c98 | 1970 | \r |
1971 | //\r | |
6b4483cd | 1972 | // 3) Initialize the Input Slot Context data structure\r |
92870c98 | 1973 | //\r |
6b4483cd | 1974 | InputContext->Slot.RouteString = RouteChart.Route.RouteString;\r |
1975 | InputContext->Slot.Speed = DeviceSpeed + 1;\r | |
1976 | InputContext->Slot.ContextEntries = 1;\r | |
1977 | InputContext->Slot.RootHubPortNum = RouteChart.Route.RootPortNum;\r | |
92870c98 | 1978 | \r |
6b4483cd | 1979 | if (RouteChart.Route.RouteString) {\r |
1980 | //\r | |
1981 | // The device is behind of hub device.\r | |
1982 | //\r | |
1983 | ParentSlotId = XhcRouteStringToSlotId(Xhc, ParentRouteChart);\r | |
1984 | ASSERT (ParentSlotId != 0);\r | |
1985 | //\r | |
1986 | //if the Full/Low device attached to a High Speed Hub, Init the TTPortNum and TTHubSlotId field of slot context\r | |
1987 | //\r | |
1988 | ParentDeviceContext = (DEVICE_CONTEXT_64 *)Xhc->UsbDevContext[ParentSlotId].OutputContext;\r | |
1989 | if ((ParentDeviceContext->Slot.TTPortNum == 0) &&\r | |
1990 | (ParentDeviceContext->Slot.TTHubSlotId == 0)) {\r | |
1991 | if ((ParentDeviceContext->Slot.Speed == (EFI_USB_SPEED_HIGH + 1)) && (DeviceSpeed < EFI_USB_SPEED_HIGH)) {\r | |
1992 | //\r | |
1993 | // Full/Low device attached to High speed hub port that isolates the high speed signaling\r | |
1994 | // environment from Full/Low speed signaling environment for a device\r | |
1995 | //\r | |
1996 | InputContext->Slot.TTPortNum = ParentPort;\r | |
1997 | InputContext->Slot.TTHubSlotId = ParentSlotId;\r | |
1998 | }\r | |
1999 | } else {\r | |
2000 | //\r | |
2001 | // Inherit the TT parameters from parent device.\r | |
2002 | //\r | |
2003 | InputContext->Slot.TTPortNum = ParentDeviceContext->Slot.TTPortNum;\r | |
2004 | InputContext->Slot.TTHubSlotId = ParentDeviceContext->Slot.TTHubSlotId;\r | |
2005 | //\r | |
2006 | // If the device is a High speed device then down the speed to be the same as its parent Hub\r | |
2007 | //\r | |
2008 | if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
2009 | InputContext->Slot.Speed = ParentDeviceContext->Slot.Speed;\r | |
2010 | }\r | |
92870c98 | 2011 | }\r |
2012 | }\r | |
2013 | \r | |
92870c98 | 2014 | //\r |
6b4483cd | 2015 | // 4) Allocate and initialize the Transfer Ring for the Default Control Endpoint.\r |
92870c98 | 2016 | //\r |
6b4483cd | 2017 | EndpointTransferRing = AllocateZeroPool (sizeof (TRANSFER_RING));\r |
2018 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[0] = EndpointTransferRing;\r | |
2019 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0]);\r | |
2020 | //\r | |
2021 | // 5) Initialize the Input default control Endpoint 0 Context (6.2.3).\r | |
2022 | //\r | |
2023 | InputContext->EP[0].EPType = ED_CONTROL_BIDIR;\r | |
2024 | \r | |
2025 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
2026 | InputContext->EP[0].MaxPacketSize = 512;\r | |
2027 | } else if (DeviceSpeed == EFI_USB_SPEED_HIGH) {\r | |
2028 | InputContext->EP[0].MaxPacketSize = 64;\r | |
2029 | } else {\r | |
2030 | InputContext->EP[0].MaxPacketSize = 8;\r | |
2031 | }\r | |
2032 | //\r | |
2033 | // Initial value of Average TRB Length for Control endpoints would be 8B, Interrupt endpoints\r | |
2034 | // 1KB, and Bulk and Isoch endpoints 3KB.\r | |
2035 | //\r | |
2036 | InputContext->EP[0].AverageTRBLength = 8;\r | |
2037 | InputContext->EP[0].MaxBurstSize = 0;\r | |
2038 | InputContext->EP[0].Interval = 0;\r | |
2039 | InputContext->EP[0].MaxPStreams = 0;\r | |
2040 | InputContext->EP[0].Mult = 0;\r | |
2041 | InputContext->EP[0].CErr = 3;\r | |
2042 | \r | |
2043 | //\r | |
2044 | // Init the DCS(dequeue cycle state) as the transfer ring's CCS\r | |
2045 | //\r | |
2046 | InputContext->EP[0].PtrLo = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0) | BIT0;\r | |
2047 | InputContext->EP[0].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[0])->RingSeg0);\r | |
2048 | \r | |
2049 | //\r | |
2050 | // 6) Allocate the Output Device Context data structure (6.2.1) and initialize it to '0'.\r | |
2051 | //\r | |
2052 | OutputContext = AllocatePages (EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));\r | |
2053 | ASSERT (OutputContext != NULL);\r | |
2054 | ASSERT (((UINTN) OutputContext & 0x3F) == 0);\r | |
2055 | ZeroMem (OutputContext, sizeof (DEVICE_CONTEXT_64));\r | |
2056 | \r | |
2057 | Xhc->UsbDevContext[SlotId].OutputContext = OutputContext;\r | |
2058 | //\r | |
2059 | // 7) Load the appropriate (Device Slot ID) entry in the Device Context Base Address Array (5.4.6) with\r | |
2060 | // a pointer to the Output Device Context data structure (6.2.1).\r | |
2061 | //\r | |
2062 | Xhc->DCBAA[SlotId] = (UINT64) (UINTN) OutputContext;\r | |
2063 | \r | |
2064 | //\r | |
2065 | // 8) Issue an Address Device Command for the Device Slot, where the command points to the Input\r | |
2066 | // Context data structure described above.\r | |
2067 | //\r | |
2068 | ZeroMem (&CmdTrbAddr, sizeof (CmdTrbAddr));\r | |
2069 | CmdTrbAddr.PtrLo = XHC_LOW_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r | |
2070 | CmdTrbAddr.PtrHi = XHC_HIGH_32BIT (Xhc->UsbDevContext[SlotId].InputContext);\r | |
2071 | CmdTrbAddr.CycleBit = 1;\r | |
2072 | CmdTrbAddr.Type = TRB_TYPE_ADDRESS_DEV;\r | |
2073 | CmdTrbAddr.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
2074 | Status = XhcCmdTransfer (\r | |
2075 | Xhc,\r | |
2076 | (TRB_TEMPLATE *) (UINTN) &CmdTrbAddr,\r | |
2077 | XHC_GENERIC_TIMEOUT,\r | |
2078 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2079 | );\r | |
2080 | ASSERT (!EFI_ERROR(Status));\r | |
2081 | \r | |
2082 | DeviceAddress = (UINT8) ((DEVICE_CONTEXT_64 *) OutputContext)->Slot.DeviceAddress;\r | |
a50f7c4c | 2083 | DEBUG ((EFI_D_INFO, " Address %d assigned successfully\n", DeviceAddress));\r |
6b4483cd | 2084 | \r |
2085 | Xhc->UsbDevContext[SlotId].XhciDevAddr = DeviceAddress;\r | |
2086 | \r | |
2087 | return Status;\r | |
2088 | }\r | |
2089 | \r | |
2090 | \r | |
2091 | /**\r | |
2092 | Disable the specified device slot.\r | |
2093 | \r | |
2094 | @param Xhc The XHCI Instance.\r | |
2095 | @param SlotId The slot id to be disabled.\r | |
2096 | \r | |
2097 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
2098 | \r | |
2099 | **/\r | |
2100 | EFI_STATUS\r | |
2101 | EFIAPI\r | |
2102 | XhcDisableSlotCmd (\r | |
2103 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2104 | IN UINT8 SlotId\r | |
2105 | )\r | |
2106 | {\r | |
2107 | EFI_STATUS Status;\r | |
2108 | TRB_TEMPLATE *EvtTrb;\r | |
2109 | CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;\r | |
2110 | UINT8 Index;\r | |
2111 | VOID *RingSeg;\r | |
2112 | \r | |
2113 | //\r | |
2114 | // Disable the device slots occupied by these devices on its downstream ports.\r | |
2115 | // Entry 0 is reserved.\r | |
2116 | //\r | |
2117 | for (Index = 0; Index < 255; Index++) {\r | |
2118 | if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r | |
2119 | (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r | |
2120 | (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r | |
2121 | continue;\r | |
2122 | }\r | |
2123 | \r | |
2124 | Status = XhcDisableSlotCmd (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r | |
2125 | \r | |
2126 | if (EFI_ERROR (Status)) {\r | |
2127 | DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r | |
2128 | Xhc->UsbDevContext[Index + 1].SlotId = 0;\r | |
2129 | }\r | |
2130 | }\r | |
2131 | \r | |
2132 | //\r | |
2133 | // Construct the disable slot command\r | |
2134 | //\r | |
2135 | DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r | |
2136 | \r | |
2137 | ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r | |
2138 | CmdTrbDisSlot.CycleBit = 1;\r | |
2139 | CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r | |
2140 | CmdTrbDisSlot.SlotId = SlotId;\r | |
2141 | Status = XhcCmdTransfer (\r | |
2142 | Xhc,\r | |
2143 | (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r | |
2144 | XHC_GENERIC_TIMEOUT,\r | |
2145 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2146 | );\r | |
2147 | ASSERT_EFI_ERROR(Status);\r | |
2148 | //\r | |
2149 | // Free the slot's device context entry\r | |
2150 | //\r | |
2151 | Xhc->DCBAA[SlotId] = 0;\r | |
2152 | \r | |
2153 | //\r | |
2154 | // Free the slot related data structure\r | |
2155 | //\r | |
2156 | for (Index = 0; Index < 31; Index++) {\r | |
2157 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r | |
2158 | RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r | |
2159 | if (RingSeg != NULL) {\r | |
2160 | FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));\r | |
2161 | }\r | |
2162 | FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r | |
2163 | }\r | |
2164 | }\r | |
2165 | \r | |
2166 | for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r | |
2167 | if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r | |
2168 | FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r | |
2169 | }\r | |
2170 | }\r | |
2171 | \r | |
2172 | if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r | |
2173 | FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT)));\r | |
2174 | }\r | |
2175 | \r | |
2176 | if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r | |
2177 | FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT)));\r | |
2178 | }\r | |
2179 | //\r | |
2180 | // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r | |
2181 | // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r | |
2182 | // remove urb from XHCI's asynchronous transfer list.\r | |
2183 | //\r | |
2184 | Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r | |
2185 | Xhc->UsbDevContext[SlotId].SlotId = 0;\r | |
2186 | \r | |
2187 | return Status;\r | |
2188 | }\r | |
2189 | \r | |
2190 | /**\r | |
2191 | Disable the specified device slot.\r | |
2192 | \r | |
2193 | @param Xhc The XHCI Instance.\r | |
2194 | @param SlotId The slot id to be disabled.\r | |
2195 | \r | |
2196 | @retval EFI_SUCCESS Successfully disable the device slot.\r | |
2197 | \r | |
2198 | **/\r | |
2199 | EFI_STATUS\r | |
2200 | EFIAPI\r | |
2201 | XhcDisableSlotCmd64 (\r | |
2202 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2203 | IN UINT8 SlotId\r | |
2204 | )\r | |
2205 | {\r | |
2206 | EFI_STATUS Status;\r | |
2207 | TRB_TEMPLATE *EvtTrb;\r | |
2208 | CMD_TRB_DISABLE_SLOT CmdTrbDisSlot;\r | |
2209 | UINT8 Index;\r | |
2210 | VOID *RingSeg;\r | |
2211 | \r | |
2212 | //\r | |
2213 | // Disable the device slots occupied by these devices on its downstream ports.\r | |
2214 | // Entry 0 is reserved.\r | |
2215 | //\r | |
2216 | for (Index = 0; Index < 255; Index++) {\r | |
2217 | if (!Xhc->UsbDevContext[Index + 1].Enabled ||\r | |
2218 | (Xhc->UsbDevContext[Index + 1].SlotId == 0) ||\r | |
2219 | (Xhc->UsbDevContext[Index + 1].ParentRouteString.Dword != Xhc->UsbDevContext[SlotId].RouteString.Dword)) {\r | |
2220 | continue;\r | |
2221 | }\r | |
2222 | \r | |
2223 | Status = XhcDisableSlotCmd64 (Xhc, Xhc->UsbDevContext[Index + 1].SlotId);\r | |
2224 | \r | |
2225 | if (EFI_ERROR (Status)) {\r | |
2226 | DEBUG ((EFI_D_ERROR, "XhcDisableSlotCmd: failed to disable child, ignore error\n"));\r | |
2227 | Xhc->UsbDevContext[Index + 1].SlotId = 0;\r | |
2228 | }\r | |
2229 | }\r | |
2230 | \r | |
2231 | //\r | |
2232 | // Construct the disable slot command\r | |
2233 | //\r | |
2234 | DEBUG ((EFI_D_INFO, "Disable device slot %d!\n", SlotId));\r | |
2235 | \r | |
2236 | ZeroMem (&CmdTrbDisSlot, sizeof (CmdTrbDisSlot));\r | |
2237 | CmdTrbDisSlot.CycleBit = 1;\r | |
2238 | CmdTrbDisSlot.Type = TRB_TYPE_DIS_SLOT;\r | |
2239 | CmdTrbDisSlot.SlotId = SlotId;\r | |
2240 | Status = XhcCmdTransfer (\r | |
2241 | Xhc,\r | |
2242 | (TRB_TEMPLATE *) (UINTN) &CmdTrbDisSlot,\r | |
2243 | XHC_GENERIC_TIMEOUT,\r | |
2244 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2245 | );\r | |
2246 | ASSERT_EFI_ERROR(Status);\r | |
2247 | //\r | |
2248 | // Free the slot's device context entry\r | |
2249 | //\r | |
2250 | Xhc->DCBAA[SlotId] = 0;\r | |
2251 | \r | |
2252 | //\r | |
2253 | // Free the slot related data structure\r | |
2254 | //\r | |
2255 | for (Index = 0; Index < 31; Index++) {\r | |
2256 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index] != NULL) {\r | |
2257 | RingSeg = ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index])->RingSeg0;\r | |
2258 | if (RingSeg != NULL) {\r | |
2259 | FreePages (RingSeg, EFI_SIZE_TO_PAGES (sizeof (TRB_TEMPLATE) * TR_RING_TRB_NUMBER));\r | |
2260 | }\r | |
2261 | FreePool (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Index]);\r | |
2262 | }\r | |
2263 | }\r | |
2264 | \r | |
2265 | for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r | |
2266 | if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] != NULL) {\r | |
2267 | FreePool (Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r | |
2268 | }\r | |
2269 | }\r | |
2270 | \r | |
2271 | if (Xhc->UsbDevContext[SlotId].InputContext != NULL) {\r | |
2272 | FreePages (Xhc->UsbDevContext[SlotId].InputContext, EFI_SIZE_TO_PAGES (sizeof (INPUT_CONTEXT_64)));\r | |
2273 | }\r | |
2274 | \r | |
2275 | if (Xhc->UsbDevContext[SlotId].OutputContext != NULL) {\r | |
2276 | FreePages (Xhc->UsbDevContext[SlotId].OutputContext, EFI_SIZE_TO_PAGES (sizeof (DEVICE_CONTEXT_64)));\r | |
2277 | }\r | |
2278 | //\r | |
2279 | // Doesn't zero the entry because XhcAsyncInterruptTransfer() may be invoked to remove the established\r | |
2280 | // asynchronous interrupt pipe after the device is disabled. It needs the device address mapping info to\r | |
2281 | // remove urb from XHCI's asynchronous transfer list.\r | |
2282 | //\r | |
2283 | Xhc->UsbDevContext[SlotId].Enabled = FALSE;\r | |
2284 | Xhc->UsbDevContext[SlotId].SlotId = 0;\r | |
2285 | \r | |
2286 | return Status;\r | |
2287 | }\r | |
2288 | \r | |
2289 | \r | |
2290 | /**\r | |
2291 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
2292 | \r | |
2293 | @param Xhc The XHCI Instance.\r | |
2294 | @param SlotId The slot id to be configured.\r | |
2295 | @param DeviceSpeed The device's speed.\r | |
2296 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
2297 | \r | |
2298 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
2299 | \r | |
2300 | **/\r | |
2301 | EFI_STATUS\r | |
2302 | EFIAPI\r | |
2303 | XhcSetConfigCmd (\r | |
2304 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2305 | IN UINT8 SlotId,\r | |
2306 | IN UINT8 DeviceSpeed,\r | |
2307 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r | |
2308 | )\r | |
2309 | {\r | |
2310 | EFI_STATUS Status;\r | |
2311 | \r | |
2312 | USB_INTERFACE_DESCRIPTOR *IfDesc;\r | |
2313 | USB_ENDPOINT_DESCRIPTOR *EpDesc;\r | |
2314 | UINT8 Index;\r | |
2315 | UINTN NumEp;\r | |
2316 | UINTN EpIndex;\r | |
2317 | UINT8 EpAddr;\r | |
2318 | UINT8 Direction;\r | |
2319 | UINT8 Dci;\r | |
2320 | UINT8 MaxDci;\r | |
2321 | UINT32 PhyAddr;\r | |
2322 | UINT8 Interval;\r | |
2323 | \r | |
2324 | TRANSFER_RING *EndpointTransferRing;\r | |
2325 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
2326 | INPUT_CONTEXT *InputContext;\r | |
2327 | DEVICE_CONTEXT *OutputContext;\r | |
2328 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
2329 | //\r | |
2330 | // 4.6.6 Configure Endpoint\r | |
2331 | //\r | |
2332 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
2333 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
2334 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r | |
2335 | CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT));\r | |
2336 | \r | |
2337 | ASSERT (ConfigDesc != NULL);\r | |
2338 | \r | |
2339 | MaxDci = 0;\r | |
2340 | \r | |
2341 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r | |
2342 | for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r | |
2343 | while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {\r | |
2344 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
2345 | }\r | |
2346 | \r | |
2347 | NumEp = IfDesc->NumEndpoints;\r | |
2348 | \r | |
2349 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r | |
2350 | for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r | |
2351 | while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r | |
2352 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2353 | }\r | |
2354 | \r | |
2355 | EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r | |
2356 | Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r | |
2357 | \r | |
2358 | Dci = XhcEndpointToDci (EpAddr, Direction);\r | |
2359 | ASSERT (Dci < 32);\r | |
2360 | if (Dci > MaxDci) {\r | |
2361 | MaxDci = Dci;\r | |
2362 | }\r | |
2363 | \r | |
2364 | InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r | |
2365 | InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r | |
2366 | \r | |
2367 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
2368 | //\r | |
2369 | // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r | |
2370 | //\r | |
2371 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2372 | } else {\r | |
2373 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2374 | }\r | |
2375 | \r | |
2376 | switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r | |
2377 | case USB_ENDPOINT_BULK:\r | |
2378 | if (Direction == EfiUsbDataIn) {\r | |
2379 | InputContext->EP[Dci-1].CErr = 3;\r | |
2380 | InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r | |
2381 | } else {\r | |
2382 | InputContext->EP[Dci-1].CErr = 3;\r | |
2383 | InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r | |
2384 | }\r | |
2385 | \r | |
2386 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2387 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r | |
2388 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2389 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2390 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
2391 | }\r | |
2392 | \r | |
2393 | break;\r | |
2394 | case USB_ENDPOINT_ISO:\r | |
2395 | if (Direction == EfiUsbDataIn) {\r | |
2396 | InputContext->EP[Dci-1].CErr = 0;\r | |
2397 | InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r | |
2398 | } else {\r | |
2399 | InputContext->EP[Dci-1].CErr = 0;\r | |
2400 | InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r | |
2401 | }\r | |
2402 | break;\r | |
2403 | case USB_ENDPOINT_INTERRUPT:\r | |
2404 | if (Direction == EfiUsbDataIn) {\r | |
2405 | InputContext->EP[Dci-1].CErr = 3;\r | |
2406 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r | |
2407 | } else {\r | |
2408 | InputContext->EP[Dci-1].CErr = 3;\r | |
2409 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r | |
2410 | }\r | |
2411 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2412 | InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r | |
2413 | //\r | |
2414 | // Get the bInterval from descriptor and init the the interval field of endpoint context\r | |
2415 | //\r | |
2416 | if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r | |
2417 | Interval = EpDesc->Interval;\r | |
2418 | //\r | |
2419 | // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.\r | |
2420 | //\r | |
2421 | InputContext->EP[Dci-1].Interval = 6;\r | |
2422 | } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r | |
2423 | Interval = EpDesc->Interval;\r | |
2424 | ASSERT (Interval >= 1 && Interval <= 16);\r | |
2425 | //\r | |
2426 | // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r | |
2427 | //\r | |
2428 | InputContext->EP[Dci-1].Interval = Interval - 1;\r | |
2429 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2430 | InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r | |
2431 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2432 | InputContext->EP[Dci-1].CErr = 3;\r | |
2433 | }\r | |
2434 | \r | |
2435 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r | |
2436 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2437 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2438 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
2439 | }\r | |
2440 | break;\r | |
2441 | \r | |
2442 | case USB_ENDPOINT_CONTROL:\r | |
2443 | default:\r | |
2444 | ASSERT (0);\r | |
2445 | break;\r | |
2446 | }\r | |
2447 | \r | |
2448 | PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r | |
2449 | PhyAddr &= ~(0x0F);\r | |
2450 | PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r | |
2451 | InputContext->EP[Dci-1].PtrLo = PhyAddr;\r | |
2452 | InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r | |
2453 | \r | |
2454 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2455 | }\r | |
2456 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
2457 | }\r | |
2458 | \r | |
2459 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
2460 | InputContext->Slot.ContextEntries = MaxDci;\r | |
2461 | //\r | |
2462 | // configure endpoint\r | |
2463 | //\r | |
2464 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
2465 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r | |
2466 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r | |
2467 | CmdTrbCfgEP.CycleBit = 1;\r | |
2468 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
2469 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
2470 | DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r | |
2471 | Status = XhcCmdTransfer (\r | |
2472 | Xhc,\r | |
2473 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r | |
2474 | XHC_GENERIC_TIMEOUT,\r | |
2475 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2476 | );\r | |
2477 | ASSERT_EFI_ERROR(Status);\r | |
2478 | \r | |
92870c98 | 2479 | return Status;\r |
2480 | }\r | |
2481 | \r | |
2482 | /**\r | |
2483 | Configure all the device endpoints through XHCI's Configure_Endpoint cmd.\r | |
2484 | \r | |
a9292c13 | 2485 | @param Xhc The XHCI Instance.\r |
92870c98 | 2486 | @param SlotId The slot id to be configured.\r |
2487 | @param DeviceSpeed The device's speed.\r | |
2488 | @param ConfigDesc The pointer to the usb device configuration descriptor.\r | |
2489 | \r | |
2490 | @retval EFI_SUCCESS Successfully configure all the device endpoints.\r | |
2491 | \r | |
2492 | **/\r | |
2493 | EFI_STATUS\r | |
2494 | EFIAPI\r | |
6b4483cd | 2495 | XhcSetConfigCmd64 (\r |
a9292c13 | 2496 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 2497 | IN UINT8 SlotId,\r |
a9292c13 | 2498 | IN UINT8 DeviceSpeed,\r |
92870c98 | 2499 | IN USB_CONFIG_DESCRIPTOR *ConfigDesc\r |
2500 | )\r | |
2501 | {\r | |
a9292c13 | 2502 | EFI_STATUS Status;\r |
2503 | \r | |
2504 | USB_INTERFACE_DESCRIPTOR *IfDesc;\r | |
2505 | USB_ENDPOINT_DESCRIPTOR *EpDesc;\r | |
2506 | UINT8 Index;\r | |
2507 | UINTN NumEp;\r | |
2508 | UINTN EpIndex;\r | |
2509 | UINT8 EpAddr;\r | |
2510 | UINT8 Direction;\r | |
2511 | UINT8 Dci;\r | |
2512 | UINT8 MaxDci;\r | |
2513 | UINT32 PhyAddr;\r | |
2514 | UINT8 Interval;\r | |
2515 | \r | |
2516 | TRANSFER_RING *EndpointTransferRing;\r | |
2517 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
6b4483cd | 2518 | INPUT_CONTEXT_64 *InputContext;\r |
2519 | DEVICE_CONTEXT_64 *OutputContext;\r | |
a9292c13 | 2520 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r |
92870c98 | 2521 | //\r |
2522 | // 4.6.6 Configure Endpoint\r | |
2523 | //\r | |
a9292c13 | 2524 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r |
2525 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
6b4483cd | 2526 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r |
2527 | CopyMem (&InputContext->Slot, &OutputContext->Slot, sizeof (SLOT_CONTEXT_64));\r | |
92870c98 | 2528 | \r |
2529 | ASSERT (ConfigDesc != NULL);\r | |
2530 | \r | |
2531 | MaxDci = 0;\r | |
2532 | \r | |
2533 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)(ConfigDesc + 1);\r | |
2534 | for (Index = 0; Index < ConfigDesc->NumInterfaces; Index++) {\r | |
2535 | while (IfDesc->DescriptorType != USB_DESC_TYPE_INTERFACE) {\r | |
2536 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
2537 | }\r | |
2538 | \r | |
2539 | NumEp = IfDesc->NumEndpoints;\r | |
2540 | \r | |
2541 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)(IfDesc + 1);\r | |
2542 | for (EpIndex = 0; EpIndex < NumEp; EpIndex++) {\r | |
2543 | while (EpDesc->DescriptorType != USB_DESC_TYPE_ENDPOINT) {\r | |
2544 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2545 | }\r | |
2546 | \r | |
ce9b5900 | 2547 | EpAddr = (UINT8)(EpDesc->EndpointAddress & 0x0F);\r |
92870c98 | 2548 | Direction = (UINT8)((EpDesc->EndpointAddress & 0x80) ? EfiUsbDataIn : EfiUsbDataOut);\r |
2549 | \r | |
2550 | Dci = XhcEndpointToDci (EpAddr, Direction);\r | |
a9292c13 | 2551 | ASSERT (Dci < 32);\r |
92870c98 | 2552 | if (Dci > MaxDci) {\r |
2553 | MaxDci = Dci;\r | |
2554 | }\r | |
2555 | \r | |
2556 | InputContext->InputControlContext.Dword2 |= (BIT0 << Dci);\r | |
2557 | InputContext->EP[Dci-1].MaxPacketSize = EpDesc->MaxPacketSize;\r | |
2558 | \r | |
2559 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
2560 | //\r | |
2561 | // 6.2.3.4, shall be set to the value defined in the bMaxBurst field of the SuperSpeed Endpoint Companion Descriptor.\r | |
2562 | //\r | |
2563 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2564 | } else {\r | |
2565 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2566 | }\r | |
2567 | \r | |
2568 | switch (EpDesc->Attributes & USB_ENDPOINT_TYPE_MASK) {\r | |
2569 | case USB_ENDPOINT_BULK:\r | |
2570 | if (Direction == EfiUsbDataIn) {\r | |
2571 | InputContext->EP[Dci-1].CErr = 3;\r | |
2572 | InputContext->EP[Dci-1].EPType = ED_BULK_IN;\r | |
2573 | } else {\r | |
2574 | InputContext->EP[Dci-1].CErr = 3;\r | |
2575 | InputContext->EP[Dci-1].EPType = ED_BULK_OUT;\r | |
2576 | }\r | |
2577 | \r | |
2578 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
a9292c13 | 2579 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r |
2580 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2581 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2582 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
92870c98 | 2583 | }\r |
2584 | \r | |
2585 | break;\r | |
2586 | case USB_ENDPOINT_ISO:\r | |
2587 | if (Direction == EfiUsbDataIn) {\r | |
2588 | InputContext->EP[Dci-1].CErr = 0;\r | |
2589 | InputContext->EP[Dci-1].EPType = ED_ISOCH_IN;\r | |
2590 | } else {\r | |
2591 | InputContext->EP[Dci-1].CErr = 0;\r | |
2592 | InputContext->EP[Dci-1].EPType = ED_ISOCH_OUT;\r | |
2593 | }\r | |
2594 | break;\r | |
2595 | case USB_ENDPOINT_INTERRUPT:\r | |
2596 | if (Direction == EfiUsbDataIn) {\r | |
2597 | InputContext->EP[Dci-1].CErr = 3;\r | |
2598 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_IN;\r | |
2599 | } else {\r | |
2600 | InputContext->EP[Dci-1].CErr = 3;\r | |
2601 | InputContext->EP[Dci-1].EPType = ED_INTERRUPT_OUT;\r | |
2602 | }\r | |
2603 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r | |
2604 | InputContext->EP[Dci-1].MaxESITPayload = EpDesc->MaxPacketSize;\r | |
2605 | //\r | |
2606 | // Get the bInterval from descriptor and init the the interval field of endpoint context\r | |
2607 | //\r | |
2608 | if ((DeviceSpeed == EFI_USB_SPEED_FULL) || (DeviceSpeed == EFI_USB_SPEED_LOW)) {\r | |
2609 | Interval = EpDesc->Interval;\r | |
2610 | //\r | |
a9292c13 | 2611 | // Hard code the interval to MAX first, need calculate through the bInterval field of Endpoint descriptor.\r |
92870c98 | 2612 | //\r |
2613 | InputContext->EP[Dci-1].Interval = 6;\r | |
a9292c13 | 2614 | } else if ((DeviceSpeed == EFI_USB_SPEED_HIGH) || (DeviceSpeed == EFI_USB_SPEED_SUPER)) {\r |
92870c98 | 2615 | Interval = EpDesc->Interval;\r |
a9292c13 | 2616 | ASSERT (Interval >= 1 && Interval <= 16);\r |
2617 | //\r | |
2618 | // Refer to XHCI 1.0 spec section 6.2.3.6, table 61\r | |
2619 | //\r | |
2620 | InputContext->EP[Dci-1].Interval = Interval - 1;\r | |
92870c98 | 2621 | InputContext->EP[Dci-1].AverageTRBLength = 0x1000;\r |
2622 | InputContext->EP[Dci-1].MaxESITPayload = 0x0002;\r | |
2623 | InputContext->EP[Dci-1].MaxBurstSize = 0x0;\r | |
2624 | InputContext->EP[Dci-1].CErr = 3;\r | |
2625 | }\r | |
2626 | \r | |
a9292c13 | 2627 | if (Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] == NULL) {\r |
2628 | EndpointTransferRing = AllocateZeroPool(sizeof (TRANSFER_RING));\r | |
2629 | Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1] = (VOID *) EndpointTransferRing;\r | |
2630 | CreateTransferRing(Xhc, TR_RING_TRB_NUMBER, (TRANSFER_RING *)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1]);\r | |
92870c98 | 2631 | }\r |
2632 | break;\r | |
2633 | \r | |
2634 | case USB_ENDPOINT_CONTROL:\r | |
2635 | default:\r | |
2636 | ASSERT (0);\r | |
2637 | break;\r | |
2638 | }\r | |
2639 | \r | |
a9292c13 | 2640 | PhyAddr = XHC_LOW_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r |
92870c98 | 2641 | PhyAddr &= ~(0x0F);\r |
a9292c13 | 2642 | PhyAddr |= ((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingPCS;\r |
92870c98 | 2643 | InputContext->EP[Dci-1].PtrLo = PhyAddr;\r |
a9292c13 | 2644 | InputContext->EP[Dci-1].PtrHi = XHC_HIGH_32BIT (((TRANSFER_RING *)(UINTN)Xhc->UsbDevContext[SlotId].EndpointTransferRing[Dci-1])->RingSeg0);\r |
92870c98 | 2645 | \r |
2646 | EpDesc = (USB_ENDPOINT_DESCRIPTOR *)((UINTN)EpDesc + EpDesc->Length);\r | |
2647 | }\r | |
2648 | IfDesc = (USB_INTERFACE_DESCRIPTOR *)((UINTN)IfDesc + IfDesc->Length);\r | |
2649 | }\r | |
2650 | \r | |
2651 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
2652 | InputContext->Slot.ContextEntries = MaxDci;\r | |
2653 | //\r | |
2654 | // configure endpoint\r | |
2655 | //\r | |
2656 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
2657 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r | |
2658 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r | |
2659 | CmdTrbCfgEP.CycleBit = 1;\r | |
2660 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
a9292c13 | 2661 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 2662 | DEBUG ((EFI_D_INFO, "Configure Endpoint\n"));\r |
2663 | Status = XhcCmdTransfer (\r | |
2664 | Xhc,\r | |
a9292c13 | 2665 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r |
92870c98 | 2666 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 2667 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 2668 | );\r |
2669 | ASSERT_EFI_ERROR(Status);\r | |
2670 | \r | |
2671 | return Status;\r | |
2672 | }\r | |
2673 | \r | |
6b4483cd | 2674 | \r |
92870c98 | 2675 | /**\r |
2676 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
2677 | \r | |
a9292c13 | 2678 | @param Xhc The XHCI Instance.\r |
92870c98 | 2679 | @param SlotId The slot id to be evaluated.\r |
2680 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
2681 | \r | |
2682 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
2683 | \r | |
2684 | **/\r | |
2685 | EFI_STATUS\r | |
2686 | EFIAPI\r | |
2687 | XhcEvaluateContext (\r | |
a9292c13 | 2688 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 2689 | IN UINT8 SlotId,\r |
2690 | IN UINT32 MaxPacketSize\r | |
2691 | )\r | |
2692 | {\r | |
a9292c13 | 2693 | EFI_STATUS Status;\r |
2694 | CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r | |
2695 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
2696 | INPUT_CONTEXT *InputContext;\r | |
92870c98 | 2697 | \r |
a9292c13 | 2698 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r |
92870c98 | 2699 | \r |
2700 | //\r | |
2701 | // 4.6.7 Evaluate Context\r | |
2702 | //\r | |
a9292c13 | 2703 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r |
92870c98 | 2704 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r |
2705 | \r | |
2706 | InputContext->InputControlContext.Dword2 |= BIT1;\r | |
2707 | InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r | |
2708 | \r | |
2709 | ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r | |
2710 | CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);\r | |
2711 | CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);\r | |
2712 | CmdTrbEvalu.CycleBit = 1;\r | |
2713 | CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r | |
a9292c13 | 2714 | CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 2715 | DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r |
2716 | Status = XhcCmdTransfer (\r | |
2717 | Xhc,\r | |
a9292c13 | 2718 | (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r |
92870c98 | 2719 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 2720 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 2721 | );\r |
2722 | ASSERT (!EFI_ERROR(Status));\r | |
2723 | \r | |
2724 | return Status;\r | |
2725 | }\r | |
2726 | \r | |
6b4483cd | 2727 | /**\r |
2728 | Evaluate the endpoint 0 context through XHCI's Evaluate_Context cmd.\r | |
2729 | \r | |
2730 | @param Xhc The XHCI Instance.\r | |
2731 | @param SlotId The slot id to be evaluated.\r | |
2732 | @param MaxPacketSize The max packet size supported by the device control transfer.\r | |
2733 | \r | |
2734 | @retval EFI_SUCCESS Successfully evaluate the device endpoint 0.\r | |
2735 | \r | |
2736 | **/\r | |
2737 | EFI_STATUS\r | |
2738 | EFIAPI\r | |
2739 | XhcEvaluateContext64 (\r | |
2740 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2741 | IN UINT8 SlotId,\r | |
2742 | IN UINT32 MaxPacketSize\r | |
2743 | )\r | |
2744 | {\r | |
2745 | EFI_STATUS Status;\r | |
2746 | CMD_TRB_EVALUATE_CONTEXT CmdTrbEvalu;\r | |
2747 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
2748 | INPUT_CONTEXT_64 *InputContext;\r | |
2749 | \r | |
2750 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r | |
2751 | \r | |
2752 | //\r | |
2753 | // 4.6.7 Evaluate Context\r | |
2754 | //\r | |
2755 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
2756 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r | |
2757 | \r | |
2758 | InputContext->InputControlContext.Dword2 |= BIT1;\r | |
2759 | InputContext->EP[0].MaxPacketSize = MaxPacketSize;\r | |
2760 | \r | |
2761 | ZeroMem (&CmdTrbEvalu, sizeof (CmdTrbEvalu));\r | |
2762 | CmdTrbEvalu.PtrLo = XHC_LOW_32BIT (InputContext);\r | |
2763 | CmdTrbEvalu.PtrHi = XHC_HIGH_32BIT (InputContext);\r | |
2764 | CmdTrbEvalu.CycleBit = 1;\r | |
2765 | CmdTrbEvalu.Type = TRB_TYPE_EVALU_CONTXT;\r | |
2766 | CmdTrbEvalu.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
2767 | DEBUG ((EFI_D_INFO, "Evaluate context\n"));\r | |
2768 | Status = XhcCmdTransfer (\r | |
2769 | Xhc,\r | |
2770 | (TRB_TEMPLATE *) (UINTN) &CmdTrbEvalu,\r | |
2771 | XHC_GENERIC_TIMEOUT,\r | |
2772 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2773 | );\r | |
2774 | ASSERT (!EFI_ERROR(Status));\r | |
2775 | \r | |
2776 | return Status;\r | |
2777 | }\r | |
2778 | \r | |
2779 | \r | |
92870c98 | 2780 | /**\r |
2781 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
2782 | \r | |
a9292c13 | 2783 | @param Xhc The XHCI Instance.\r |
92870c98 | 2784 | @param SlotId The slot id to be configured.\r |
2785 | @param PortNum The total number of downstream port supported by the hub.\r | |
2786 | @param TTT The TT think time of the hub device.\r | |
2787 | @param MTT The multi-TT of the hub device.\r | |
2788 | \r | |
2789 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
2790 | \r | |
2791 | **/\r | |
2792 | EFI_STATUS\r | |
2793 | XhcConfigHubContext (\r | |
a9292c13 | 2794 | IN USB_XHCI_INSTANCE *Xhc,\r |
92870c98 | 2795 | IN UINT8 SlotId,\r |
2796 | IN UINT8 PortNum,\r | |
2797 | IN UINT8 TTT,\r | |
2798 | IN UINT8 MTT\r | |
2799 | )\r | |
2800 | {\r | |
a9292c13 | 2801 | EFI_STATUS Status;\r |
92870c98 | 2802 | \r |
a9292c13 | 2803 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r |
2804 | INPUT_CONTEXT *InputContext;\r | |
2805 | DEVICE_CONTEXT *OutputContext;\r | |
2806 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
92870c98 | 2807 | \r |
a9292c13 | 2808 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r |
2809 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
2810 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
92870c98 | 2811 | \r |
2812 | //\r | |
2813 | // 4.6.7 Evaluate Context\r | |
2814 | //\r | |
2815 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT));\r | |
2816 | \r | |
2817 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
2818 | \r | |
2819 | //\r | |
2820 | // Copy the slot context from OutputContext to Input context\r | |
2821 | //\r | |
a9292c13 | 2822 | CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT));\r |
92870c98 | 2823 | InputContext->Slot.Hub = 1;\r |
2824 | InputContext->Slot.PortNum = PortNum;\r | |
2825 | InputContext->Slot.TTT = TTT;\r | |
2826 | InputContext->Slot.MTT = MTT;\r | |
2827 | \r | |
2828 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
2829 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r | |
2830 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r | |
2831 | CmdTrbCfgEP.CycleBit = 1;\r | |
2832 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
a9292c13 | 2833 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r |
92870c98 | 2834 | DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r |
2835 | Status = XhcCmdTransfer (\r | |
2836 | Xhc,\r | |
a9292c13 | 2837 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r |
92870c98 | 2838 | XHC_GENERIC_TIMEOUT,\r |
a9292c13 | 2839 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r |
92870c98 | 2840 | );\r |
2841 | ASSERT (!EFI_ERROR(Status));\r | |
2842 | \r | |
2843 | return Status;\r | |
2844 | }\r | |
2845 | \r | |
6b4483cd | 2846 | /**\r |
2847 | Evaluate the slot context for hub device through XHCI's Configure_Endpoint cmd.\r | |
2848 | \r | |
2849 | @param Xhc The XHCI Instance.\r | |
2850 | @param SlotId The slot id to be configured.\r | |
2851 | @param PortNum The total number of downstream port supported by the hub.\r | |
2852 | @param TTT The TT think time of the hub device.\r | |
2853 | @param MTT The multi-TT of the hub device.\r | |
2854 | \r | |
2855 | @retval EFI_SUCCESS Successfully configure the hub device's slot context.\r | |
2856 | \r | |
2857 | **/\r | |
2858 | EFI_STATUS\r | |
2859 | XhcConfigHubContext64 (\r | |
2860 | IN USB_XHCI_INSTANCE *Xhc,\r | |
2861 | IN UINT8 SlotId,\r | |
2862 | IN UINT8 PortNum,\r | |
2863 | IN UINT8 TTT,\r | |
2864 | IN UINT8 MTT\r | |
2865 | )\r | |
2866 | {\r | |
2867 | EFI_STATUS Status;\r | |
2868 | \r | |
2869 | EVT_TRB_COMMAND_COMPLETION *EvtTrb;\r | |
2870 | INPUT_CONTEXT_64 *InputContext;\r | |
2871 | DEVICE_CONTEXT_64 *OutputContext;\r | |
2872 | CMD_TRB_CONFIG_ENDPOINT CmdTrbCfgEP;\r | |
2873 | \r | |
2874 | ASSERT (Xhc->UsbDevContext[SlotId].SlotId != 0);\r | |
2875 | InputContext = Xhc->UsbDevContext[SlotId].InputContext;\r | |
2876 | OutputContext = Xhc->UsbDevContext[SlotId].OutputContext;\r | |
2877 | \r | |
2878 | //\r | |
2879 | // 4.6.7 Evaluate Context\r | |
2880 | //\r | |
2881 | ZeroMem (InputContext, sizeof (INPUT_CONTEXT_64));\r | |
2882 | \r | |
2883 | InputContext->InputControlContext.Dword2 |= BIT0;\r | |
2884 | \r | |
2885 | //\r | |
2886 | // Copy the slot context from OutputContext to Input context\r | |
2887 | //\r | |
2888 | CopyMem(&(InputContext->Slot), &(OutputContext->Slot), sizeof (SLOT_CONTEXT_64));\r | |
2889 | InputContext->Slot.Hub = 1;\r | |
2890 | InputContext->Slot.PortNum = PortNum;\r | |
2891 | InputContext->Slot.TTT = TTT;\r | |
2892 | InputContext->Slot.MTT = MTT;\r | |
2893 | \r | |
2894 | ZeroMem (&CmdTrbCfgEP, sizeof (CmdTrbCfgEP));\r | |
2895 | CmdTrbCfgEP.PtrLo = XHC_LOW_32BIT (InputContext);\r | |
2896 | CmdTrbCfgEP.PtrHi = XHC_HIGH_32BIT (InputContext);\r | |
2897 | CmdTrbCfgEP.CycleBit = 1;\r | |
2898 | CmdTrbCfgEP.Type = TRB_TYPE_CON_ENDPOINT;\r | |
2899 | CmdTrbCfgEP.SlotId = Xhc->UsbDevContext[SlotId].SlotId;\r | |
2900 | DEBUG ((EFI_D_INFO, "Configure Hub Slot Context\n"));\r | |
2901 | Status = XhcCmdTransfer (\r | |
2902 | Xhc,\r | |
2903 | (TRB_TEMPLATE *) (UINTN) &CmdTrbCfgEP,\r | |
2904 | XHC_GENERIC_TIMEOUT,\r | |
2905 | (TRB_TEMPLATE **) (UINTN) &EvtTrb\r | |
2906 | );\r | |
2907 | ASSERT (!EFI_ERROR(Status));\r | |
2908 | \r | |
2909 | return Status;\r | |
2910 | }\r | |
2911 | \r | |
2912 | \r |