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d987459f SZ |
1 | /** @file\r |
2 | PEIM to produce gPeiUsb2HostControllerPpiGuid based on gPeiUsbControllerPpiGuid\r | |
3 | which is used to enable recovery function from USB Drivers.\r | |
4 | \r | |
958a8181 | 5 | Copyright (c) 2014 - 2017, Intel Corporation. All rights reserved.<BR>\r |
d987459f SZ |
6 | \r |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions\r | |
9 | of the BSD License which accompanies this distribution. The\r | |
10 | full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
12 | \r | |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
15 | \r | |
16 | **/\r | |
17 | \r | |
18 | #include "XhcPeim.h"\r | |
19 | \r | |
20 | //\r | |
21 | // Two arrays used to translate the XHCI port state (change)\r | |
22 | // to the UEFI protocol's port state (change).\r | |
23 | //\r | |
24 | USB_PORT_STATE_MAP mUsbPortStateMap[] = {\r | |
25 | {XHC_PORTSC_CCS, USB_PORT_STAT_CONNECTION},\r | |
26 | {XHC_PORTSC_PED, USB_PORT_STAT_ENABLE},\r | |
27 | {XHC_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},\r | |
28 | {XHC_PORTSC_PP, USB_PORT_STAT_POWER},\r | |
29 | {XHC_PORTSC_RESET, USB_PORT_STAT_RESET}\r | |
30 | };\r | |
31 | \r | |
32 | USB_PORT_STATE_MAP mUsbPortChangeMap[] = {\r | |
33 | {XHC_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},\r | |
34 | {XHC_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},\r | |
35 | {XHC_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},\r | |
36 | {XHC_PORTSC_PRC, USB_PORT_STAT_C_RESET}\r | |
37 | };\r | |
38 | \r | |
39 | USB_CLEAR_PORT_MAP mUsbClearPortChangeMap[] = {\r | |
40 | {XHC_PORTSC_CSC, EfiUsbPortConnectChange},\r | |
41 | {XHC_PORTSC_PEC, EfiUsbPortEnableChange},\r | |
42 | {XHC_PORTSC_OCC, EfiUsbPortOverCurrentChange},\r | |
43 | {XHC_PORTSC_PRC, EfiUsbPortResetChange}\r | |
44 | };\r | |
45 | \r | |
46 | USB_PORT_STATE_MAP mUsbHubPortStateMap[] = {\r | |
47 | {XHC_HUB_PORTSC_CCS, USB_PORT_STAT_CONNECTION},\r | |
48 | {XHC_HUB_PORTSC_PED, USB_PORT_STAT_ENABLE},\r | |
49 | {XHC_HUB_PORTSC_OCA, USB_PORT_STAT_OVERCURRENT},\r | |
50 | {XHC_HUB_PORTSC_PP, USB_PORT_STAT_POWER},\r | |
51 | {XHC_HUB_PORTSC_RESET, USB_PORT_STAT_RESET}\r | |
52 | };\r | |
53 | \r | |
54 | USB_PORT_STATE_MAP mUsbHubPortChangeMap[] = {\r | |
55 | {XHC_HUB_PORTSC_CSC, USB_PORT_STAT_C_CONNECTION},\r | |
56 | {XHC_HUB_PORTSC_PEC, USB_PORT_STAT_C_ENABLE},\r | |
57 | {XHC_HUB_PORTSC_OCC, USB_PORT_STAT_C_OVERCURRENT},\r | |
58 | {XHC_HUB_PORTSC_PRC, USB_PORT_STAT_C_RESET}\r | |
59 | };\r | |
60 | \r | |
61 | USB_CLEAR_PORT_MAP mUsbHubClearPortChangeMap[] = {\r | |
62 | {XHC_HUB_PORTSC_CSC, EfiUsbPortConnectChange},\r | |
63 | {XHC_HUB_PORTSC_PEC, EfiUsbPortEnableChange},\r | |
64 | {XHC_HUB_PORTSC_OCC, EfiUsbPortOverCurrentChange},\r | |
65 | {XHC_HUB_PORTSC_PRC, EfiUsbPortResetChange},\r | |
66 | {XHC_HUB_PORTSC_BHRC, Usb3PortBHPortResetChange}\r | |
67 | };\r | |
68 | \r | |
69 | /**\r | |
70 | Read XHCI Operation register.\r | |
71 | \r | |
72 | @param Xhc The XHCI device.\r | |
73 | @param Offset The operation register offset.\r | |
74 | \r | |
75 | @retval the register content read.\r | |
76 | \r | |
77 | **/\r | |
78 | UINT32\r | |
79 | XhcPeiReadOpReg (\r | |
80 | IN PEI_XHC_DEV *Xhc,\r | |
81 | IN UINT32 Offset\r | |
82 | )\r | |
83 | {\r | |
84 | UINT32 Data;\r | |
85 | \r | |
86 | ASSERT (Xhc->CapLength != 0);\r | |
87 | \r | |
88 | Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset);\r | |
89 | return Data;\r | |
90 | }\r | |
91 | \r | |
92 | /**\r | |
93 | Write the data to the XHCI operation register.\r | |
94 | \r | |
95 | @param Xhc The XHCI device.\r | |
96 | @param Offset The operation register offset.\r | |
97 | @param Data The data to write.\r | |
98 | \r | |
99 | **/\r | |
100 | VOID\r | |
101 | XhcPeiWriteOpReg (\r | |
102 | IN PEI_XHC_DEV *Xhc,\r | |
103 | IN UINT32 Offset,\r | |
104 | IN UINT32 Data\r | |
105 | )\r | |
106 | {\r | |
107 | ASSERT (Xhc->CapLength != 0);\r | |
108 | \r | |
109 | MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->CapLength + Offset, Data);\r | |
110 | }\r | |
111 | \r | |
112 | /**\r | |
113 | Set one bit of the operational register while keeping other bits.\r | |
114 | \r | |
115 | @param Xhc The XHCI device.\r | |
116 | @param Offset The offset of the operational register.\r | |
117 | @param Bit The bit mask of the register to set.\r | |
118 | \r | |
119 | **/\r | |
120 | VOID\r | |
121 | XhcPeiSetOpRegBit (\r | |
122 | IN PEI_XHC_DEV *Xhc,\r | |
123 | IN UINT32 Offset,\r | |
124 | IN UINT32 Bit\r | |
125 | )\r | |
126 | {\r | |
127 | UINT32 Data;\r | |
128 | \r | |
129 | Data = XhcPeiReadOpReg (Xhc, Offset);\r | |
130 | Data |= Bit;\r | |
131 | XhcPeiWriteOpReg (Xhc, Offset, Data);\r | |
132 | }\r | |
133 | \r | |
134 | /**\r | |
135 | Clear one bit of the operational register while keeping other bits.\r | |
136 | \r | |
137 | @param Xhc The XHCI device.\r | |
138 | @param Offset The offset of the operational register.\r | |
139 | @param Bit The bit mask of the register to clear.\r | |
140 | \r | |
141 | **/\r | |
142 | VOID\r | |
143 | XhcPeiClearOpRegBit (\r | |
144 | IN PEI_XHC_DEV *Xhc,\r | |
145 | IN UINT32 Offset,\r | |
146 | IN UINT32 Bit\r | |
147 | )\r | |
148 | {\r | |
149 | UINT32 Data;\r | |
150 | \r | |
151 | Data = XhcPeiReadOpReg (Xhc, Offset);\r | |
152 | Data &= ~Bit;\r | |
153 | XhcPeiWriteOpReg (Xhc, Offset, Data);\r | |
154 | }\r | |
155 | \r | |
156 | /**\r | |
157 | Wait the operation register's bit as specified by Bit\r | |
158 | to become set (or clear).\r | |
159 | \r | |
160 | @param Xhc The XHCI device.\r | |
161 | @param Offset The offset of the operational register.\r | |
162 | @param Bit The bit mask of the register to wait for.\r | |
163 | @param WaitToSet Wait the bit to set or clear.\r | |
26cd2d6d | 164 | @param Timeout The time to wait before abort (in millisecond, ms).\r |
d987459f SZ |
165 | \r |
166 | @retval EFI_SUCCESS The bit successfully changed by host controller.\r | |
167 | @retval EFI_TIMEOUT The time out occurred.\r | |
168 | \r | |
169 | **/\r | |
170 | EFI_STATUS\r | |
171 | XhcPeiWaitOpRegBit (\r | |
172 | IN PEI_XHC_DEV *Xhc,\r | |
173 | IN UINT32 Offset,\r | |
174 | IN UINT32 Bit,\r | |
175 | IN BOOLEAN WaitToSet,\r | |
176 | IN UINT32 Timeout\r | |
177 | )\r | |
178 | {\r | |
26cd2d6d | 179 | UINT64 Index;\r |
d987459f | 180 | \r |
26cd2d6d | 181 | for (Index = 0; Index < Timeout * XHC_1_MILLISECOND; Index++) {\r |
d987459f SZ |
182 | if (XHC_REG_BIT_IS_SET (Xhc, Offset, Bit) == WaitToSet) {\r |
183 | return EFI_SUCCESS;\r | |
184 | }\r | |
185 | \r | |
26cd2d6d | 186 | MicroSecondDelay (XHC_1_MICROSECOND);\r |
d987459f SZ |
187 | }\r |
188 | \r | |
189 | return EFI_TIMEOUT;\r | |
190 | }\r | |
191 | \r | |
192 | /**\r | |
193 | Read XHCI capability register.\r | |
194 | \r | |
195 | @param Xhc The XHCI device.\r | |
196 | @param Offset Capability register address.\r | |
197 | \r | |
198 | @retval the register content read.\r | |
199 | \r | |
200 | **/\r | |
201 | UINT32\r | |
202 | XhcPeiReadCapRegister (\r | |
203 | IN PEI_XHC_DEV *Xhc,\r | |
204 | IN UINT32 Offset\r | |
205 | )\r | |
206 | {\r | |
207 | UINT32 Data;\r | |
208 | \r | |
209 | Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Offset);\r | |
210 | \r | |
211 | return Data;\r | |
212 | }\r | |
213 | \r | |
214 | /**\r | |
215 | Read XHCI door bell register.\r | |
216 | \r | |
217 | @param Xhc The XHCI device.\r | |
218 | @param Offset The offset of the door bell register.\r | |
219 | \r | |
220 | @return The register content read\r | |
221 | \r | |
222 | **/\r | |
223 | UINT32\r | |
224 | XhcPeiReadDoorBellReg (\r | |
225 | IN PEI_XHC_DEV *Xhc,\r | |
226 | IN UINT32 Offset\r | |
227 | )\r | |
228 | {\r | |
229 | UINT32 Data;\r | |
230 | \r | |
231 | ASSERT (Xhc->DBOff != 0);\r | |
232 | \r | |
233 | Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset);\r | |
234 | \r | |
235 | return Data;\r | |
236 | }\r | |
237 | \r | |
238 | /**\r | |
239 | Write the data to the XHCI door bell register.\r | |
240 | \r | |
241 | @param Xhc The XHCI device.\r | |
242 | @param Offset The offset of the door bell register.\r | |
243 | @param Data The data to write.\r | |
244 | \r | |
245 | **/\r | |
246 | VOID\r | |
247 | XhcPeiWriteDoorBellReg (\r | |
248 | IN PEI_XHC_DEV *Xhc,\r | |
249 | IN UINT32 Offset,\r | |
250 | IN UINT32 Data\r | |
251 | )\r | |
252 | {\r | |
253 | ASSERT (Xhc->DBOff != 0);\r | |
254 | \r | |
255 | MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->DBOff + Offset, Data);\r | |
256 | }\r | |
257 | \r | |
258 | /**\r | |
259 | Read XHCI runtime register.\r | |
260 | \r | |
261 | @param Xhc The XHCI device.\r | |
262 | @param Offset The offset of the runtime register.\r | |
263 | \r | |
264 | @return The register content read\r | |
265 | \r | |
266 | **/\r | |
267 | UINT32\r | |
268 | XhcPeiReadRuntimeReg (\r | |
269 | IN PEI_XHC_DEV *Xhc,\r | |
270 | IN UINT32 Offset\r | |
271 | )\r | |
272 | {\r | |
273 | UINT32 Data;\r | |
274 | \r | |
275 | ASSERT (Xhc->RTSOff != 0);\r | |
276 | \r | |
277 | Data = MmioRead32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset);\r | |
278 | \r | |
279 | return Data;\r | |
280 | }\r | |
281 | \r | |
282 | /**\r | |
283 | Write the data to the XHCI runtime register.\r | |
284 | \r | |
285 | @param Xhc The XHCI device.\r | |
286 | @param Offset The offset of the runtime register.\r | |
287 | @param Data The data to write.\r | |
288 | \r | |
289 | **/\r | |
290 | VOID\r | |
291 | XhcPeiWriteRuntimeReg (\r | |
292 | IN PEI_XHC_DEV *Xhc,\r | |
293 | IN UINT32 Offset,\r | |
294 | IN UINT32 Data\r | |
295 | )\r | |
296 | {\r | |
297 | ASSERT (Xhc->RTSOff != 0);\r | |
298 | \r | |
299 | MmioWrite32 (Xhc->UsbHostControllerBaseAddress + Xhc->RTSOff + Offset, Data);\r | |
300 | }\r | |
301 | \r | |
302 | /**\r | |
303 | Set one bit of the runtime register while keeping other bits.\r | |
304 | \r | |
305 | @param Xhc The XHCI device.\r | |
306 | @param Offset The offset of the runtime register.\r | |
307 | @param Bit The bit mask of the register to set.\r | |
308 | \r | |
309 | **/\r | |
310 | VOID\r | |
311 | XhcPeiSetRuntimeRegBit (\r | |
312 | IN PEI_XHC_DEV *Xhc,\r | |
313 | IN UINT32 Offset,\r | |
314 | IN UINT32 Bit\r | |
315 | )\r | |
316 | {\r | |
317 | UINT32 Data;\r | |
318 | \r | |
319 | Data = XhcPeiReadRuntimeReg (Xhc, Offset);\r | |
320 | Data |= Bit;\r | |
321 | XhcPeiWriteRuntimeReg (Xhc, Offset, Data);\r | |
322 | }\r | |
323 | \r | |
324 | /**\r | |
325 | Clear one bit of the runtime register while keeping other bits.\r | |
326 | \r | |
327 | @param Xhc The XHCI device.\r | |
328 | @param Offset The offset of the runtime register.\r | |
329 | @param Bit The bit mask of the register to set.\r | |
330 | \r | |
331 | **/\r | |
332 | VOID\r | |
333 | XhcPeiClearRuntimeRegBit (\r | |
334 | IN PEI_XHC_DEV *Xhc,\r | |
335 | IN UINT32 Offset,\r | |
336 | IN UINT32 Bit\r | |
337 | )\r | |
338 | {\r | |
339 | UINT32 Data;\r | |
340 | \r | |
341 | Data = XhcPeiReadRuntimeReg (Xhc, Offset);\r | |
342 | Data &= ~Bit;\r | |
343 | XhcPeiWriteRuntimeReg (Xhc, Offset, Data);\r | |
344 | }\r | |
345 | \r | |
346 | /**\r | |
347 | Check whether Xhc is halted.\r | |
348 | \r | |
349 | @param Xhc The XHCI device.\r | |
350 | \r | |
351 | @retval TRUE The controller is halted.\r | |
352 | @retval FALSE The controller isn't halted.\r | |
353 | \r | |
354 | **/\r | |
355 | BOOLEAN\r | |
356 | XhcPeiIsHalt (\r | |
357 | IN PEI_XHC_DEV *Xhc\r | |
358 | )\r | |
359 | {\r | |
360 | return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT);\r | |
361 | }\r | |
362 | \r | |
363 | /**\r | |
364 | Check whether system error occurred.\r | |
365 | \r | |
366 | @param Xhc The XHCI device.\r | |
367 | \r | |
368 | @retval TRUE System error happened.\r | |
369 | @retval FALSE No system error.\r | |
370 | \r | |
371 | **/\r | |
372 | BOOLEAN\r | |
373 | XhcPeiIsSysError (\r | |
374 | IN PEI_XHC_DEV *Xhc\r | |
375 | )\r | |
376 | {\r | |
377 | return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);\r | |
378 | }\r | |
379 | \r | |
380 | /**\r | |
381 | Reset the host controller.\r | |
382 | \r | |
383 | @param Xhc The XHCI device.\r | |
26cd2d6d | 384 | @param Timeout Time to wait before abort (in millisecond, ms).\r |
d987459f SZ |
385 | \r |
386 | @retval EFI_TIMEOUT The transfer failed due to time out.\r | |
387 | @retval Others Failed to reset the host.\r | |
388 | \r | |
389 | **/\r | |
390 | EFI_STATUS\r | |
391 | XhcPeiResetHC (\r | |
392 | IN PEI_XHC_DEV *Xhc,\r | |
393 | IN UINT32 Timeout\r | |
394 | )\r | |
395 | {\r | |
396 | EFI_STATUS Status;\r | |
397 | \r | |
398 | //\r | |
399 | // Host can only be reset when it is halt. If not so, halt it\r | |
400 | //\r | |
401 | if (!XhcPeiIsHalt (Xhc)) {\r | |
402 | Status = XhcPeiHaltHC (Xhc, Timeout);\r | |
403 | \r | |
404 | if (EFI_ERROR (Status)) {\r | |
405 | goto ON_EXIT;\r | |
406 | }\r | |
407 | }\r | |
408 | \r | |
409 | XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);\r | |
1f87985a FT |
410 | //\r |
411 | // Some XHCI host controllers require to have extra 1ms delay before accessing any MMIO register during reset.\r | |
412 | // Otherwise there may have the timeout case happened.\r | |
413 | // The below is a workaround to solve such problem.\r | |
414 | //\r | |
415 | MicroSecondDelay (1000);\r | |
d987459f SZ |
416 | Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);\r |
417 | ON_EXIT:\r | |
418 | DEBUG ((EFI_D_INFO, "XhcPeiResetHC: %r\n", Status));\r | |
419 | return Status;\r | |
420 | }\r | |
421 | \r | |
422 | /**\r | |
423 | Halt the host controller.\r | |
424 | \r | |
425 | @param Xhc The XHCI device.\r | |
426 | @param Timeout Time to wait before abort.\r | |
427 | \r | |
428 | @retval EFI_TIMEOUT Failed to halt the controller before Timeout.\r | |
429 | @retval EFI_SUCCESS The XHCI is halt.\r | |
430 | \r | |
431 | **/\r | |
432 | EFI_STATUS\r | |
433 | XhcPeiHaltHC (\r | |
434 | IN PEI_XHC_DEV *Xhc,\r | |
435 | IN UINT32 Timeout\r | |
436 | )\r | |
437 | {\r | |
438 | EFI_STATUS Status;\r | |
439 | \r | |
440 | XhcPeiClearOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r | |
441 | Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, TRUE, Timeout);\r | |
442 | DEBUG ((EFI_D_INFO, "XhcPeiHaltHC: %r\n", Status));\r | |
443 | return Status;\r | |
444 | }\r | |
445 | \r | |
446 | /**\r | |
447 | Set the XHCI to run.\r | |
448 | \r | |
449 | @param Xhc The XHCI device.\r | |
450 | @param Timeout Time to wait before abort.\r | |
451 | \r | |
452 | @retval EFI_SUCCESS The XHCI is running.\r | |
453 | @retval Others Failed to set the XHCI to run.\r | |
454 | \r | |
455 | **/\r | |
456 | EFI_STATUS\r | |
457 | XhcPeiRunHC (\r | |
458 | IN PEI_XHC_DEV *Xhc,\r | |
459 | IN UINT32 Timeout\r | |
460 | )\r | |
461 | {\r | |
462 | EFI_STATUS Status;\r | |
463 | \r | |
464 | XhcPeiSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RUN);\r | |
465 | Status = XhcPeiWaitOpRegBit (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HALT, FALSE, Timeout);\r | |
466 | DEBUG ((EFI_D_INFO, "XhcPeiRunHC: %r\n", Status));\r | |
467 | return Status;\r | |
468 | }\r | |
469 | \r | |
470 | /**\r | |
471 | Submits control transfer to a target USB device.\r | |
472 | \r | |
473 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
474 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
475 | @param DeviceAddress The target device address.\r | |
476 | @param DeviceSpeed Target device speed.\r | |
477 | @param MaximumPacketLength Maximum packet size the default control transfer\r | |
478 | endpoint is capable of sending or receiving.\r | |
479 | @param Request USB device request to send.\r | |
480 | @param TransferDirection Specifies the data direction for the data stage.\r | |
481 | @param Data Data buffer to be transmitted or received from USB device.\r | |
482 | @param DataLength The size (in bytes) of the data buffer.\r | |
483 | @param TimeOut Indicates the maximum timeout, in millisecond.\r | |
484 | If Timeout is 0, then the caller must wait for the function\r | |
485 | to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.\r | |
486 | @param Translator Transaction translator to be used by this device.\r | |
487 | @param TransferResult Return the result of this control transfer.\r | |
488 | \r | |
489 | @retval EFI_SUCCESS Transfer was completed successfully.\r | |
490 | @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resources.\r | |
491 | @retval EFI_INVALID_PARAMETER Some parameters are invalid.\r | |
492 | @retval EFI_TIMEOUT Transfer failed due to timeout.\r | |
493 | @retval EFI_DEVICE_ERROR Transfer failed due to host controller or device error.\r | |
494 | \r | |
495 | **/\r | |
496 | EFI_STATUS\r | |
497 | EFIAPI\r | |
498 | XhcPeiControlTransfer (\r | |
499 | IN EFI_PEI_SERVICES **PeiServices,\r | |
500 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
501 | IN UINT8 DeviceAddress,\r | |
502 | IN UINT8 DeviceSpeed,\r | |
503 | IN UINTN MaximumPacketLength,\r | |
504 | IN EFI_USB_DEVICE_REQUEST *Request,\r | |
505 | IN EFI_USB_DATA_DIRECTION TransferDirection,\r | |
506 | IN OUT VOID *Data,\r | |
507 | IN OUT UINTN *DataLength,\r | |
508 | IN UINTN TimeOut,\r | |
509 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
510 | OUT UINT32 *TransferResult\r | |
511 | )\r | |
512 | {\r | |
513 | PEI_XHC_DEV *Xhc;\r | |
514 | URB *Urb;\r | |
515 | UINT8 Endpoint;\r | |
516 | UINT8 Index;\r | |
517 | UINT8 DescriptorType;\r | |
518 | UINT8 SlotId;\r | |
519 | UINT8 TTT;\r | |
520 | UINT8 MTT;\r | |
521 | UINT32 MaxPacket0;\r | |
522 | EFI_USB_HUB_DESCRIPTOR *HubDesc;\r | |
523 | EFI_STATUS Status;\r | |
524 | EFI_STATUS RecoveryStatus;\r | |
525 | UINTN MapSize;\r | |
526 | EFI_USB_PORT_STATUS PortStatus;\r | |
527 | UINT32 State;\r | |
528 | EFI_USB_DEVICE_REQUEST ClearPortRequest;\r | |
529 | UINTN Len;\r | |
530 | \r | |
531 | //\r | |
532 | // Validate parameters\r | |
533 | //\r | |
534 | if ((Request == NULL) || (TransferResult == NULL)) {\r | |
535 | return EFI_INVALID_PARAMETER;\r | |
536 | }\r | |
537 | \r | |
538 | if ((TransferDirection != EfiUsbDataIn) &&\r | |
539 | (TransferDirection != EfiUsbDataOut) &&\r | |
540 | (TransferDirection != EfiUsbNoData)) {\r | |
541 | return EFI_INVALID_PARAMETER;\r | |
542 | }\r | |
543 | \r | |
544 | if ((TransferDirection == EfiUsbNoData) &&\r | |
545 | ((Data != NULL) || (*DataLength != 0))) {\r | |
546 | return EFI_INVALID_PARAMETER;\r | |
547 | }\r | |
548 | \r | |
549 | if ((TransferDirection != EfiUsbNoData) &&\r | |
550 | ((Data == NULL) || (*DataLength == 0))) {\r | |
551 | return EFI_INVALID_PARAMETER;\r | |
552 | }\r | |
553 | \r | |
554 | if ((MaximumPacketLength != 8) && (MaximumPacketLength != 16) &&\r | |
555 | (MaximumPacketLength != 32) && (MaximumPacketLength != 64) &&\r | |
556 | (MaximumPacketLength != 512)\r | |
557 | ) {\r | |
558 | return EFI_INVALID_PARAMETER;\r | |
559 | }\r | |
560 | \r | |
561 | if ((DeviceSpeed == EFI_USB_SPEED_LOW) && (MaximumPacketLength != 8)) {\r | |
562 | return EFI_INVALID_PARAMETER;\r | |
563 | }\r | |
564 | \r | |
565 | if ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength != 512)) {\r | |
566 | return EFI_INVALID_PARAMETER;\r | |
567 | }\r | |
568 | \r | |
569 | Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r | |
570 | \r | |
571 | Status = EFI_DEVICE_ERROR;\r | |
572 | *TransferResult = EFI_USB_ERR_SYSTEM;\r | |
573 | Len = 0;\r | |
574 | \r | |
575 | if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {\r | |
576 | DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: HC is halted or has system error\n"));\r | |
577 | goto ON_EXIT;\r | |
578 | }\r | |
579 | \r | |
580 | //\r | |
581 | // Check if the device is still enabled before every transaction.\r | |
582 | //\r | |
583 | SlotId = XhcPeiBusDevAddrToSlotId (Xhc, DeviceAddress);\r | |
584 | if (SlotId == 0) {\r | |
585 | goto ON_EXIT;\r | |
586 | }\r | |
587 | \r | |
588 | //\r | |
589 | // Hook the Set_Address request from UsbBus.\r | |
590 | // According to XHCI 1.0 spec, the Set_Address request is replaced by XHCI's Address_Device cmd.\r | |
591 | //\r | |
592 | if ((Request->Request == USB_REQ_SET_ADDRESS) &&\r | |
593 | (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {\r | |
594 | //\r | |
595 | // Reset the BusDevAddr field of all disabled entries in UsbDevContext array firstly.\r | |
596 | // This way is used to clean the history to avoid using wrong device address afterwards.\r | |
597 | //\r | |
598 | for (Index = 0; Index < 255; Index++) {\r | |
599 | if (!Xhc->UsbDevContext[Index + 1].Enabled &&\r | |
600 | (Xhc->UsbDevContext[Index + 1].SlotId == 0) &&\r | |
601 | (Xhc->UsbDevContext[Index + 1].BusDevAddr == (UINT8) Request->Value)) {\r | |
602 | Xhc->UsbDevContext[Index + 1].BusDevAddr = 0;\r | |
603 | }\r | |
604 | }\r | |
605 | \r | |
606 | if (Xhc->UsbDevContext[SlotId].XhciDevAddr == 0) {\r | |
607 | goto ON_EXIT;\r | |
608 | }\r | |
609 | //\r | |
610 | // The actual device address has been assigned by XHCI during initializing the device slot.\r | |
611 | // So we just need establish the mapping relationship between the device address requested from UsbBus\r | |
612 | // and the actual device address assigned by XHCI. The following invocations through EFI_USB2_HC_PROTOCOL interface\r | |
613 | // can find out the actual device address by it.\r | |
614 | //\r | |
615 | Xhc->UsbDevContext[SlotId].BusDevAddr = (UINT8) Request->Value;\r | |
616 | Status = EFI_SUCCESS;\r | |
617 | goto ON_EXIT;\r | |
618 | }\r | |
619 | \r | |
620 | //\r | |
621 | // Create a new URB, insert it into the asynchronous\r | |
622 | // schedule list, then poll the execution status.\r | |
623 | // Note that we encode the direction in address although default control\r | |
624 | // endpoint is bidirectional. XhcPeiCreateUrb expects this\r | |
625 | // combination of Ep addr and its direction.\r | |
626 | //\r | |
627 | Endpoint = (UINT8) (0 | ((TransferDirection == EfiUsbDataIn) ? 0x80 : 0));\r | |
628 | Urb = XhcPeiCreateUrb (\r | |
629 | Xhc,\r | |
630 | DeviceAddress,\r | |
631 | Endpoint,\r | |
632 | DeviceSpeed,\r | |
633 | MaximumPacketLength,\r | |
634 | XHC_CTRL_TRANSFER,\r | |
635 | Request,\r | |
636 | Data,\r | |
637 | *DataLength,\r | |
638 | NULL,\r | |
639 | NULL\r | |
640 | );\r | |
641 | \r | |
642 | if (Urb == NULL) {\r | |
643 | DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: failed to create URB"));\r | |
644 | Status = EFI_OUT_OF_RESOURCES;\r | |
645 | goto ON_EXIT;\r | |
646 | }\r | |
647 | \r | |
648 | Status = XhcPeiExecTransfer (Xhc, FALSE, Urb, TimeOut);\r | |
649 | \r | |
650 | //\r | |
651 | // Get the status from URB. The result is updated in XhcPeiCheckUrbResult\r | |
652 | // which is called by XhcPeiExecTransfer\r | |
653 | //\r | |
654 | *TransferResult = Urb->Result;\r | |
655 | *DataLength = Urb->Completed;\r | |
656 | \r | |
12e6c738 FT |
657 | if (Status == EFI_TIMEOUT) {\r |
658 | //\r | |
659 | // The transfer timed out. Abort the transfer by dequeueing of the TD.\r | |
660 | //\r | |
661 | RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);\r | |
662 | if (EFI_ERROR(RecoveryStatus)) {\r | |
663 | DEBUG((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));\r | |
d987459f | 664 | }\r |
d987459f SZ |
665 | goto FREE_URB;\r |
666 | } else {\r | |
12e6c738 FT |
667 | if (*TransferResult == EFI_USB_NOERROR) {\r |
668 | Status = EFI_SUCCESS;\r | |
958a8181 | 669 | } else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {\r |
12e6c738 FT |
670 | RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);\r |
671 | if (EFI_ERROR (RecoveryStatus)) {\r | |
672 | DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));\r | |
673 | }\r | |
674 | Status = EFI_DEVICE_ERROR;\r | |
675 | goto FREE_URB;\r | |
676 | } else {\r | |
677 | goto FREE_URB;\r | |
678 | }\r | |
d987459f SZ |
679 | }\r |
680 | \r | |
681 | //\r | |
682 | // Hook Get_Descriptor request from UsbBus as we need evaluate context and configure endpoint.\r | |
683 | // Hook Get_Status request form UsbBus as we need trace device attach/detach event happened at hub.\r | |
684 | // Hook Set_Config request from UsbBus as we need configure device endpoint.\r | |
685 | //\r | |
686 | if ((Request->Request == USB_REQ_GET_DESCRIPTOR) &&\r | |
687 | ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE)) ||\r | |
688 | ((Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_DEVICE))))) {\r | |
689 | DescriptorType = (UINT8) (Request->Value >> 8);\r | |
690 | if ((DescriptorType == USB_DESC_TYPE_DEVICE) && ((*DataLength == sizeof (EFI_USB_DEVICE_DESCRIPTOR)) || ((DeviceSpeed == EFI_USB_SPEED_FULL) && (*DataLength == 8)))) {\r | |
691 | ASSERT (Data != NULL);\r | |
692 | //\r | |
693 | // Store a copy of device scriptor as hub device need this info to configure endpoint.\r | |
694 | //\r | |
695 | CopyMem (&Xhc->UsbDevContext[SlotId].DevDesc, Data, *DataLength);\r | |
b9953b65 | 696 | if (Xhc->UsbDevContext[SlotId].DevDesc.BcdUSB >= 0x0300) {\r |
d987459f SZ |
697 | //\r |
698 | // If it's a usb3.0 device, then its max packet size is a 2^n.\r | |
699 | //\r | |
700 | MaxPacket0 = 1 << Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r | |
701 | } else {\r | |
702 | MaxPacket0 = Xhc->UsbDevContext[SlotId].DevDesc.MaxPacketSize0;\r | |
703 | }\r | |
704 | Xhc->UsbDevContext[SlotId].ConfDesc = AllocateZeroPool (Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations * sizeof (EFI_USB_CONFIG_DESCRIPTOR *));\r | |
705 | if (Xhc->UsbDevContext[SlotId].ConfDesc == NULL) {\r | |
706 | Status = EFI_OUT_OF_RESOURCES;\r | |
707 | goto FREE_URB;\r | |
708 | }\r | |
709 | if (Xhc->HcCParams.Data.Csz == 0) {\r | |
710 | Status = XhcPeiEvaluateContext (Xhc, SlotId, MaxPacket0);\r | |
711 | } else {\r | |
712 | Status = XhcPeiEvaluateContext64 (Xhc, SlotId, MaxPacket0);\r | |
713 | }\r | |
714 | } else if (DescriptorType == USB_DESC_TYPE_CONFIG) {\r | |
715 | ASSERT (Data != NULL);\r | |
716 | if (*DataLength == ((UINT16 *) Data)[1]) {\r | |
717 | //\r | |
718 | // Get configuration value from request, store the configuration descriptor for Configure_Endpoint cmd.\r | |
719 | //\r | |
720 | Index = (UINT8) Request->Value;\r | |
721 | ASSERT (Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations);\r | |
722 | Xhc->UsbDevContext[SlotId].ConfDesc[Index] = AllocateZeroPool (*DataLength);\r | |
723 | if (Xhc->UsbDevContext[SlotId].ConfDesc[Index] == NULL) {\r | |
724 | Status = EFI_OUT_OF_RESOURCES;\r | |
725 | goto FREE_URB;\r | |
726 | }\r | |
727 | CopyMem (Xhc->UsbDevContext[SlotId].ConfDesc[Index], Data, *DataLength);\r | |
728 | }\r | |
729 | } else if (((DescriptorType == USB_DESC_TYPE_HUB) ||\r | |
730 | (DescriptorType == USB_DESC_TYPE_HUB_SUPER_SPEED)) && (*DataLength > 2)) {\r | |
731 | ASSERT (Data != NULL);\r | |
732 | HubDesc = (EFI_USB_HUB_DESCRIPTOR *) Data;\r | |
733 | ASSERT (HubDesc->NumPorts <= 15);\r | |
734 | //\r | |
735 | // The bit 5,6 of HubCharacter field of Hub Descriptor is TTT.\r | |
736 | //\r | |
737 | TTT = (UINT8) ((HubDesc->HubCharacter & (BIT5 | BIT6)) >> 5);\r | |
738 | if (Xhc->UsbDevContext[SlotId].DevDesc.DeviceProtocol == 2) {\r | |
739 | //\r | |
740 | // Don't support multi-TT feature for super speed hub now.\r | |
741 | //\r | |
742 | MTT = 0;\r | |
743 | DEBUG ((EFI_D_ERROR, "XHCI: Don't support multi-TT feature for Hub now. (force to disable MTT)\n"));\r | |
744 | } else {\r | |
745 | MTT = 0;\r | |
746 | }\r | |
747 | \r | |
748 | if (Xhc->HcCParams.Data.Csz == 0) {\r | |
749 | Status = XhcPeiConfigHubContext (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);\r | |
750 | } else {\r | |
751 | Status = XhcPeiConfigHubContext64 (Xhc, SlotId, HubDesc->NumPorts, TTT, MTT);\r | |
752 | }\r | |
753 | }\r | |
754 | } else if ((Request->Request == USB_REQ_SET_CONFIG) &&\r | |
755 | (Request->RequestType == USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_STANDARD, USB_TARGET_DEVICE))) {\r | |
756 | //\r | |
757 | // Hook Set_Config request from UsbBus as we need configure device endpoint.\r | |
758 | //\r | |
759 | for (Index = 0; Index < Xhc->UsbDevContext[SlotId].DevDesc.NumConfigurations; Index++) {\r | |
760 | if (Xhc->UsbDevContext[SlotId].ConfDesc[Index]->ConfigurationValue == (UINT8)Request->Value) {\r | |
761 | if (Xhc->HcCParams.Data.Csz == 0) {\r | |
762 | Status = XhcPeiSetConfigCmd (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r | |
763 | } else {\r | |
764 | Status = XhcPeiSetConfigCmd64 (Xhc, SlotId, DeviceSpeed, Xhc->UsbDevContext[SlotId].ConfDesc[Index]);\r | |
765 | }\r | |
766 | break;\r | |
767 | }\r | |
768 | }\r | |
769 | } else if ((Request->Request == USB_REQ_GET_STATUS) &&\r | |
770 | (Request->RequestType == USB_REQUEST_TYPE (EfiUsbDataIn, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER))) {\r | |
771 | ASSERT (Data != NULL);\r | |
772 | //\r | |
773 | // Hook Get_Status request from UsbBus to keep track of the port status change.\r | |
774 | //\r | |
775 | State = *(UINT32 *) Data;\r | |
776 | PortStatus.PortStatus = 0;\r | |
777 | PortStatus.PortChangeStatus = 0;\r | |
778 | \r | |
779 | if (DeviceSpeed == EFI_USB_SPEED_SUPER) {\r | |
780 | //\r | |
781 | // For super speed hub, its bit10~12 presents the attached device speed.\r | |
782 | //\r | |
783 | if ((State & XHC_PORTSC_PS) >> 10 == 0) {\r | |
784 | PortStatus.PortStatus |= USB_PORT_STAT_SUPER_SPEED;\r | |
785 | }\r | |
786 | } else {\r | |
787 | //\r | |
788 | // For high or full/low speed hub, its bit9~10 presents the attached device speed.\r | |
789 | //\r | |
790 | if (XHC_BIT_IS_SET (State, BIT9)) {\r | |
791 | PortStatus.PortStatus |= USB_PORT_STAT_LOW_SPEED;\r | |
792 | } else if (XHC_BIT_IS_SET (State, BIT10)) {\r | |
793 | PortStatus.PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r | |
794 | }\r | |
795 | }\r | |
796 | \r | |
797 | //\r | |
798 | // Convert the XHCI port/port change state to UEFI status\r | |
799 | //\r | |
800 | MapSize = sizeof (mUsbHubPortStateMap) / sizeof (USB_PORT_STATE_MAP);\r | |
801 | for (Index = 0; Index < MapSize; Index++) {\r | |
802 | if (XHC_BIT_IS_SET (State, mUsbHubPortStateMap[Index].HwState)) {\r | |
803 | PortStatus.PortStatus = (UINT16) (PortStatus.PortStatus | mUsbHubPortStateMap[Index].UefiState);\r | |
804 | }\r | |
805 | }\r | |
806 | \r | |
807 | MapSize = sizeof (mUsbHubPortChangeMap) / sizeof (USB_PORT_STATE_MAP);\r | |
808 | for (Index = 0; Index < MapSize; Index++) {\r | |
809 | if (XHC_BIT_IS_SET (State, mUsbHubPortChangeMap[Index].HwState)) {\r | |
810 | PortStatus.PortChangeStatus = (UINT16) (PortStatus.PortChangeStatus | mUsbHubPortChangeMap[Index].UefiState);\r | |
811 | }\r | |
812 | }\r | |
813 | \r | |
814 | MapSize = sizeof (mUsbHubClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);\r | |
815 | \r | |
816 | for (Index = 0; Index < MapSize; Index++) {\r | |
817 | if (XHC_BIT_IS_SET (State, mUsbHubClearPortChangeMap[Index].HwState)) {\r | |
818 | ZeroMem (&ClearPortRequest, sizeof (EFI_USB_DEVICE_REQUEST));\r | |
819 | ClearPortRequest.RequestType = USB_REQUEST_TYPE (EfiUsbNoData, USB_REQ_TYPE_CLASS, USB_TARGET_OTHER);\r | |
820 | ClearPortRequest.Request = (UINT8) USB_REQ_CLEAR_FEATURE;\r | |
821 | ClearPortRequest.Value = mUsbHubClearPortChangeMap[Index].Selector;\r | |
822 | ClearPortRequest.Index = Request->Index;\r | |
823 | ClearPortRequest.Length = 0;\r | |
824 | \r | |
825 | XhcPeiControlTransfer (\r | |
826 | PeiServices,\r | |
827 | This,\r | |
828 | DeviceAddress,\r | |
829 | DeviceSpeed,\r | |
830 | MaximumPacketLength,\r | |
831 | &ClearPortRequest,\r | |
832 | EfiUsbNoData,\r | |
833 | NULL,\r | |
834 | &Len,\r | |
835 | TimeOut,\r | |
836 | Translator,\r | |
837 | TransferResult\r | |
838 | );\r | |
839 | }\r | |
840 | }\r | |
841 | \r | |
842 | XhcPeiPollPortStatusChange (Xhc, Xhc->UsbDevContext[SlotId].RouteString, (UINT8)Request->Index, &PortStatus);\r | |
843 | \r | |
844 | *(UINT32 *) Data = *(UINT32 *) &PortStatus;\r | |
845 | }\r | |
846 | \r | |
847 | FREE_URB:\r | |
848 | XhcPeiFreeUrb (Xhc, Urb);\r | |
849 | \r | |
850 | ON_EXIT:\r | |
851 | \r | |
852 | if (EFI_ERROR (Status)) {\r | |
853 | DEBUG ((EFI_D_ERROR, "XhcPeiControlTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r | |
854 | }\r | |
855 | \r | |
856 | return Status;\r | |
857 | }\r | |
858 | \r | |
859 | /**\r | |
860 | Submits bulk transfer to a bulk endpoint of a USB device.\r | |
861 | \r | |
862 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
863 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
864 | @param DeviceAddress Target device address.\r | |
865 | @param EndPointAddress Endpoint number and its direction in bit 7.\r | |
866 | @param DeviceSpeed Device speed, Low speed device doesn't support\r | |
867 | bulk transfer.\r | |
868 | @param MaximumPacketLength Maximum packet size the endpoint is capable of\r | |
869 | sending or receiving.\r | |
870 | @param Data Array of pointers to the buffers of data to transmit\r | |
871 | from or receive into.\r | |
872 | @param DataLength The lenght of the data buffer.\r | |
873 | @param DataToggle On input, the initial data toggle for the transfer;\r | |
874 | On output, it is updated to to next data toggle to use of\r | |
875 | the subsequent bulk transfer.\r | |
876 | @param TimeOut Indicates the maximum time, in millisecond, which the\r | |
877 | transfer is allowed to complete.\r | |
878 | If Timeout is 0, then the caller must wait for the function\r | |
879 | to be completed until EFI_SUCCESS or EFI_DEVICE_ERROR is returned.\r | |
880 | @param Translator A pointr to the transaction translator data.\r | |
881 | @param TransferResult A pointer to the detailed result information of the\r | |
882 | bulk transfer.\r | |
883 | \r | |
884 | @retval EFI_SUCCESS The transfer was completed successfully.\r | |
885 | @retval EFI_OUT_OF_RESOURCES The transfer failed due to lack of resource.\r | |
886 | @retval EFI_INVALID_PARAMETER Parameters are invalid.\r | |
887 | @retval EFI_TIMEOUT The transfer failed due to timeout.\r | |
888 | @retval EFI_DEVICE_ERROR The transfer failed due to host controller error.\r | |
889 | \r | |
890 | **/\r | |
891 | EFI_STATUS\r | |
892 | EFIAPI\r | |
893 | XhcPeiBulkTransfer (\r | |
894 | IN EFI_PEI_SERVICES **PeiServices,\r | |
895 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
896 | IN UINT8 DeviceAddress,\r | |
897 | IN UINT8 EndPointAddress,\r | |
898 | IN UINT8 DeviceSpeed,\r | |
899 | IN UINTN MaximumPacketLength,\r | |
900 | IN OUT VOID *Data[EFI_USB_MAX_BULK_BUFFER_NUM],\r | |
901 | IN OUT UINTN *DataLength,\r | |
902 | IN OUT UINT8 *DataToggle,\r | |
903 | IN UINTN TimeOut,\r | |
904 | IN EFI_USB2_HC_TRANSACTION_TRANSLATOR *Translator,\r | |
905 | OUT UINT32 *TransferResult\r | |
906 | )\r | |
907 | {\r | |
908 | PEI_XHC_DEV *Xhc;\r | |
909 | URB *Urb;\r | |
910 | UINT8 SlotId;\r | |
911 | EFI_STATUS Status;\r | |
912 | EFI_STATUS RecoveryStatus;\r | |
913 | \r | |
914 | //\r | |
915 | // Validate the parameters\r | |
916 | //\r | |
917 | if ((DataLength == NULL) || (*DataLength == 0) ||\r | |
918 | (Data == NULL) || (Data[0] == NULL) || (TransferResult == NULL)) {\r | |
919 | return EFI_INVALID_PARAMETER;\r | |
920 | }\r | |
921 | \r | |
922 | if ((*DataToggle != 0) && (*DataToggle != 1)) {\r | |
923 | return EFI_INVALID_PARAMETER;\r | |
924 | }\r | |
925 | \r | |
926 | if ((DeviceSpeed == EFI_USB_SPEED_LOW) ||\r | |
927 | ((DeviceSpeed == EFI_USB_SPEED_FULL) && (MaximumPacketLength > 64)) ||\r | |
928 | ((DeviceSpeed == EFI_USB_SPEED_HIGH) && (MaximumPacketLength > 512)) ||\r | |
929 | ((DeviceSpeed == EFI_USB_SPEED_SUPER) && (MaximumPacketLength > 1024))) {\r | |
930 | return EFI_INVALID_PARAMETER;\r | |
931 | }\r | |
932 | \r | |
933 | Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r | |
934 | \r | |
935 | *TransferResult = EFI_USB_ERR_SYSTEM;\r | |
936 | Status = EFI_DEVICE_ERROR;\r | |
937 | \r | |
938 | if (XhcPeiIsHalt (Xhc) || XhcPeiIsSysError (Xhc)) {\r | |
939 | DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: HC is halted or has system error\n"));\r | |
940 | goto ON_EXIT;\r | |
941 | }\r | |
942 | \r | |
943 | //\r | |
944 | // Check if the device is still enabled before every transaction.\r | |
945 | //\r | |
946 | SlotId = XhcPeiBusDevAddrToSlotId (Xhc, DeviceAddress);\r | |
947 | if (SlotId == 0) {\r | |
948 | goto ON_EXIT;\r | |
949 | }\r | |
950 | \r | |
951 | //\r | |
952 | // Create a new URB, insert it into the asynchronous\r | |
953 | // schedule list, then poll the execution status.\r | |
954 | //\r | |
955 | Urb = XhcPeiCreateUrb (\r | |
956 | Xhc,\r | |
957 | DeviceAddress,\r | |
958 | EndPointAddress,\r | |
959 | DeviceSpeed,\r | |
960 | MaximumPacketLength,\r | |
961 | XHC_BULK_TRANSFER,\r | |
962 | NULL,\r | |
963 | Data[0],\r | |
964 | *DataLength,\r | |
965 | NULL,\r | |
966 | NULL\r | |
967 | );\r | |
968 | \r | |
969 | if (Urb == NULL) {\r | |
970 | DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: failed to create URB\n"));\r | |
971 | Status = EFI_OUT_OF_RESOURCES;\r | |
972 | goto ON_EXIT;\r | |
973 | }\r | |
974 | \r | |
975 | Status = XhcPeiExecTransfer (Xhc, FALSE, Urb, TimeOut);\r | |
976 | \r | |
977 | *TransferResult = Urb->Result;\r | |
978 | *DataLength = Urb->Completed;\r | |
979 | \r | |
12e6c738 FT |
980 | if (Status == EFI_TIMEOUT) {\r |
981 | //\r | |
982 | // The transfer timed out. Abort the transfer by dequeueing of the TD.\r | |
983 | //\r | |
984 | RecoveryStatus = XhcPeiDequeueTrbFromEndpoint(Xhc, Urb);\r | |
985 | if (EFI_ERROR(RecoveryStatus)) {\r | |
986 | DEBUG((EFI_D_ERROR, "XhcPeiBulkTransfer: XhcPeiDequeueTrbFromEndpoint failed\n"));\r | |
987 | }\r | |
988 | } else {\r | |
989 | if (*TransferResult == EFI_USB_NOERROR) {\r | |
990 | Status = EFI_SUCCESS;\r | |
958a8181 | 991 | } else if ((*TransferResult == EFI_USB_ERR_STALL) || (*TransferResult == EFI_USB_ERR_BABBLE)) {\r |
12e6c738 FT |
992 | RecoveryStatus = XhcPeiRecoverHaltedEndpoint(Xhc, Urb);\r |
993 | if (EFI_ERROR (RecoveryStatus)) {\r | |
994 | DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: XhcPeiRecoverHaltedEndpoint failed\n"));\r | |
995 | }\r | |
996 | Status = EFI_DEVICE_ERROR;\r | |
d987459f | 997 | }\r |
d987459f SZ |
998 | }\r |
999 | \r | |
1000 | XhcPeiFreeUrb (Xhc, Urb);\r | |
1001 | \r | |
1002 | ON_EXIT:\r | |
1003 | \r | |
1004 | if (EFI_ERROR (Status)) {\r | |
1005 | DEBUG ((EFI_D_ERROR, "XhcPeiBulkTransfer: error - %r, transfer - %x\n", Status, *TransferResult));\r | |
1006 | }\r | |
1007 | \r | |
1008 | return Status;\r | |
1009 | }\r | |
1010 | \r | |
1011 | /**\r | |
1012 | Retrieves the number of root hub ports.\r | |
1013 | \r | |
1014 | @param[in] PeiServices The pointer to the PEI Services Table.\r | |
1015 | @param[in] This The pointer to this instance of the\r | |
1016 | PEI_USB2_HOST_CONTROLLER_PPI.\r | |
1017 | @param[out] PortNumber The pointer to the number of the root hub ports.\r | |
1018 | \r | |
1019 | @retval EFI_SUCCESS The port number was retrieved successfully.\r | |
1020 | @retval EFI_INVALID_PARAMETER PortNumber is NULL.\r | |
1021 | \r | |
1022 | **/\r | |
1023 | EFI_STATUS\r | |
1024 | EFIAPI\r | |
1025 | XhcPeiGetRootHubPortNumber (\r | |
1026 | IN EFI_PEI_SERVICES **PeiServices,\r | |
1027 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
1028 | OUT UINT8 *PortNumber\r | |
1029 | )\r | |
1030 | {\r | |
1031 | PEI_XHC_DEV *XhcDev;\r | |
1032 | XhcDev = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r | |
1033 | \r | |
1034 | if (PortNumber == NULL) {\r | |
1035 | return EFI_INVALID_PARAMETER;\r | |
1036 | }\r | |
1037 | \r | |
1038 | *PortNumber = XhcDev->HcSParams1.Data.MaxPorts;\r | |
1039 | DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortNumber: PortNumber = %x\n", *PortNumber));\r | |
1040 | return EFI_SUCCESS;\r | |
1041 | }\r | |
1042 | \r | |
1043 | /**\r | |
1044 | Clears a feature for the specified root hub port.\r | |
1045 | \r | |
1046 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
1047 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
1048 | @param PortNumber Specifies the root hub port whose feature\r | |
1049 | is requested to be cleared.\r | |
1050 | @param PortFeature Indicates the feature selector associated with the\r | |
1051 | feature clear request.\r | |
1052 | \r | |
1053 | @retval EFI_SUCCESS The feature specified by PortFeature was cleared\r | |
1054 | for the USB root hub port specified by PortNumber.\r | |
1055 | @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r | |
1056 | \r | |
1057 | **/\r | |
1058 | EFI_STATUS\r | |
1059 | EFIAPI\r | |
1060 | XhcPeiClearRootHubPortFeature (\r | |
1061 | IN EFI_PEI_SERVICES **PeiServices,\r | |
1062 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
1063 | IN UINT8 PortNumber,\r | |
1064 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
1065 | )\r | |
1066 | {\r | |
1067 | PEI_XHC_DEV *Xhc;\r | |
1068 | UINT32 Offset;\r | |
1069 | UINT32 State;\r | |
1070 | EFI_STATUS Status;\r | |
1071 | \r | |
1072 | Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r | |
1073 | Status = EFI_SUCCESS;\r | |
1074 | \r | |
1075 | if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {\r | |
1076 | Status = EFI_INVALID_PARAMETER;\r | |
1077 | goto ON_EXIT;\r | |
1078 | }\r | |
1079 | \r | |
1080 | Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r | |
1081 | State = XhcPeiReadOpReg (Xhc, Offset);\r | |
1082 | DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));\r | |
1083 | \r | |
1084 | //\r | |
1085 | // Mask off the port status change bits, these bits are\r | |
1086 | // write clean bits\r | |
1087 | //\r | |
1088 | State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r | |
1089 | \r | |
1090 | switch (PortFeature) {\r | |
1091 | case EfiUsbPortEnable:\r | |
1092 | //\r | |
1093 | // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r | |
1094 | // A port may be disabled by software writing a '1' to this flag.\r | |
1095 | //\r | |
1096 | State |= XHC_PORTSC_PED;\r | |
1097 | State &= ~XHC_PORTSC_RESET;\r | |
1098 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1099 | break;\r | |
1100 | \r | |
1101 | case EfiUsbPortSuspend:\r | |
1102 | State |= XHC_PORTSC_LWS;\r | |
1103 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1104 | State &= ~XHC_PORTSC_PLS;\r | |
1105 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1106 | break;\r | |
1107 | \r | |
1108 | case EfiUsbPortReset:\r | |
1109 | //\r | |
1110 | // PORTSC_RESET BIT(4) bit is RW1S attribute, which means Write-1-to-set status:\r | |
1111 | // Register bits indicate status when read, a clear bit may be set by\r | |
1112 | // writing a '1'. Writing a '0' to RW1S bits has no effect.\r | |
1113 | //\r | |
1114 | break;\r | |
1115 | \r | |
1116 | case EfiUsbPortPower:\r | |
1117 | if (Xhc->HcCParams.Data.Ppc) {\r | |
1118 | //\r | |
1119 | // Port Power Control supported\r | |
1120 | //\r | |
1121 | State &= ~XHC_PORTSC_PP;\r | |
1122 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1123 | }\r | |
1124 | break;\r | |
1125 | \r | |
1126 | case EfiUsbPortOwner:\r | |
1127 | //\r | |
1128 | // XHCI root hub port don't has the owner bit, ignore the operation\r | |
1129 | //\r | |
1130 | break;\r | |
1131 | \r | |
1132 | case EfiUsbPortConnectChange:\r | |
1133 | //\r | |
1134 | // Clear connect status change\r | |
1135 | //\r | |
1136 | State |= XHC_PORTSC_CSC;\r | |
1137 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1138 | break;\r | |
1139 | \r | |
1140 | case EfiUsbPortEnableChange:\r | |
1141 | //\r | |
1142 | // Clear enable status change\r | |
1143 | //\r | |
1144 | State |= XHC_PORTSC_PEC;\r | |
1145 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1146 | break;\r | |
1147 | \r | |
1148 | case EfiUsbPortOverCurrentChange:\r | |
1149 | //\r | |
1150 | // Clear PortOverCurrent change\r | |
1151 | //\r | |
1152 | State |= XHC_PORTSC_OCC;\r | |
1153 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1154 | break;\r | |
1155 | \r | |
1156 | case EfiUsbPortResetChange:\r | |
1157 | //\r | |
1158 | // Clear Port Reset change\r | |
1159 | //\r | |
1160 | State |= XHC_PORTSC_PRC;\r | |
1161 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1162 | break;\r | |
1163 | \r | |
1164 | case EfiUsbPortSuspendChange:\r | |
1165 | //\r | |
1166 | // Not supported or not related operation\r | |
1167 | //\r | |
1168 | break;\r | |
1169 | \r | |
1170 | default:\r | |
1171 | Status = EFI_INVALID_PARAMETER;\r | |
1172 | break;\r | |
1173 | }\r | |
1174 | \r | |
1175 | ON_EXIT:\r | |
1176 | DEBUG ((EFI_D_INFO, "XhcPeiClearRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));\r | |
1177 | return Status;\r | |
1178 | }\r | |
1179 | \r | |
1180 | /**\r | |
1181 | Sets a feature for the specified root hub port.\r | |
1182 | \r | |
1183 | @param PeiServices The pointer of EFI_PEI_SERVICES\r | |
1184 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI\r | |
1185 | @param PortNumber Root hub port to set.\r | |
1186 | @param PortFeature Feature to set.\r | |
1187 | \r | |
1188 | @retval EFI_SUCCESS The feature specified by PortFeature was set.\r | |
1189 | @retval EFI_INVALID_PARAMETER PortNumber is invalid or PortFeature is invalid.\r | |
1190 | @retval EFI_TIMEOUT The time out occurred.\r | |
1191 | \r | |
1192 | **/\r | |
1193 | EFI_STATUS\r | |
1194 | EFIAPI\r | |
1195 | XhcPeiSetRootHubPortFeature (\r | |
1196 | IN EFI_PEI_SERVICES **PeiServices,\r | |
1197 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
1198 | IN UINT8 PortNumber,\r | |
1199 | IN EFI_USB_PORT_FEATURE PortFeature\r | |
1200 | )\r | |
1201 | {\r | |
1202 | PEI_XHC_DEV *Xhc;\r | |
1203 | UINT32 Offset;\r | |
1204 | UINT32 State;\r | |
1205 | EFI_STATUS Status;\r | |
1206 | \r | |
1207 | Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r | |
1208 | Status = EFI_SUCCESS;\r | |
1209 | \r | |
1210 | if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {\r | |
1211 | Status = EFI_INVALID_PARAMETER;\r | |
1212 | goto ON_EXIT;\r | |
1213 | }\r | |
1214 | \r | |
1215 | Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r | |
1216 | State = XhcPeiReadOpReg (Xhc, Offset);\r | |
1217 | DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: Port: %x State: %x\n", PortNumber, State));\r | |
1218 | \r | |
1219 | //\r | |
1220 | // Mask off the port status change bits, these bits are\r | |
1221 | // write clean bits\r | |
1222 | //\r | |
1223 | State &= ~ (BIT1 | BIT17 | BIT18 | BIT19 | BIT20 | BIT21 | BIT22 | BIT23);\r | |
1224 | \r | |
1225 | switch (PortFeature) {\r | |
1226 | case EfiUsbPortEnable:\r | |
1227 | //\r | |
1228 | // Ports may only be enabled by the xHC. Software cannot enable a port by writing a '1' to this flag.\r | |
1229 | // A port may be disabled by software writing a '1' to this flag.\r | |
1230 | //\r | |
1231 | break;\r | |
1232 | \r | |
1233 | case EfiUsbPortSuspend:\r | |
1234 | State |= XHC_PORTSC_LWS;\r | |
1235 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1236 | State &= ~XHC_PORTSC_PLS;\r | |
1237 | State |= (3 << 5) ;\r | |
1238 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1239 | break;\r | |
1240 | \r | |
1241 | case EfiUsbPortReset:\r | |
1242 | //\r | |
1243 | // Make sure Host Controller not halt before reset it\r | |
1244 | //\r | |
1245 | if (XhcPeiIsHalt (Xhc)) {\r | |
1246 | Status = XhcPeiRunHC (Xhc, XHC_GENERIC_TIMEOUT);\r | |
1247 | if (EFI_ERROR (Status)) {\r | |
1248 | break;\r | |
1249 | }\r | |
1250 | }\r | |
1251 | \r | |
1252 | //\r | |
1253 | // 4.3.1 Resetting a Root Hub Port\r | |
1254 | // 1) Write the PORTSC register with the Port Reset (PR) bit set to '1'.\r | |
1255 | // 2) Wait for a successful Port Status Change Event for the port, where the Port Reset Change (PRC)\r | |
1256 | // bit in the PORTSC field is set to '1'.\r | |
1257 | //\r | |
1258 | State |= XHC_PORTSC_RESET;\r | |
1259 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1260 | XhcPeiWaitOpRegBit(Xhc, Offset, XHC_PORTSC_PRC, TRUE, XHC_GENERIC_TIMEOUT);\r | |
1261 | break;\r | |
1262 | \r | |
1263 | case EfiUsbPortPower:\r | |
1264 | if (Xhc->HcCParams.Data.Ppc) {\r | |
1265 | //\r | |
1266 | // Port Power Control supported\r | |
1267 | //\r | |
1268 | State |= XHC_PORTSC_PP;\r | |
1269 | XhcPeiWriteOpReg (Xhc, Offset, State);\r | |
1270 | }\r | |
1271 | break;\r | |
1272 | \r | |
1273 | case EfiUsbPortOwner:\r | |
1274 | //\r | |
1275 | // XHCI root hub port don't has the owner bit, ignore the operation\r | |
1276 | //\r | |
1277 | break;\r | |
1278 | \r | |
1279 | default:\r | |
1280 | Status = EFI_INVALID_PARAMETER;\r | |
1281 | }\r | |
1282 | \r | |
1283 | ON_EXIT:\r | |
1284 | DEBUG ((EFI_D_INFO, "XhcPeiSetRootHubPortFeature: PortFeature: %x Status = %r\n", PortFeature, Status));\r | |
1285 | return Status;\r | |
1286 | }\r | |
1287 | \r | |
1288 | /**\r | |
1289 | Retrieves the current status of a USB root hub port.\r | |
1290 | \r | |
1291 | @param PeiServices The pointer of EFI_PEI_SERVICES.\r | |
1292 | @param This The pointer of PEI_USB2_HOST_CONTROLLER_PPI.\r | |
1293 | @param PortNumber The root hub port to retrieve the state from.\r | |
1294 | @param PortStatus Variable to receive the port state.\r | |
1295 | \r | |
1296 | @retval EFI_SUCCESS The status of the USB root hub port specified.\r | |
1297 | by PortNumber was returned in PortStatus.\r | |
1298 | @retval EFI_INVALID_PARAMETER PortNumber is invalid.\r | |
1299 | \r | |
1300 | **/\r | |
1301 | EFI_STATUS\r | |
1302 | EFIAPI\r | |
1303 | XhcPeiGetRootHubPortStatus (\r | |
1304 | IN EFI_PEI_SERVICES **PeiServices,\r | |
1305 | IN PEI_USB2_HOST_CONTROLLER_PPI *This,\r | |
1306 | IN UINT8 PortNumber,\r | |
1307 | OUT EFI_USB_PORT_STATUS *PortStatus\r | |
1308 | )\r | |
1309 | {\r | |
1310 | PEI_XHC_DEV *Xhc;\r | |
1311 | UINT32 Offset;\r | |
1312 | UINT32 State;\r | |
1313 | UINTN Index;\r | |
1314 | UINTN MapSize;\r | |
1315 | USB_DEV_ROUTE ParentRouteChart;\r | |
1316 | \r | |
1317 | if (PortStatus == NULL) {\r | |
1318 | return EFI_INVALID_PARAMETER;\r | |
1319 | }\r | |
1320 | \r | |
1321 | Xhc = PEI_RECOVERY_USB_XHC_DEV_FROM_THIS (This);\r | |
1322 | \r | |
1323 | if (PortNumber >= Xhc->HcSParams1.Data.MaxPorts) {\r | |
1324 | return EFI_INVALID_PARAMETER;\r | |
1325 | }\r | |
1326 | \r | |
1327 | //\r | |
1328 | // Clear port status.\r | |
1329 | //\r | |
1330 | PortStatus->PortStatus = 0;\r | |
1331 | PortStatus->PortChangeStatus = 0;\r | |
1332 | \r | |
1333 | Offset = (UINT32) (XHC_PORTSC_OFFSET + (0x10 * PortNumber));\r | |
1334 | State = XhcPeiReadOpReg (Xhc, Offset);\r | |
1335 | DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: Port: %x State: %x\n", PortNumber, State));\r | |
1336 | \r | |
1337 | //\r | |
1338 | // According to XHCI 1.0 spec, bit 10~13 of the root port status register identifies the speed of the attached device.\r | |
1339 | //\r | |
1340 | switch ((State & XHC_PORTSC_PS) >> 10) {\r | |
1341 | case 2:\r | |
1342 | PortStatus->PortStatus |= USB_PORT_STAT_LOW_SPEED;\r | |
1343 | break;\r | |
1344 | \r | |
1345 | case 3:\r | |
1346 | PortStatus->PortStatus |= USB_PORT_STAT_HIGH_SPEED;\r | |
1347 | break;\r | |
1348 | \r | |
1349 | case 4:\r | |
1350 | PortStatus->PortStatus |= USB_PORT_STAT_SUPER_SPEED;\r | |
1351 | break;\r | |
1352 | \r | |
1353 | default:\r | |
1354 | break;\r | |
1355 | }\r | |
1356 | \r | |
1357 | //\r | |
1358 | // Convert the XHCI port/port change state to UEFI status\r | |
1359 | //\r | |
1360 | MapSize = sizeof (mUsbPortStateMap) / sizeof (USB_PORT_STATE_MAP);\r | |
1361 | \r | |
1362 | for (Index = 0; Index < MapSize; Index++) {\r | |
1363 | if (XHC_BIT_IS_SET (State, mUsbPortStateMap[Index].HwState)) {\r | |
1364 | PortStatus->PortStatus = (UINT16) (PortStatus->PortStatus | mUsbPortStateMap[Index].UefiState);\r | |
1365 | }\r | |
1366 | }\r | |
1367 | //\r | |
1368 | // Bit5~8 reflects its current link state.\r | |
1369 | //\r | |
1370 | if ((State & XHC_PORTSC_PLS) >> 5 == 3) {\r | |
1371 | PortStatus->PortStatus |= USB_PORT_STAT_SUSPEND;\r | |
1372 | }\r | |
1373 | \r | |
1374 | MapSize = sizeof (mUsbPortChangeMap) / sizeof (USB_PORT_STATE_MAP);\r | |
1375 | \r | |
1376 | for (Index = 0; Index < MapSize; Index++) {\r | |
1377 | if (XHC_BIT_IS_SET (State, mUsbPortChangeMap[Index].HwState)) {\r | |
1378 | PortStatus->PortChangeStatus = (UINT16) (PortStatus->PortChangeStatus | mUsbPortChangeMap[Index].UefiState);\r | |
1379 | }\r | |
1380 | }\r | |
1381 | \r | |
1382 | MapSize = sizeof (mUsbClearPortChangeMap) / sizeof (USB_CLEAR_PORT_MAP);\r | |
1383 | \r | |
1384 | for (Index = 0; Index < MapSize; Index++) {\r | |
1385 | if (XHC_BIT_IS_SET (State, mUsbClearPortChangeMap[Index].HwState)) {\r | |
1386 | XhcPeiClearRootHubPortFeature (PeiServices, This, PortNumber, (EFI_USB_PORT_FEATURE)mUsbClearPortChangeMap[Index].Selector);\r | |
1387 | }\r | |
1388 | }\r | |
1389 | \r | |
1390 | //\r | |
1391 | // Poll the root port status register to enable/disable corresponding device slot if there is a device attached/detached.\r | |
1392 | // For those devices behind hub, we get its attach/detach event by hooking Get_Port_Status request at control transfer for those hub.\r | |
1393 | //\r | |
1394 | ParentRouteChart.Dword = 0;\r | |
1395 | XhcPeiPollPortStatusChange (Xhc, ParentRouteChart, PortNumber, PortStatus);\r | |
1396 | \r | |
1397 | DEBUG ((EFI_D_INFO, "XhcPeiGetRootHubPortStatus: PortChangeStatus: %x PortStatus: %x\n", PortStatus->PortChangeStatus, PortStatus->PortStatus));\r | |
1398 | return EFI_SUCCESS;\r | |
1399 | }\r | |
1400 | \r | |
1401 | /**\r | |
1402 | @param FileHandle Handle of the file being invoked.\r | |
1403 | @param PeiServices Describes the list of possible PEI Services.\r | |
1404 | \r | |
1405 | @retval EFI_SUCCESS PPI successfully installed.\r | |
1406 | \r | |
1407 | **/\r | |
1408 | EFI_STATUS\r | |
1409 | EFIAPI\r | |
1410 | XhcPeimEntry (\r | |
1411 | IN EFI_PEI_FILE_HANDLE FileHandle,\r | |
1412 | IN CONST EFI_PEI_SERVICES **PeiServices\r | |
1413 | )\r | |
1414 | {\r | |
1415 | PEI_USB_CONTROLLER_PPI *UsbControllerPpi;\r | |
1416 | EFI_STATUS Status;\r | |
1417 | UINT8 Index;\r | |
1418 | UINTN ControllerType;\r | |
1419 | UINTN BaseAddress;\r | |
1420 | UINTN MemPages;\r | |
1421 | PEI_XHC_DEV *XhcDev;\r | |
1422 | EFI_PHYSICAL_ADDRESS TempPtr;\r | |
1423 | UINT32 PageSize;\r | |
1424 | \r | |
1425 | //\r | |
1426 | // Shadow this PEIM to run from memory.\r | |
1427 | //\r | |
1428 | if (!EFI_ERROR (PeiServicesRegisterForShadow (FileHandle))) {\r | |
1429 | return EFI_SUCCESS;\r | |
1430 | }\r | |
1431 | \r | |
1432 | Status = PeiServicesLocatePpi (\r | |
1433 | &gPeiUsbControllerPpiGuid,\r | |
1434 | 0,\r | |
1435 | NULL,\r | |
1436 | (VOID **) &UsbControllerPpi\r | |
1437 | );\r | |
1438 | if (EFI_ERROR (Status)) {\r | |
1439 | return EFI_UNSUPPORTED;\r | |
1440 | }\r | |
1441 | \r | |
1442 | Index = 0;\r | |
1443 | while (TRUE) {\r | |
1444 | Status = UsbControllerPpi->GetUsbController (\r | |
1445 | (EFI_PEI_SERVICES **) PeiServices,\r | |
1446 | UsbControllerPpi,\r | |
1447 | Index,\r | |
1448 | &ControllerType,\r | |
1449 | &BaseAddress\r | |
1450 | );\r | |
1451 | //\r | |
1452 | // When status is error, it means no controller is found.\r | |
1453 | //\r | |
1454 | if (EFI_ERROR (Status)) {\r | |
1455 | break;\r | |
1456 | }\r | |
1457 | \r | |
1458 | //\r | |
1459 | // This PEIM is for XHC type controller.\r | |
1460 | //\r | |
1461 | if (ControllerType != PEI_XHCI_CONTROLLER) {\r | |
1462 | Index++;\r | |
1463 | continue;\r | |
1464 | }\r | |
1465 | \r | |
1466 | MemPages = EFI_SIZE_TO_PAGES (sizeof (PEI_XHC_DEV));\r | |
1467 | Status = PeiServicesAllocatePages (\r | |
1468 | EfiBootServicesData,\r | |
1469 | MemPages,\r | |
1470 | &TempPtr\r | |
1471 | );\r | |
1472 | if (EFI_ERROR (Status)) {\r | |
1473 | return EFI_OUT_OF_RESOURCES;\r | |
1474 | }\r | |
1475 | ZeroMem ((VOID *) (UINTN) TempPtr, EFI_PAGES_TO_SIZE (MemPages));\r | |
1476 | XhcDev = (PEI_XHC_DEV *) ((UINTN) TempPtr);\r | |
1477 | \r | |
1478 | XhcDev->Signature = USB_XHC_DEV_SIGNATURE;\r | |
1479 | XhcDev->UsbHostControllerBaseAddress = (UINT32) BaseAddress;\r | |
4918a06a | 1480 | XhcDev->CapLength = (UINT8) (XhcPeiReadCapRegister (XhcDev, XHC_CAPLENGTH_OFFSET) & 0x0FF);\r |
d987459f SZ |
1481 | XhcDev->HcSParams1.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS1_OFFSET);\r |
1482 | XhcDev->HcSParams2.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCSPARAMS2_OFFSET);\r | |
1483 | XhcDev->HcCParams.Dword = XhcPeiReadCapRegister (XhcDev, XHC_HCCPARAMS_OFFSET);\r | |
1484 | XhcDev->DBOff = XhcPeiReadCapRegister (XhcDev, XHC_DBOFF_OFFSET);\r | |
1485 | XhcDev->RTSOff = XhcPeiReadCapRegister (XhcDev, XHC_RTSOFF_OFFSET);\r | |
1486 | \r | |
1487 | //\r | |
1488 | // This PageSize field defines the page size supported by the xHC implementation.\r | |
1489 | // This xHC supports a page size of 2^(n+12) if bit n is Set. For example,\r | |
1490 | // if bit 0 is Set, the xHC supports 4k byte page sizes.\r | |
1491 | //\r | |
1492 | PageSize = XhcPeiReadOpReg (XhcDev, XHC_PAGESIZE_OFFSET) & XHC_PAGESIZE_MASK;\r | |
1493 | XhcDev->PageSize = 1 << (HighBitSet32 (PageSize) + 12);\r | |
1494 | \r | |
1495 | DEBUG ((EFI_D_INFO, "XhciPei: UsbHostControllerBaseAddress: %x\n", XhcDev->UsbHostControllerBaseAddress));\r | |
1496 | DEBUG ((EFI_D_INFO, "XhciPei: CapLength: %x\n", XhcDev->CapLength));\r | |
1497 | DEBUG ((EFI_D_INFO, "XhciPei: HcSParams1: %x\n", XhcDev->HcSParams1.Dword));\r | |
1498 | DEBUG ((EFI_D_INFO, "XhciPei: HcSParams2: %x\n", XhcDev->HcSParams2.Dword));\r | |
1499 | DEBUG ((EFI_D_INFO, "XhciPei: HcCParams: %x\n", XhcDev->HcCParams.Dword));\r | |
1500 | DEBUG ((EFI_D_INFO, "XhciPei: DBOff: %x\n", XhcDev->DBOff));\r | |
1501 | DEBUG ((EFI_D_INFO, "XhciPei: RTSOff: %x\n", XhcDev->RTSOff));\r | |
1502 | DEBUG ((EFI_D_INFO, "XhciPei: PageSize: %x\n", XhcDev->PageSize));\r | |
1503 | \r | |
1504 | XhcPeiResetHC (XhcDev, XHC_RESET_TIMEOUT);\r | |
1505 | ASSERT (XhcPeiIsHalt (XhcDev));\r | |
1506 | \r | |
1507 | //\r | |
1508 | // Initialize the schedule\r | |
1509 | //\r | |
1510 | XhcPeiInitSched (XhcDev);\r | |
1511 | \r | |
1512 | //\r | |
1513 | // Start the Host Controller\r | |
1514 | //\r | |
1515 | XhcPeiRunHC (XhcDev, XHC_GENERIC_TIMEOUT);\r | |
1516 | \r | |
1517 | //\r | |
1518 | // Wait for root port state stable\r | |
1519 | //\r | |
1520 | MicroSecondDelay (XHC_ROOT_PORT_STATE_STABLE);\r | |
1521 | \r | |
1522 | XhcDev->Usb2HostControllerPpi.ControlTransfer = XhcPeiControlTransfer;\r | |
1523 | XhcDev->Usb2HostControllerPpi.BulkTransfer = XhcPeiBulkTransfer;\r | |
1524 | XhcDev->Usb2HostControllerPpi.GetRootHubPortNumber = XhcPeiGetRootHubPortNumber;\r | |
1525 | XhcDev->Usb2HostControllerPpi.GetRootHubPortStatus = XhcPeiGetRootHubPortStatus;\r | |
1526 | XhcDev->Usb2HostControllerPpi.SetRootHubPortFeature = XhcPeiSetRootHubPortFeature;\r | |
1527 | XhcDev->Usb2HostControllerPpi.ClearRootHubPortFeature = XhcPeiClearRootHubPortFeature;\r | |
1528 | \r | |
1529 | XhcDev->PpiDescriptor.Flags = (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST);\r | |
1530 | XhcDev->PpiDescriptor.Guid = &gPeiUsb2HostControllerPpiGuid;\r | |
1531 | XhcDev->PpiDescriptor.Ppi = &XhcDev->Usb2HostControllerPpi;\r | |
1532 | \r | |
1533 | PeiServicesInstallPpi (&XhcDev->PpiDescriptor);\r | |
1534 | \r | |
1535 | Index++;\r | |
1536 | }\r | |
1537 | \r | |
1538 | return EFI_SUCCESS;\r | |
1539 | }\r | |
1540 | \r |