[mirror_edk2.git] / MdeModulePkg / Bus / Pci / XhciPei / XhcPeim.h

/** @file\r
Private Header file for Usb Host Controller PEIM\r
\r
Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
\r
SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#ifndef _RECOVERY_XHC_H_\r
#define _RECOVERY_XHC_H_\r
\r
#include <PiPei.h>\r
\r
#include <Ppi/UsbController.h>\r
#include <Ppi/Usb2HostController.h>\r
#include <Ppi/IoMmu.h>\r
#include <Ppi/EndOfPeiPhase.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/PeiServicesLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/TimerLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
\r
typedef struct _PEI_XHC_DEV      PEI_XHC_DEV;\r
typedef struct _USB_DEV_CONTEXT  USB_DEV_CONTEXT;\r
\r
#include "UsbHcMem.h"\r
#include "XhciReg.h"\r
#include "XhciSched.h"\r
\r
#define CMD_RING_TRB_NUMBER    0x100\r
#define TR_RING_TRB_NUMBER     0x100\r
#define ERST_NUMBER            0x01\r
#define EVENT_RING_TRB_NUMBER  0x200\r
\r
#define XHC_1_MICROSECOND  1\r
#define XHC_1_MILLISECOND  (1000 * XHC_1_MICROSECOND)\r
#define XHC_1_SECOND       (1000 * XHC_1_MILLISECOND)\r
\r
//\r
// XHC reset timeout experience values.\r
// The unit is millisecond, setting it as 1s.\r
//\r
#define XHC_RESET_TIMEOUT  (1000)\r
\r
//\r
// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.\r
// The unit is microsecond, setting it as 10ms.\r
//\r
#define XHC_RESET_RECOVERY_DELAY  (10 * 1000)\r
\r
//\r
// Wait for root port state stable.\r
//\r
#define XHC_ROOT_PORT_STATE_STABLE  (200 * XHC_1_MILLISECOND)\r
\r
//\r
// XHC generic timeout experience values.\r
// The unit is millisecond, setting it as 10s.\r
//\r
#define XHC_GENERIC_TIMEOUT  (10 * 1000)\r
\r
#define XHC_LOW_32BIT(Addr64)      ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
#define XHC_HIGH_32BIT(Addr64)     ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
#define XHC_BIT_IS_SET(Data, Bit)  ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
\r
#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \\r
          (XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))\r
\r
#define USB_DESC_TYPE_HUB              0x29\r
#define USB_DESC_TYPE_HUB_SUPER_SPEED  0x2a\r
\r
//\r
// The RequestType in EFI_USB_DEVICE_REQUEST is composed of\r
// three fields: One bit direction, 2 bit type, and 5 bit\r
// target.\r
//\r
#define USB_REQUEST_TYPE(Dir, Type, Target) \\r
          ((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) | (Type) | (Target)))\r
\r
struct _USB_DEV_CONTEXT {\r
  //\r
  // Whether this entry in UsbDevContext array is used or not.\r
  //\r
  BOOLEAN          Enabled;\r
  //\r
  // The slot id assigned to the new device through XHCI's Enable_Slot cmd.\r
  //\r
  UINT8            SlotId;\r
  //\r
  // The route string presented an attached usb device.\r
  //\r
  USB_DEV_ROUTE    RouteString;\r
  //\r
  // The route string of parent device if it exists. Otherwise it's zero.\r
  //\r
  USB_DEV_ROUTE    ParentRouteString;\r
  //\r
  // The actual device address assigned by XHCI through Address_Device command.\r
  //\r
  UINT8            XhciDevAddr;\r
  //\r
  // The requested device address from UsbBus driver through Set_Address standard usb request.\r
  // As XHCI spec replaces this request with Address_Device command, we have to record the\r
  // requested device address and establish a mapping relationship with the actual device address.\r
  // Then UsbBus driver just need to be aware of the requested device address to access usb device\r
  // through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual\r
  // device address and access the actual device.\r
  //\r
  UINT8                        BusDevAddr;\r
  //\r
  // The pointer to the input device context.\r
  //\r
  VOID                         *InputContext;\r
  //\r
  // The pointer to the output device context.\r
  //\r
  VOID                         *OutputContext;\r
  //\r
  // The transfer queue for every endpoint.\r
  //\r
  VOID                         *EndpointTransferRing[31];\r
  //\r
  // The device descriptor which is stored to support XHCI's Evaluate_Context cmd.\r
  //\r
  EFI_USB_DEVICE_DESCRIPTOR    DevDesc;\r
  //\r
  // As a usb device may include multiple configuration descriptors, we dynamically allocate an array\r
  // to store them.\r
  // Note that every configuration descriptor stored here includes those lower level descriptors,\r
  // such as Interface descriptor, Endpoint descriptor, and so on.\r
  // These information is used to support XHCI's Config_Endpoint cmd.\r
  //\r
  EFI_USB_CONFIG_DESCRIPTOR    **ConfDesc;\r
};\r
\r
#define USB_XHC_DEV_SIGNATURE  SIGNATURE_32 ('x', 'h', 'c', 'i')\r
\r
struct _PEI_XHC_DEV {\r
  UINTN                           Signature;\r
  PEI_USB2_HOST_CONTROLLER_PPI    Usb2HostControllerPpi;\r
  EFI_PEI_PPI_DESCRIPTOR          PpiDescriptor;\r
  UINT32                          UsbHostControllerBaseAddress;\r
  USBHC_MEM_POOL                  *MemPool;\r
\r
  //\r
  // EndOfPei callback is used to stop the XHC DMA operation\r
  // after exit PEI phase.\r
  //\r
  EFI_PEI_NOTIFY_DESCRIPTOR       EndOfPeiNotifyList;\r
\r
  //\r
  // XHCI configuration data\r
  //\r
  UINT8                           CapLength;      ///< Capability Register Length\r
  XHC_HCSPARAMS1                  HcSParams1;     ///< Structural Parameters 1\r
  XHC_HCSPARAMS2                  HcSParams2;     ///< Structural Parameters 2\r
  XHC_HCCPARAMS                   HcCParams;      ///< Capability Parameters\r
  UINT32                          DBOff;          ///< Doorbell Offset\r
  UINT32                          RTSOff;         ///< Runtime Register Space Offset\r
  UINT32                          PageSize;\r
  UINT32                          MaxScratchpadBufs;\r
  UINT64                          *ScratchBuf;\r
  VOID                            *ScratchMap;\r
  UINT64                          *ScratchEntry;\r
  UINTN                           *ScratchEntryMap;\r
  UINT64                          *DCBAA;\r
  UINT32                          MaxSlotsEn;\r
  //\r
  // Cmd Transfer Ring\r
  //\r
  TRANSFER_RING                   CmdRing;\r
  //\r
  // EventRing\r
  //\r
  EVENT_RING                      EventRing;\r
\r
  //\r
  // Store device contexts managed by XHCI device\r
  // The array supports up to 255 devices, entry 0 is reserved and should not be used.\r
  //\r
  USB_DEV_CONTEXT                 UsbDevContext[256];\r
};\r
\r
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a)         CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)\r
#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a)  CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)\r
\r
/**\r
  Initialize the memory management pool for the host controller.\r
\r
  @return Pointer to the allocated memory pool or NULL if failed.\r
\r
**/\r
USBHC_MEM_POOL *\r
UsbHcInitMemPool (\r
  VOID\r
  )\r
;\r
\r
/**\r
  Release the memory management pool.\r
\r
  @param  Pool          The USB memory pool to free.\r
\r
**/\r
VOID\r
UsbHcFreeMemPool (\r
  IN USBHC_MEM_POOL  *Pool\r
  )\r
;\r
\r
/**\r
  Allocate some memory from the host controller's memory pool\r
  which can be used to communicate with host controller.\r
\r
  @param  Pool          The host controller's memory pool.\r
  @param  Size          Size of the memory to allocate.\r
\r
  @return The allocated memory or NULL.\r
\r
**/\r
VOID *\r
UsbHcAllocateMem (\r
  IN USBHC_MEM_POOL  *Pool,\r
  IN UINTN           Size\r
  )\r
;\r
\r
/**\r
  Free the allocated memory back to the memory pool.\r
\r
  @param  Pool          The memory pool of the host controller.\r
  @param  Mem           The memory to free.\r
  @param  Size          The size of the memory to free.\r
\r
**/\r
VOID\r
UsbHcFreeMem (\r
  IN USBHC_MEM_POOL  *Pool,\r
  IN VOID            *Mem,\r
  IN UINTN           Size\r
  )\r
;\r
\r
/**\r
  Initialize IOMMU.\r
**/\r
VOID\r
IoMmuInit (\r
  VOID\r
  );\r
\r
/**\r
  Provides the controller-specific addresses required to access system memory from a\r
  DMA bus master.\r
\r
  @param  Operation             Indicates if the bus master is going to read or write to system memory.\r
  @param  HostAddress           The system memory address to map to the PCI controller.\r
  @param  NumberOfBytes         On input the number of bytes to map. On output the number of bytes\r
                                that were mapped.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The range was mapped for the returned NumberOfBytes.\r
  @retval EFI_UNSUPPORTED       The HostAddress cannot be mapped as a common buffer.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The request could not be completed due to a lack of resources.\r
  @retval EFI_DEVICE_ERROR      The system hardware could not map the requested address.\r
\r
**/\r
EFI_STATUS\r
IoMmuMap (\r
  IN  EDKII_IOMMU_OPERATION  Operation,\r
  IN  VOID                   *HostAddress,\r
  IN  OUT UINTN              *NumberOfBytes,\r
  OUT EFI_PHYSICAL_ADDRESS   *DeviceAddress,\r
  OUT VOID                   **Mapping\r
  );\r
\r
/**\r
  Completes the Map() operation and releases any corresponding resources.\r
\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The range was unmapped.\r
  @retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
  @retval EFI_DEVICE_ERROR      The data was not committed to the target system memory.\r
**/\r
EFI_STATUS\r
IoMmuUnmap (\r
  IN VOID  *Mapping\r
  );\r
\r
/**\r
  Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
  OperationBusMasterCommonBuffer64 mapping.\r
\r
  @param  Pages                 The number of pages to allocate.\r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
IoMmuAllocateBuffer (\r
  IN UINTN                  Pages,\r
  OUT VOID                  **HostAddress,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
/**\r
  Frees memory that was allocated with AllocateBuffer().\r
\r
  @param  Pages                 The number of pages to free.\r
  @param  HostAddress           The base system memory address of the allocated range.\r
  @param  Mapping               The mapping value returned from Map().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were freed.\r
  @retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
                                was not allocated with AllocateBuffer().\r
\r
**/\r
EFI_STATUS\r
IoMmuFreeBuffer (\r
  IN UINTN  Pages,\r
  IN VOID   *HostAddress,\r
  IN VOID   *Mapping\r
  );\r
\r
/**\r
  Allocates aligned pages that are suitable for an OperationBusMasterCommonBuffer or\r
  OperationBusMasterCommonBuffer64 mapping.\r
\r
  @param  Pages                 The number of pages to allocate.\r
  @param  Alignment             The requested alignment of the allocation.  Must be a power of two.\r
  @param  HostAddress           A pointer to store the base system memory address of the\r
                                allocated range.\r
  @param  DeviceAddress         The resulting map address for the bus master PCI controller to use to\r
                                access the hosts HostAddress.\r
  @param  Mapping               A resulting value to pass to Unmap().\r
\r
  @retval EFI_SUCCESS           The requested memory pages were allocated.\r
  @retval EFI_UNSUPPORTED       Attributes is unsupported. The only legal attribute bits are\r
                                MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
  @retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
  @retval EFI_OUT_OF_RESOURCES  The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
IoMmuAllocateAlignedBuffer (\r
  IN UINTN                  Pages,\r
  IN UINTN                  Alignment,\r
  OUT VOID                  **HostAddress,\r
  OUT EFI_PHYSICAL_ADDRESS  *DeviceAddress,\r
  OUT VOID                  **Mapping\r
  );\r
\r
#endif\r
Commit	Line	Data
d987459f SZ	1	/** @file\r
	2	Private Header file for Usb Host Controller PEIM\r
	3	\r
26b85012	4	Copyright (c) 2014 - 2016, Intel Corporation. All rights reserved.<BR>\r
d987459f	5	\r
9d510e61	6	SPDX-License-Identifier: BSD-2-Clause-Patent\r
d987459f SZ	7	\r
	8	**/\r
	9	\r
	10	#ifndef _RECOVERY_XHC_H_\r
	11	#define _RECOVERY_XHC_H_\r
	12	\r
	13	#include <PiPei.h>\r
	14	\r
	15	#include <Ppi/UsbController.h>\r
	16	#include <Ppi/Usb2HostController.h>\r
b575ca32 JY	17	#include <Ppi/IoMmu.h>\r
b575ca32 JY	18	#include <Ppi/EndOfPeiPhase.h>\r
d987459f SZ	19	\r
	20	#include <Library/DebugLib.h>\r
	21	#include <Library/PeimEntryPoint.h>\r
	22	#include <Library/PeiServicesLib.h>\r
	23	#include <Library/BaseMemoryLib.h>\r
	24	#include <Library/TimerLib.h>\r
	25	#include <Library/IoLib.h>\r
	26	#include <Library/MemoryAllocationLib.h>\r
	27	\r
1436aea4 MK	28	typedef struct _PEI_XHC_DEV PEI_XHC_DEV;\r
1436aea4 MK	29	typedef struct _USB_DEV_CONTEXT USB_DEV_CONTEXT;\r
d987459f SZ	30	\r
	31	#include "UsbHcMem.h"\r
	32	#include "XhciReg.h"\r
	33	#include "XhciSched.h"\r
	34	\r
1436aea4 MK	35	#define CMD_RING_TRB_NUMBER 0x100\r
	36	#define TR_RING_TRB_NUMBER 0x100\r
	37	#define ERST_NUMBER 0x01\r
	38	#define EVENT_RING_TRB_NUMBER 0x200\r
d987459f	39	\r
1436aea4 MK	40	#define XHC_1_MICROSECOND 1\r
	41	#define XHC_1_MILLISECOND (1000 * XHC_1_MICROSECOND)\r
	42	#define XHC_1_SECOND (1000 * XHC_1_MILLISECOND)\r
d987459f SZ	43	\r
	44	//\r
	45	// XHC reset timeout experience values.\r
26cd2d6d	46	// The unit is millisecond, setting it as 1s.\r
d987459f	47	//\r
1436aea4	48	#define XHC_RESET_TIMEOUT (1000)\r
d987459f	49	\r
26b85012 FT	50	//\r
	51	// TRSTRCY delay requirement in usb 2.0 spec chapter 7.1.7.5.\r
	52	// The unit is microsecond, setting it as 10ms.\r
	53	//\r
1436aea4	54	#define XHC_RESET_RECOVERY_DELAY (10 * 1000)\r
26b85012	55	\r
d987459f SZ	56	//\r
	57	// Wait for root port state stable.\r
	58	//\r
	59	#define XHC_ROOT_PORT_STATE_STABLE (200 * XHC_1_MILLISECOND)\r
	60	\r
26cd2d6d FT	61	//\r
	62	// XHC generic timeout experience values.\r
	63	// The unit is millisecond, setting it as 10s.\r
	64	//\r
1436aea4	65	#define XHC_GENERIC_TIMEOUT (10 * 1000)\r
d987459f	66	\r
1436aea4 MK	67	#define XHC_LOW_32BIT(Addr64) ((UINT32)(((UINTN)(Addr64)) & 0XFFFFFFFF))\r
	68	#define XHC_HIGH_32BIT(Addr64) ((UINT32)(RShiftU64((UINTN)(Addr64), 32) & 0XFFFFFFFF))\r
	69	#define XHC_BIT_IS_SET(Data, Bit) ((BOOLEAN)(((Data) & (Bit)) == (Bit)))\r
d987459f SZ	70	\r
	71	#define XHC_REG_BIT_IS_SET(XHC, Offset, Bit) \\r
	72	(XHC_BIT_IS_SET(XhcPeiReadOpReg ((XHC), (Offset)), (Bit)))\r
	73	\r
	74	#define USB_DESC_TYPE_HUB 0x29\r
	75	#define USB_DESC_TYPE_HUB_SUPER_SPEED 0x2a\r
	76	\r
	77	//\r
	78	// The RequestType in EFI_USB_DEVICE_REQUEST is composed of\r
	79	// three fields: One bit direction, 2 bit type, and 5 bit\r
	80	// target.\r
	81	//\r
	82	#define USB_REQUEST_TYPE(Dir, Type, Target) \\r
	83	((UINT8)((((Dir) == EfiUsbDataIn ? 0x01 : 0) << 7) \| (Type) \| (Target)))\r
	84	\r
	85	struct _USB_DEV_CONTEXT {\r
	86	//\r
	87	// Whether this entry in UsbDevContext array is used or not.\r
	88	//\r
1436aea4	89	BOOLEAN Enabled;\r
d987459f SZ	90	//\r
	91	// The slot id assigned to the new device through XHCI's Enable_Slot cmd.\r
	92	//\r
1436aea4	93	UINT8 SlotId;\r
d987459f SZ	94	//\r
	95	// The route string presented an attached usb device.\r
	96	//\r
1436aea4	97	USB_DEV_ROUTE RouteString;\r
d987459f SZ	98	//\r
	99	// The route string of parent device if it exists. Otherwise it's zero.\r
	100	//\r
1436aea4	101	USB_DEV_ROUTE ParentRouteString;\r
d987459f SZ	102	//\r
	103	// The actual device address assigned by XHCI through Address_Device command.\r
	104	//\r
1436aea4	105	UINT8 XhciDevAddr;\r
d987459f SZ	106	//\r
	107	// The requested device address from UsbBus driver through Set_Address standard usb request.\r
	108	// As XHCI spec replaces this request with Address_Device command, we have to record the\r
	109	// requested device address and establish a mapping relationship with the actual device address.\r
	110	// Then UsbBus driver just need to be aware of the requested device address to access usb device\r
	111	// through EFI_USB2_HC_PROTOCOL. Xhci driver would be responsible for translating it to actual\r
	112	// device address and access the actual device.\r
	113	//\r
1436aea4	114	UINT8 BusDevAddr;\r
d987459f SZ	115	//\r
	116	// The pointer to the input device context.\r
	117	//\r
1436aea4	118	VOID *InputContext;\r
d987459f SZ	119	//\r
	120	// The pointer to the output device context.\r
	121	//\r
1436aea4	122	VOID *OutputContext;\r
d987459f SZ	123	//\r
	124	// The transfer queue for every endpoint.\r
	125	//\r
1436aea4	126	VOID *EndpointTransferRing[31];\r
d987459f SZ	127	//\r
	128	// The device descriptor which is stored to support XHCI's Evaluate_Context cmd.\r
	129	//\r
1436aea4	130	EFI_USB_DEVICE_DESCRIPTOR DevDesc;\r
d987459f SZ	131	//\r
	132	// As a usb device may include multiple configuration descriptors, we dynamically allocate an array\r
	133	// to store them.\r
	134	// Note that every configuration descriptor stored here includes those lower level descriptors,\r
	135	// such as Interface descriptor, Endpoint descriptor, and so on.\r
	136	// These information is used to support XHCI's Config_Endpoint cmd.\r
	137	//\r
1436aea4	138	EFI_USB_CONFIG_DESCRIPTOR **ConfDesc;\r
d987459f SZ	139	};\r
d987459f SZ	140	\r
1436aea4	141	#define USB_XHC_DEV_SIGNATURE SIGNATURE_32 ('x', 'h', 'c', 'i')\r
d987459f SZ	142	\r
d987459f SZ	143	struct _PEI_XHC_DEV {\r
1436aea4 MK	144	UINTN Signature;\r
	145	PEI_USB2_HOST_CONTROLLER_PPI Usb2HostControllerPpi;\r
	146	EFI_PEI_PPI_DESCRIPTOR PpiDescriptor;\r
	147	UINT32 UsbHostControllerBaseAddress;\r
	148	USBHC_MEM_POOL *MemPool;\r
d987459f	149	\r
b575ca32 JY	150	//\r
	151	// EndOfPei callback is used to stop the XHC DMA operation\r
	152	// after exit PEI phase.\r
	153	//\r
1436aea4	154	EFI_PEI_NOTIFY_DESCRIPTOR EndOfPeiNotifyList;\r
b575ca32	155	\r
d987459f SZ	156	//\r
	157	// XHCI configuration data\r
	158	//\r
1436aea4 MK	159	UINT8 CapLength; ///< Capability Register Length\r
	160	XHC_HCSPARAMS1 HcSParams1; ///< Structural Parameters 1\r
	161	XHC_HCSPARAMS2 HcSParams2; ///< Structural Parameters 2\r
	162	XHC_HCCPARAMS HcCParams; ///< Capability Parameters\r
	163	UINT32 DBOff; ///< Doorbell Offset\r
	164	UINT32 RTSOff; ///< Runtime Register Space Offset\r
	165	UINT32 PageSize;\r
	166	UINT32 MaxScratchpadBufs;\r
	167	UINT64 *ScratchBuf;\r
	168	VOID *ScratchMap;\r
	169	UINT64 *ScratchEntry;\r
	170	UINTN *ScratchEntryMap;\r
	171	UINT64 *DCBAA;\r
	172	UINT32 MaxSlotsEn;\r
d987459f SZ	173	//\r
	174	// Cmd Transfer Ring\r
	175	//\r
1436aea4	176	TRANSFER_RING CmdRing;\r
d987459f SZ	177	//\r
	178	// EventRing\r
	179	//\r
1436aea4	180	EVENT_RING EventRing;\r
d987459f SZ	181	\r
	182	//\r
	183	// Store device contexts managed by XHCI device\r
	184	// The array supports up to 255 devices, entry 0 is reserved and should not be used.\r
	185	//\r
1436aea4	186	USB_DEV_CONTEXT UsbDevContext[256];\r
d987459f SZ	187	};\r
d987459f SZ	188	\r
1436aea4 MK	189	#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS(a) CR (a, PEI_XHC_DEV, Usb2HostControllerPpi, USB_XHC_DEV_SIGNATURE)\r
1436aea4 MK	190	#define PEI_RECOVERY_USB_XHC_DEV_FROM_THIS_NOTIFY(a) CR (a, PEI_XHC_DEV, EndOfPeiNotifyList, USB_XHC_DEV_SIGNATURE)\r
d987459f SZ	191	\r
	192	/**\r
	193	Initialize the memory management pool for the host controller.\r
	194	\r
	195	@return Pointer to the allocated memory pool or NULL if failed.\r
	196	\r
	197	**/\r
	198	USBHC_MEM_POOL *\r
	199	UsbHcInitMemPool (\r
	200	VOID\r
	201	)\r
	202	;\r
	203	\r
	204	/**\r
	205	Release the memory management pool.\r
	206	\r
	207	@param Pool The USB memory pool to free.\r
	208	\r
	209	**/\r
	210	VOID\r
	211	UsbHcFreeMemPool (\r
1436aea4	212	IN USBHC_MEM_POOL *Pool\r
d987459f SZ	213	)\r
	214	;\r
	215	\r
	216	/**\r
	217	Allocate some memory from the host controller's memory pool\r
	218	which can be used to communicate with host controller.\r
	219	\r
	220	@param Pool The host controller's memory pool.\r
	221	@param Size Size of the memory to allocate.\r
	222	\r
	223	@return The allocated memory or NULL.\r
	224	\r
	225	**/\r
	226	VOID *\r
	227	UsbHcAllocateMem (\r
1436aea4 MK	228	IN USBHC_MEM_POOL *Pool,\r
1436aea4 MK	229	IN UINTN Size\r
d987459f SZ	230	)\r
	231	;\r
	232	\r
	233	/**\r
	234	Free the allocated memory back to the memory pool.\r
	235	\r
	236	@param Pool The memory pool of the host controller.\r
	237	@param Mem The memory to free.\r
	238	@param Size The size of the memory to free.\r
	239	\r
	240	**/\r
	241	VOID\r
	242	UsbHcFreeMem (\r
1436aea4 MK	243	IN USBHC_MEM_POOL *Pool,\r
	244	IN VOID *Mem,\r
	245	IN UINTN Size\r
d987459f SZ	246	)\r
	247	;\r
	248	\r
b575ca32 JY	249	/**\r
	250	Initialize IOMMU.\r
	251	**/\r
	252	VOID\r
	253	IoMmuInit (\r
	254	VOID\r
	255	);\r
	256	\r
	257	/**\r
	258	Provides the controller-specific addresses required to access system memory from a\r
	259	DMA bus master.\r
	260	\r
	261	@param Operation Indicates if the bus master is going to read or write to system memory.\r
	262	@param HostAddress The system memory address to map to the PCI controller.\r
	263	@param NumberOfBytes On input the number of bytes to map. On output the number of bytes\r
	264	that were mapped.\r
	265	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	266	access the hosts HostAddress.\r
	267	@param Mapping A resulting value to pass to Unmap().\r
	268	\r
	269	@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.\r
	270	@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.\r
	271	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	272	@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.\r
	273	@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.\r
	274	\r
	275	**/\r
	276	EFI_STATUS\r
	277	IoMmuMap (\r
1436aea4 MK	278	IN EDKII_IOMMU_OPERATION Operation,\r
	279	IN VOID *HostAddress,\r
	280	IN OUT UINTN *NumberOfBytes,\r
	281	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	282	OUT VOID **Mapping\r
b575ca32 JY	283	);\r
	284	\r
	285	/**\r
	286	Completes the Map() operation and releases any corresponding resources.\r
	287	\r
	288	@param Mapping The mapping value returned from Map().\r
	289	\r
	290	@retval EFI_SUCCESS The range was unmapped.\r
	291	@retval EFI_INVALID_PARAMETER Mapping is not a value that was returned by Map().\r
	292	@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.\r
	293	**/\r
	294	EFI_STATUS\r
	295	IoMmuUnmap (\r
1436aea4	296	IN VOID *Mapping\r
b575ca32 JY	297	);\r
	298	\r
	299	/**\r
	300	Allocates pages that are suitable for an OperationBusMasterCommonBuffer or\r
	301	OperationBusMasterCommonBuffer64 mapping.\r
	302	\r
	303	@param Pages The number of pages to allocate.\r
	304	@param HostAddress A pointer to store the base system memory address of the\r
	305	allocated range.\r
	306	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	307	access the hosts HostAddress.\r
	308	@param Mapping A resulting value to pass to Unmap().\r
	309	\r
	310	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	311	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
	312	MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
	313	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	314	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
	315	\r
	316	**/\r
	317	EFI_STATUS\r
	318	IoMmuAllocateBuffer (\r
	319	IN UINTN Pages,\r
	320	OUT VOID **HostAddress,\r
	321	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	322	OUT VOID **Mapping\r
	323	);\r
	324	\r
	325	/**\r
	326	Frees memory that was allocated with AllocateBuffer().\r
	327	\r
	328	@param Pages The number of pages to free.\r
	329	@param HostAddress The base system memory address of the allocated range.\r
	330	@param Mapping The mapping value returned from Map().\r
	331	\r
	332	@retval EFI_SUCCESS The requested memory pages were freed.\r
	333	@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages\r
	334	was not allocated with AllocateBuffer().\r
	335	\r
	336	**/\r
	337	EFI_STATUS\r
	338	IoMmuFreeBuffer (\r
1436aea4 MK	339	IN UINTN Pages,\r
	340	IN VOID *HostAddress,\r
	341	IN VOID *Mapping\r
b575ca32 JY	342	);\r
b575ca32 JY	343	\r
2bbbdeee AS	344	/**\r
	345	Allocates aligned pages that are suitable for an OperationBusMasterCommonBuffer or\r
	346	OperationBusMasterCommonBuffer64 mapping.\r
	347	\r
	348	@param Pages The number of pages to allocate.\r
	349	@param Alignment The requested alignment of the allocation. Must be a power of two.\r
	350	@param HostAddress A pointer to store the base system memory address of the\r
	351	allocated range.\r
	352	@param DeviceAddress The resulting map address for the bus master PCI controller to use to\r
	353	access the hosts HostAddress.\r
	354	@param Mapping A resulting value to pass to Unmap().\r
	355	\r
	356	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	357	@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are\r
	358	MEMORY_WRITE_COMBINE and MEMORY_CACHED.\r
	359	@retval EFI_INVALID_PARAMETER One or more parameters are invalid.\r
	360	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
	361	\r
	362	**/\r
	363	EFI_STATUS\r
	364	IoMmuAllocateAlignedBuffer (\r
	365	IN UINTN Pages,\r
	366	IN UINTN Alignment,\r
	367	OUT VOID **HostAddress,\r
	368	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	369	OUT VOID **Mapping\r
	370	);\r
	371	\r
d987459f	372	#endif\r