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bd86cb02 | 1 | /** @file\r |
9095d37b | 2 | GUID used for MemoryOverwriteRequestControl UEFI variable defined in\r |
bd86cb02 LG |
3 | TCG Platform Reset Attack Mitigation Specification 1.00.\r |
4 | See http://trustedcomputinggroup.org for the latest specification\r | |
5 | \r | |
9095d37b LG |
6 | The purpose of the MemoryOverwriteRequestControl UEFI variable is to give users (e.g., OS, loader) the ability to\r |
7 | indicate to the platform that secrets are present in memory and that the platform firmware must clear memory upon\r | |
8 | a restart. The OS loader should not create the variable. Rather, the firmware is required to create it.\r | |
bd86cb02 | 9 | \r |
9095d37b | 10 | Copyright (c) 2009 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
bd86cb02 LG |
12 | \r |
13 | **/\r | |
14 | \r | |
15 | #ifndef _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_\r | |
16 | #define _MEMORY_OVERWRITE_CONTROL_DATA_GUID_H_\r | |
17 | \r | |
18 | #define MEMORY_ONLY_RESET_CONTROL_GUID \\r | |
19 | { \\r | |
20 | 0xe20939be, 0x32d4, 0x41be, {0xa1, 0x50, 0x89, 0x7f, 0x85, 0xd4, 0x98, 0x29} \\r | |
21 | }\r | |
22 | \r | |
23 | ///\r | |
9095d37b LG |
24 | /// Variable name is "MemoryOverwriteRequestControl" and it is a 1 byte unsigned value.\r |
25 | /// The attributes should be:\r | |
26 | /// EFI_VARIABLE_NON_VOLATILE |\r | |
27 | /// EFI_VARIABLE_BOOTSERVICE_ACCESS |\r | |
28 | /// EFI_VARIABLE_RUNTIME_ACCESS\r | |
bd86cb02 | 29 | ///\r |
2f88bd3a | 30 | #define MEMORY_OVERWRITE_REQUEST_VARIABLE_NAME L"MemoryOverwriteRequestControl"\r |
bd86cb02 LG |
31 | \r |
32 | ///\r | |
8b1943a8 | 33 | /// 0 = Firmware MUST clear the MOR bit\r |
9095d37b | 34 | /// 1 = Firmware MUST set the MOR bit\r |
bd86cb02 | 35 | ///\r |
2f88bd3a | 36 | #define MOR_CLEAR_MEMORY_BIT_MASK 0x01\r |
bd86cb02 LG |
37 | \r |
38 | ///\r | |
39 | /// 0 = Firmware MAY autodetect a clean shutdown of the Static RTM OS.\r | |
40 | /// 1 = Firmware MUST NOT autodetect a clean shutdown of the Static RTM OS.\r | |
41 | ///\r | |
2f88bd3a | 42 | #define MOR_DISABLEAUTODETECT_BIT_MASK 0x10\r |
bd86cb02 LG |
43 | \r |
44 | ///\r | |
45 | /// MOR field bit offset\r | |
46 | ///\r | |
2f88bd3a MK |
47 | #define MOR_CLEAR_MEMORY_BIT_OFFSET 0\r |
48 | #define MOR_DISABLEAUTODETECT_BIT_OFFSET 4\r | |
bd86cb02 LG |
49 | \r |
50 | /**\r | |
51 | Return the ClearMemory bit value 0 or 1.\r | |
52 | \r | |
53 | @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.\r | |
54 | \r | |
55 | @return ClearMemory bit value\r | |
56 | **/\r | |
2f88bd3a | 57 | #define MOR_CLEAR_MEMORY_VALUE(mor) (((UINT8)(mor) & MOR_CLEAR_MEMORY_BIT_MASK) >> MOR_CLEAR_MEMORY_BIT_OFFSET)\r |
bd86cb02 LG |
58 | \r |
59 | /**\r | |
60 | Return the DisableAutoDetect bit value 0 or 1.\r | |
61 | \r | |
62 | @param mor 1 byte value that contains ClearMemory and DisableAutoDetect bit.\r | |
63 | \r | |
64 | @return DisableAutoDetect bit value\r | |
65 | **/\r | |
2f88bd3a | 66 | #define MOR_DISABLE_AUTO_DETECT_VALUE(mor) (((UINT8)(mor) & MOR_DISABLEAUTODETECT_BIT_MASK) >> MOR_DISABLEAUTODETECT_BIT_OFFSET)\r |
bd86cb02 | 67 | \r |
2f88bd3a | 68 | extern EFI_GUID gEfiMemoryOverwriteControlDataGuid;\r |
bd86cb02 LG |
69 | \r |
70 | #endif\r |