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c25f146d
JA		 1/** @file\r
2 CXL 1.1 Register definitions\r
3\r
4 This file contains the register definitions based on the Compute Express Link\r
5 (CXL) Specification Revision 1.1.\r
6\r
7Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
8SPDX-License-Identifier: BSD-2-Clause-Patent\r
9\r
10**/\r
11\r
12#ifndef _CXL11_H_\r
13#define _CXL11_H_\r
14\r
15#include <IndustryStandard/Pci.h>\r
16//\r
17// DVSEC Vendor ID\r
18// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1 - Table 58\r
19// (subject to change as per CXL assigned Vendor ID)\r
20//\r
2f88bd3a 21#define INTEL_CXL_DVSEC_VENDOR_ID 0x8086\r
c25f146d
JA		 22\r
23//\r
24// CXL Flex Bus Device default device and function number\r
25// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1\r
26//\r
2f88bd3a
MK		 27#define CXL_DEV_DEV 0\r
28#define CXL_DEV_FUNC 0\r
c25f146d
JA		 29\r
30//\r
31// Ensure proper structure formats\r
32//\r
33#pragma pack(1)\r
34\r
29d59baa
MK		 35/**\r
36 Macro used to verify the size of a data type at compile time and trigger a\r
37 STATIC_ASSERT() with an error message if the size of the data type does not\r
38 match the expected size.\r
39\r
40 @param TypeName Type name of data type to verify.\r
41 @param ExpectedSize The expected size, in bytes, of the data type specified\r
42 by TypeName.\r
43**/\r
44#define CXL_11_SIZE_ASSERT(TypeName, ExpectedSize) \\r
45 STATIC_ASSERT ( \\r
46 sizeof (TypeName) == ExpectedSize, \\r
47 "Size of " #TypeName \\r
48 " does not meet CXL 1.1 Specification requirements." \\r
49 )\r
50\r
51/**\r
52 Macro used to verify the offset of a field in a data type at compile time and\r
53 trigger a STATIC_ASSERT() with an error message if the offset of the field in\r
54 the data type does not match the expected offset.\r
55\r
56 @param TypeName Type name of data type to verify.\r
57 @param FieldName Field name in the data type specified by TypeName to\r
58 verify.\r
59 @param ExpectedOffset The expected offset, in bytes, of the field specified\r
60 by TypeName and FieldName.\r
61**/\r
62#define CXL_11_OFFSET_ASSERT(TypeName, FieldName, ExpectedOffset) \\r
63 STATIC_ASSERT ( \\r
64 OFFSET_OF (TypeName, FieldName) == ExpectedOffset, \\r
65 "Offset of " #TypeName "." #FieldName \\r
66 " does not meet CXL 1.1 Specification requirements." \\r
67 )\r
68\r
c25f146d
JA		 69///\r
70/// The PCIe DVSEC for Flex Bus Device\r
71///@{\r
72typedef union {\r
73 struct {\r
2f88bd3a
MK		 74 UINT16 CacheCapable : 1; // bit 0\r
75 UINT16 IoCapable : 1; // bit 1\r
76 UINT16 MemCapable : 1; // bit 2\r
77 UINT16 MemHwInitMode : 1; // bit 3\r
78 UINT16 HdmCount : 2; // bit 4..5\r
79 UINT16 Reserved1 : 8; // bit 6..13\r
80 UINT16 ViralCapable : 1; // bit 14\r
81 UINT16 Reserved2 : 1; // bit 15\r
c25f146d 82 } Bits;\r
2f88bd3a 83 UINT16 Uint16;\r
c25f146d
JA		 84} CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY;\r
85\r
86typedef union {\r
87 struct {\r
2f88bd3a
MK		 88 UINT16 CacheEnable : 1; // bit 0\r
89 UINT16 IoEnable : 1; // bit 1\r
90 UINT16 MemEnable : 1; // bit 2\r
91 UINT16 CacheSfCoverage : 5; // bit 3..7\r
92 UINT16 CacheSfGranularity : 3; // bit 8..10\r
93 UINT16 CacheCleanEviction : 1; // bit 11\r
94 UINT16 Reserved1 : 2; // bit 12..13\r
95 UINT16 ViralEnable : 1; // bit 14\r
96 UINT16 Reserved2 : 1; // bit 15\r
c25f146d 97 } Bits;\r
2f88bd3a 98 UINT16 Uint16;\r
c25f146d
JA		 99} CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL;\r
100\r
101typedef union {\r
102 struct {\r
2f88bd3a
MK		 103 UINT16 Reserved1 : 14; // bit 0..13\r
104 UINT16 ViralStatus : 1; // bit 14\r
105 UINT16 Reserved2 : 1; // bit 15\r
c25f146d 106 } Bits;\r
2f88bd3a 107 UINT16 Uint16;\r
c25f146d
JA		 108} CXL_DVSEC_FLEX_BUS_DEVICE_STATUS;\r
109\r
110typedef union {\r
111 struct {\r
2f88bd3a
MK		 112 UINT16 Reserved1 : 1; // bit 0\r
113 UINT16 Reserved2 : 1; // bit 1\r
114 UINT16 Reserved3 : 1; // bit 2\r
115 UINT16 Reserved4 : 13; // bit 3..15\r
c25f146d 116 } Bits;\r
2f88bd3a 117 UINT16 Uint16;\r
c25f146d
JA		 118} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2;\r
119\r
120typedef union {\r
121 struct {\r
2f88bd3a
MK		 122 UINT16 Reserved1 : 1; // bit 0\r
123 UINT16 Reserved2 : 1; // bit 1\r
124 UINT16 Reserved3 : 14; // bit 2..15\r
c25f146d 125 } Bits;\r
2f88bd3a 126 UINT16 Uint16;\r
c25f146d
JA		 127} CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2;\r
128\r
129typedef union {\r
130 struct {\r
2f88bd3a
MK		 131 UINT16 ConfigLock : 1; // bit 0\r
132 UINT16 Reserved1 : 15; // bit 1..15\r
c25f146d 133 } Bits;\r
2f88bd3a 134 UINT16 Uint16;\r
c25f146d
JA		 135} CXL_DVSEC_FLEX_BUS_DEVICE_LOCK;\r
136\r
137typedef union {\r
138 struct {\r
2f88bd3a 139 UINT32 MemorySizeHigh : 32; // bit 0..31\r
c25f146d 140 } Bits;\r
2f88bd3a 141 UINT32 Uint32;\r
c25f146d
JA		 142} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH;\r
143\r
144typedef union {\r
145 struct {\r
2f88bd3a
MK		 146 UINT32 MemoryInfoValid : 1; // bit 0\r
147 UINT32 MemoryActive : 1; // bit 1\r
148 UINT32 MediaType : 3; // bit 2..4\r
149 UINT32 MemoryClass : 3; // bit 5..7\r
150 UINT32 DesiredInterleave : 3; // bit 8..10\r
151 UINT32 Reserved : 17; // bit 11..27\r
152 UINT32 MemorySizeLow : 4; // bit 28..31\r
c25f146d 153 } Bits;\r
2f88bd3a 154 UINT32 Uint32;\r
c25f146d
JA		 155} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW;\r
156\r
157typedef union {\r
158 struct {\r
2f88bd3a 159 UINT32 MemoryBaseHigh : 32; // bit 0..31\r
c25f146d 160 } Bits;\r
2f88bd3a 161 UINT32 Uint32;\r
c25f146d
JA		 162} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH;\r
163\r
164typedef union {\r
165 struct {\r
2f88bd3a
MK		 166 UINT32 Reserved : 28; // bit 0..27\r
167 UINT32 MemoryBaseLow : 4; // bit 28..31\r
c25f146d 168 } Bits;\r
2f88bd3a 169 UINT32 Uint32;\r
c25f146d
JA		 170} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW;\r
171\r
c25f146d
JA		 172typedef union {\r
173 struct {\r
2f88bd3a 174 UINT32 MemorySizeHigh : 32; // bit 0..31\r
c25f146d 175 } Bits;\r
2f88bd3a 176 UINT32 Uint32;\r
c25f146d
JA		 177} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH;\r
178\r
179typedef union {\r
180 struct {\r
2f88bd3a
MK		 181 UINT32 MemoryInfoValid : 1; // bit 0\r
182 UINT32 MemoryActive : 1; // bit 1\r
183 UINT32 MediaType : 3; // bit 2..4\r
184 UINT32 MemoryClass : 3; // bit 5..7\r
185 UINT32 DesiredInterleave : 3; // bit 8..10\r
186 UINT32 Reserved : 17; // bit 11..27\r
187 UINT32 MemorySizeLow : 4; // bit 28..31\r
c25f146d 188 } Bits;\r
2f88bd3a 189 UINT32 Uint32;\r
c25f146d
JA		 190} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW;\r
191\r
192typedef union {\r
193 struct {\r
2f88bd3a 194 UINT32 MemoryBaseHigh : 32; // bit 0..31\r
c25f146d 195 } Bits;\r
2f88bd3a 196 UINT32 Uint32;\r
c25f146d
JA		 197} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH;\r
198\r
199typedef union {\r
200 struct {\r
2f88bd3a
MK		 201 UINT32 Reserved : 28; // bit 0..27\r
202 UINT32 MemoryBaseLow : 4; // bit 28..31\r
c25f146d 203 } Bits;\r
2f88bd3a 204 UINT32 Uint32;\r
c25f146d
JA		 205} CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW;\r
206\r
207//\r
208// Flex Bus Device DVSEC ID\r
209// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Table 58\r
210//\r
2f88bd3a 211#define FLEX_BUS_DEVICE_DVSEC_ID 0\r
c25f146d
JA		 212\r
213//\r
214// PCIe DVSEC for Flex Bus Device\r
215// Compute Express Link Specification Revision: 1.1 - Chapter 7.1.1, Figure 95\r
216//\r
217typedef struct {\r
2f88bd3a
MK		 218 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
219 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
220 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
221 CXL_DVSEC_FLEX_BUS_DEVICE_CAPABILITY DeviceCapability; // offset 10\r
222 CXL_DVSEC_FLEX_BUS_DEVICE_CONTROL DeviceControl; // offset 12\r
223 CXL_DVSEC_FLEX_BUS_DEVICE_STATUS DeviceStatus; // offset 14\r
224 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_CONTROL2 DeviceControl2; // offset 16\r
225 CXL_1_1_DVSEC_FLEX_BUS_DEVICE_STATUS2 DeviceStatus2; // offset 18\r
226 CXL_DVSEC_FLEX_BUS_DEVICE_LOCK DeviceLock; // offset 20\r
227 UINT16 Reserved; // offset 22\r
228 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_HIGH DeviceRange1SizeHigh; // offset 24\r
229 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_SIZE_LOW DeviceRange1SizeLow; // offset 28\r
230 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_HIGH DeviceRange1BaseHigh; // offset 32\r
231 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE1_BASE_LOW DeviceRange1BaseLow; // offset 36\r
232 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_HIGH DeviceRange2SizeHigh; // offset 40\r
233 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_SIZE_LOW DeviceRange2SizeLow; // offset 44\r
234 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_HIGH DeviceRange2BaseHigh; // offset 48\r
235 CXL_DVSEC_FLEX_BUS_DEVICE_RANGE2_BASE_LOW DeviceRange2BaseLow; // offset 52\r
c25f146d 236} CXL_1_1_DVSEC_FLEX_BUS_DEVICE;\r
29d59baa 237\r
2f88bd3a 238CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, Header, 0x00);\r
29d59baa
MK		 239CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader1, 0x04);\r
240CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DesignatedVendorSpecificHeader2, 0x08);\r
2f88bd3a
MK		 241CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceCapability, 0x0A);\r
242CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl, 0x0C);\r
243CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus, 0x0E);\r
244CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceControl2, 0x10);\r
245CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceStatus2, 0x12);\r
246CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceLock, 0x14);\r
247CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeHigh, 0x18);\r
248CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1SizeLow, 0x1C);\r
249CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseHigh, 0x20);\r
250CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange1BaseLow, 0x24);\r
251CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeHigh, 0x28);\r
252CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2SizeLow, 0x2C);\r
253CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseHigh, 0x30);\r
254CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, DeviceRange2BaseLow, 0x34);\r
255CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_DEVICE, 0x38);\r
c25f146d
JA		 256///@}\r
257\r
258///\r
259/// PCIe DVSEC for FLex Bus Port\r
260///@{\r
261typedef union {\r
262 struct {\r
2f88bd3a
MK		 263 UINT16 CacheCapable : 1; // bit 0\r
264 UINT16 IoCapable : 1; // bit 1\r
265 UINT16 MemCapable : 1; // bit 2\r
266 UINT16 Reserved : 13; // bit 3..15\r
c25f146d 267 } Bits;\r
2f88bd3a 268 UINT16 Uint16;\r
c25f146d
JA		 269} CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY;\r
270\r
271typedef union {\r
272 struct {\r
2f88bd3a
MK		 273 UINT16 CacheEnable : 1; // bit 0\r
274 UINT16 IoEnable : 1; // bit 1\r
275 UINT16 MemEnable : 1; // bit 2\r
276 UINT16 CxlSyncBypassEnable : 1; // bit 3\r
277 UINT16 DriftBufferEnable : 1; // bit 4\r
278 UINT16 Reserved : 3; // bit 5..7\r
279 UINT16 Retimer1Present : 1; // bit 8\r
280 UINT16 Retimer2Present : 1; // bit 9\r
281 UINT16 Reserved2 : 6; // bit 10..15\r
c25f146d 282 } Bits;\r
2f88bd3a 283 UINT16 Uint16;\r
c25f146d
JA		 284} CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL;\r
285\r
286typedef union {\r
287 struct {\r
2f88bd3a
MK		 288 UINT16 CacheEnable : 1; // bit 0\r
289 UINT16 IoEnable : 1; // bit 1\r
290 UINT16 MemEnable : 1; // bit 2\r
291 UINT16 CxlSyncBypassEnable : 1; // bit 3\r
292 UINT16 DriftBufferEnable : 1; // bit 4\r
293 UINT16 Reserved : 3; // bit 5..7\r
294 UINT16 CxlCorrectableProtocolIdFramingError : 1; // bit 8\r
295 UINT16 CxlUncorrectableProtocolIdFramingError : 1; // bit 9\r
296 UINT16 CxlUnexpectedProtocolIdDropped : 1; // bit 10\r
297 UINT16 Reserved2 : 5; // bit 11..15\r
c25f146d 298 } Bits;\r
2f88bd3a 299 UINT16 Uint16;\r
c25f146d
JA		 300} CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS;\r
301\r
302//\r
303// Flex Bus Port DVSEC ID\r
304// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Table 62\r
305//\r
2f88bd3a 306#define FLEX_BUS_PORT_DVSEC_ID 7\r
c25f146d
JA		 307\r
308//\r
309// PCIe DVSEC for Flex Bus Port\r
310// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.3, Figure 99\r
311//\r
312typedef struct {\r
2f88bd3a
MK		 313 PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; // offset 0\r
314 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_1 DesignatedVendorSpecificHeader1; // offset 4\r
315 PCI_EXPRESS_DESIGNATED_VENDOR_SPECIFIC_HEADER_2 DesignatedVendorSpecificHeader2; // offset 8\r
316 CXL_1_1_DVSEC_FLEX_BUS_PORT_CAPABILITY PortCapability; // offset 10\r
317 CXL_1_1_DVSEC_FLEX_BUS_PORT_CONTROL PortControl; // offset 12\r
318 CXL_1_1_DVSEC_FLEX_BUS_PORT_STATUS PortStatus; // offset 14\r
c25f146d 319} CXL_1_1_DVSEC_FLEX_BUS_PORT;\r
29d59baa 320\r
2f88bd3a 321CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, Header, 0x00);\r
29d59baa
MK		 322CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader1, 0x04);\r
323CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, DesignatedVendorSpecificHeader2, 0x08);\r
2f88bd3a
MK		 324CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortCapability, 0x0A);\r
325CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortControl, 0x0C);\r
326CXL_11_OFFSET_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, PortStatus, 0x0E);\r
327CXL_11_SIZE_ASSERT (CXL_1_1_DVSEC_FLEX_BUS_PORT, 0x10);\r
c25f146d
JA		 328///@}\r
329\r
330///\r
331/// CXL 1.1 Upstream and Downstream Port Subsystem Component registers\r
332///\r
333\r
334/// The CXL.Cache and CXL.Memory Architectural register definitions\r
335/// Based on chapter 7.2.2 of Compute Express Link Specification Revision: 1.1\r
336///@{\r
337\r
2f88bd3a 338#define CXL_CAPABILITY_HEADER_OFFSET 0\r
c25f146d
JA		 339typedef union {\r
340 struct {\r
2f88bd3a
MK		 341 UINT32 CxlCapabilityId : 16; // bit 0..15\r
342 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
343 UINT32 CxlCacheMemVersion : 4; // bit 20..23\r
344 UINT32 ArraySize : 8; // bit 24..31\r
c25f146d 345 } Bits;\r
2f88bd3a 346 UINT32 Uint32;\r
c25f146d
JA		 347} CXL_CAPABILITY_HEADER;\r
348\r
2f88bd3a 349#define CXL_RAS_CAPABILITY_HEADER_OFFSET 4\r
c25f146d
JA		 350typedef union {\r
351 struct {\r
2f88bd3a
MK		 352 UINT32 CxlCapabilityId : 16; // bit 0..15\r
353 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
354 UINT32 CxlRasCapabilityPointer : 12; // bit 20..31\r
c25f146d 355 } Bits;\r
2f88bd3a 356 UINT32 Uint32;\r
c25f146d
JA		 357} CXL_RAS_CAPABILITY_HEADER;\r
358\r
2f88bd3a 359#define CXL_SECURITY_CAPABILITY_HEADER_OFFSET 8\r
c25f146d
JA		 360typedef union {\r
361 struct {\r
2f88bd3a
MK		 362 UINT32 CxlCapabilityId : 16; // bit 0..15\r
363 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
364 UINT32 CxlSecurityCapabilityPointer : 12; // bit 20..31\r
c25f146d 365 } Bits;\r
2f88bd3a 366 UINT32 Uint32;\r
c25f146d
JA		 367} CXL_SECURITY_CAPABILITY_HEADER;\r
368\r
2f88bd3a 369#define CXL_LINK_CAPABILITY_HEADER_OFFSET 0xC\r
c25f146d
JA		 370typedef union {\r
371 struct {\r
2f88bd3a
MK		 372 UINT32 CxlCapabilityId : 16; // bit 0..15\r
373 UINT32 CxlCapabilityVersion : 4; // bit 16..19\r
374 UINT32 CxlLinkCapabilityPointer : 12; // bit 20..31\r
c25f146d 375 } Bits;\r
2f88bd3a 376 UINT32 Uint32;\r
c25f146d
JA		 377} CXL_LINK_CAPABILITY_HEADER;\r
378\r
379typedef union {\r
380 struct {\r
2f88bd3a
MK		 381 UINT32 CacheDataParity : 1; // bit 0..0\r
382 UINT32 CacheAddressParity : 1; // bit 1..1\r
383 UINT32 CacheByteEnableParity : 1; // bit 2..2\r
384 UINT32 CacheDataEcc : 1; // bit 3..3\r
385 UINT32 MemDataParity : 1; // bit 4..4\r
386 UINT32 MemAddressParity : 1; // bit 5..5\r
387 UINT32 MemByteEnableParity : 1; // bit 6..6\r
388 UINT32 MemDataEcc : 1; // bit 7..7\r
389 UINT32 ReInitThreshold : 1; // bit 8..8\r
390 UINT32 RsvdEncodingViolation : 1; // bit 9..9\r
391 UINT32 PoisonReceived : 1; // bit 10..10\r
392 UINT32 ReceiverOverflow : 1; // bit 11..11\r
393 UINT32 Reserved : 20; // bit 12..31\r
c25f146d 394 } Bits;\r
2f88bd3a 395 UINT32 Uint32;\r
c25f146d
JA		 396} CXL_1_1_UNCORRECTABLE_ERROR_STATUS;\r
397\r
398typedef union {\r
399 struct {\r
2f88bd3a
MK		 400 UINT32 CacheDataParityMask : 1; // bit 0..0\r
401 UINT32 CacheAddressParityMask : 1; // bit 1..1\r
402 UINT32 CacheByteEnableParityMask : 1; // bit 2..2\r
403 UINT32 CacheDataEccMask : 1; // bit 3..3\r
404 UINT32 MemDataParityMask : 1; // bit 4..4\r
405 UINT32 MemAddressParityMask : 1; // bit 5..5\r
406 UINT32 MemByteEnableParityMask : 1; // bit 6..6\r
407 UINT32 MemDataEccMask : 1; // bit 7..7\r
408 UINT32 ReInitThresholdMask : 1; // bit 8..8\r
409 UINT32 RsvdEncodingViolationMask : 1; // bit 9..9\r
410 UINT32 PoisonReceivedMask : 1; // bit 10..10\r
411 UINT32 ReceiverOverflowMask : 1; // bit 11..11\r
412 UINT32 Reserved : 20; // bit 12..31\r
c25f146d 413 } Bits;\r
2f88bd3a 414 UINT32 Uint32;\r
c25f146d
JA		 415} CXL_1_1_UNCORRECTABLE_ERROR_MASK;\r
416\r
417typedef union {\r
418 struct {\r
2f88bd3a
MK		 419 UINT32 CacheDataParitySeverity : 1; // bit 0..0\r
420 UINT32 CacheAddressParitySeverity : 1; // bit 1..1\r
421 UINT32 CacheByteEnableParitySeverity : 1; // bit 2..2\r
422 UINT32 CacheDataEccSeverity : 1; // bit 3..3\r
423 UINT32 MemDataParitySeverity : 1; // bit 4..4\r
424 UINT32 MemAddressParitySeverity : 1; // bit 5..5\r
425 UINT32 MemByteEnableParitySeverity : 1; // bit 6..6\r
426 UINT32 MemDataEccSeverity : 1; // bit 7..7\r
427 UINT32 ReInitThresholdSeverity : 1; // bit 8..8\r
428 UINT32 RsvdEncodingViolationSeverity : 1; // bit 9..9\r
429 UINT32 PoisonReceivedSeverity : 1; // bit 10..10\r
430 UINT32 ReceiverOverflowSeverity : 1; // bit 11..11\r
431 UINT32 Reserved : 20; // bit 12..31\r
c25f146d 432 } Bits;\r
2f88bd3a 433 UINT32 Uint32;\r
c25f146d
JA		 434} CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY;\r
435\r
436typedef union {\r
437 struct {\r
2f88bd3a
MK		 438 UINT32 CacheDataEcc : 1; // bit 0..0\r
439 UINT32 MemoryDataEcc : 1; // bit 1..1\r
440 UINT32 CrcThreshold : 1; // bit 2..2\r
441 UINT32 RetryThreshold : 1; // bit 3..3\r
442 UINT32 CachePoisonReceived : 1; // bit 4..4\r
443 UINT32 MemoryPoisonReceived : 1; // bit 5..5\r
444 UINT32 PhysicalLayerError : 1; // bit 6..6\r
445 UINT32 Reserved : 25; // bit 7..31\r
c25f146d 446 } Bits;\r
2f88bd3a 447 UINT32 Uint32;\r
c25f146d
JA		 448} CXL_CORRECTABLE_ERROR_STATUS;\r
449\r
450typedef union {\r
451 struct {\r
2f88bd3a
MK		 452 UINT32 CacheDataEccMask : 1; // bit 0..0\r
453 UINT32 MemoryDataEccMask : 1; // bit 1..1\r
454 UINT32 CrcThresholdMask : 1; // bit 2..2\r
455 UINT32 RetryThresholdMask : 1; // bit 3..3\r
456 UINT32 CachePoisonReceivedMask : 1; // bit 4..4\r
457 UINT32 MemoryPoisonReceivedMask : 1; // bit 5..5\r
458 UINT32 PhysicalLayerErrorMask : 1; // bit 6..6\r
459 UINT32 Reserved : 25; // bit 7..31\r
c25f146d 460 } Bits;\r
2f88bd3a 461 UINT32 Uint32;\r
c25f146d
JA		 462} CXL_CORRECTABLE_ERROR_MASK;\r
463\r
464typedef union {\r
465 struct {\r
2f88bd3a
MK		 466 UINT32 FirstErrorPointer : 4; // bit 0..3\r
467 UINT32 Reserved1 : 5; // bit 4..8\r
468 UINT32 MultipleHeaderRecordingCapability : 1; // bit 9..9\r
469 UINT32 Reserved2 : 3; // bit 10..12\r
470 UINT32 PoisonEnabled : 1; // bit 13..13\r
471 UINT32 Reserved3 : 18; // bit 14..31\r
c25f146d 472 } Bits;\r
2f88bd3a 473 UINT32 Uint32;\r
c25f146d
JA		 474} CXL_ERROR_CAPABILITIES_AND_CONTROL;\r
475\r
476typedef struct {\r
2f88bd3a
MK		 477 CXL_1_1_UNCORRECTABLE_ERROR_STATUS UncorrectableErrorStatus;\r
478 CXL_1_1_UNCORRECTABLE_ERROR_MASK UncorrectableErrorMask;\r
479 CXL_1_1_UNCORRECTABLE_ERROR_SEVERITY UncorrectableErrorSeverity;\r
480 CXL_CORRECTABLE_ERROR_STATUS CorrectableErrorStatus;\r
481 CXL_CORRECTABLE_ERROR_MASK CorrectableErrorMask;\r
482 CXL_ERROR_CAPABILITIES_AND_CONTROL ErrorCapabilitiesAndControl;\r
483 UINT32 HeaderLog[16];\r
c25f146d
JA		 484} CXL_1_1_RAS_CAPABILITY_STRUCTURE;\r
485\r
2f88bd3a
MK		 486CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorStatus, 0x00);\r
487CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorMask, 0x04);\r
488CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, UncorrectableErrorSeverity, 0x08);\r
489CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorStatus, 0x0C);\r
490CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, CorrectableErrorMask, 0x10);\r
29d59baa 491CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, ErrorCapabilitiesAndControl, 0x14);\r
2f88bd3a
MK		 492CXL_11_OFFSET_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, HeaderLog, 0x18);\r
493CXL_11_SIZE_ASSERT (CXL_1_1_RAS_CAPABILITY_STRUCTURE, 0x58);\r
29d59baa 494\r
c25f146d
JA		 495typedef union {\r
496 struct {\r
2f88bd3a
MK		 497 UINT32 DeviceTrustLevel : 2; // bit 0..1\r
498 UINT32 Reserved : 30; // bit 2..31\r
c25f146d 499 } Bits;\r
2f88bd3a 500 UINT32 Uint32;\r
c25f146d
JA		 501} CXL_1_1_SECURITY_POLICY;\r
502\r
503typedef struct {\r
2f88bd3a 504 CXL_1_1_SECURITY_POLICY SecurityPolicy;\r
c25f146d
JA		 505} CXL_1_1_SECURITY_CAPABILITY_STRUCTURE;\r
506\r
29d59baa 507CXL_11_OFFSET_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, SecurityPolicy, 0x0);\r
2f88bd3a 508CXL_11_SIZE_ASSERT (CXL_1_1_SECURITY_CAPABILITY_STRUCTURE, 0x4);\r
29d59baa 509\r
c25f146d
JA		 510typedef union {\r
511 struct {\r
2f88bd3a
MK		 512 UINT64 CxlLinkVersionSupported : 4; // bit 0..3\r
513 UINT64 CxlLinkVersionReceived : 4; // bit 4..7\r
514 UINT64 LlrWrapValueSupported : 8; // bit 8..15\r
515 UINT64 LlrWrapValueReceived : 8; // bit 16..23\r
516 UINT64 NumRetryReceived : 5; // bit 24..28\r
517 UINT64 NumPhyReinitReceived : 5; // bit 29..33\r
518 UINT64 WrPtrReceived : 8; // bit 34..41\r
519 UINT64 EchoEseqReceived : 8; // bit 42..49\r
520 UINT64 NumFreeBufReceived : 8; // bit 50..57\r
521 UINT64 Reserved : 6; // bit 58..63\r
c25f146d 522 } Bits;\r
2f88bd3a 523 UINT64 Uint64;\r
c25f146d
JA		 524} CXL_LINK_LAYER_CAPABILITY;\r
525\r
526typedef union {\r
527 struct {\r
2f88bd3a
MK		 528 UINT16 LlReset : 1; // bit 0..0\r
529 UINT16 LlInitStall : 1; // bit 1..1\r
530 UINT16 LlCrdStall : 1; // bit 2..2\r
531 UINT16 InitState : 2; // bit 3..4\r
532 UINT16 LlRetryBufferConsumed : 8; // bit 5..12\r
533 UINT16 Reserved : 3; // bit 13..15\r
c25f146d 534 } Bits;\r
2f88bd3a 535 UINT64 Uint64;\r
c25f146d
JA		 536} CXL_LINK_LAYER_CONTROL_AND_STATUS;\r
537\r
538typedef union {\r
539 struct {\r
2f88bd3a
MK		 540 UINT64 CacheReqCredits : 10; // bit 0..9\r
541 UINT64 CacheRspCredits : 10; // bit 10..19\r
542 UINT64 CacheDataCredits : 10; // bit 20..29\r
543 UINT64 MemReqRspCredits : 10; // bit 30..39\r
544 UINT64 MemDataCredits : 10; // bit 40..49\r
c25f146d 545 } Bits;\r
2f88bd3a 546 UINT64 Uint64;\r
c25f146d
JA		 547} CXL_LINK_LAYER_RX_CREDIT_CONTROL;\r
548\r
549typedef union {\r
550 struct {\r
2f88bd3a
MK		 551 UINT64 CacheReqCredits : 10; // bit 0..9\r
552 UINT64 CacheRspCredits : 10; // bit 10..19\r
553 UINT64 CacheDataCredits : 10; // bit 20..29\r
554 UINT64 MemReqRspCredits : 10; // bit 30..39\r
555 UINT64 MemDataCredits : 10; // bit 40..49\r
c25f146d 556 } Bits;\r
2f88bd3a 557 UINT64 Uint64;\r
c25f146d
JA		 558} CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS;\r
559\r
560typedef union {\r
561 struct {\r
2f88bd3a
MK		 562 UINT64 CacheReqCredits : 10; // bit 0..9\r
563 UINT64 CacheRspCredits : 10; // bit 10..19\r
564 UINT64 CacheDataCredits : 10; // bit 20..29\r
565 UINT64 MemReqRspCredits : 10; // bit 30..39\r
566 UINT64 MemDataCredits : 10; // bit 40..49\r
c25f146d 567 } Bits;\r
2f88bd3a 568 UINT64 Uint64;\r
c25f146d
JA		 569} CXL_LINK_LAYER_TX_CREDIT_STATUS;\r
570\r
571typedef union {\r
572 struct {\r
2f88bd3a
MK		 573 UINT32 AckForceThreshold : 8; // bit 0..7\r
574 UINT32 AckFLushRetimer : 10; // bit 8..17\r
c25f146d 575 } Bits;\r
2f88bd3a 576 UINT64 Uint64;\r
c25f146d
JA		 577} CXL_LINK_LAYER_ACK_TIMER_CONTROL;\r
578\r
579typedef union {\r
580 struct {\r
2f88bd3a
MK		 581 UINT32 MdhDisable : 1; // bit 0..0\r
582 UINT32 Reserved : 31; // bit 1..31\r
c25f146d 583 } Bits;\r
2f88bd3a 584 UINT64 Uint64;\r
c25f146d
JA		 585} CXL_LINK_LAYER_DEFEATURE;\r
586\r
587typedef struct {\r
2f88bd3a
MK		 588 CXL_LINK_LAYER_CAPABILITY LinkLayerCapability;\r
589 CXL_LINK_LAYER_CONTROL_AND_STATUS LinkLayerControlStatus;\r
590 CXL_LINK_LAYER_RX_CREDIT_CONTROL LinkLayerRxCreditControl;\r
591 CXL_LINK_LAYER_RX_CREDIT_RETURN_STATUS LinkLayerRxCreditReturnStatus;\r
592 CXL_LINK_LAYER_TX_CREDIT_STATUS LinkLayerTxCreditStatus;\r
593 CXL_LINK_LAYER_ACK_TIMER_CONTROL LinkLayerAckTimerControl;\r
594 CXL_LINK_LAYER_DEFEATURE LinkLayerDefeature;\r
c25f146d
JA		 595} CXL_1_1_LINK_CAPABILITY_STRUCTURE;\r
596\r
2f88bd3a
MK		 597CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerCapability, 0x00);\r
598CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerControlStatus, 0x08);\r
599CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditControl, 0x10);\r
29d59baa 600CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerRxCreditReturnStatus, 0x18);\r
2f88bd3a
MK		 601CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerTxCreditStatus, 0x20);\r
602CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerAckTimerControl, 0x28);\r
603CXL_11_OFFSET_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, LinkLayerDefeature, 0x30);\r
604CXL_11_SIZE_ASSERT (CXL_1_1_LINK_CAPABILITY_STRUCTURE, 0x38);\r
29d59baa 605\r
2f88bd3a 606#define CXL_IO_ARBITRATION_CONTROL_OFFSET 0x180\r
c25f146d
JA		 607typedef union {\r
608 struct {\r
2f88bd3a
MK		 609 UINT32 Reserved1 : 4; // bit 0..3\r
610 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
611 UINT32 Reserved2 : 24; // bit 8..31\r
c25f146d 612 } Bits;\r
2f88bd3a 613 UINT32 Uint32;\r
c25f146d
JA		 614} CXL_IO_ARBITRATION_CONTROL;\r
615\r
29d59baa
MK		 616CXL_11_SIZE_ASSERT (CXL_IO_ARBITRATION_CONTROL, 0x4);\r
617\r
2f88bd3a 618#define CXL_CACHE_MEMORY_ARBITRATION_CONTROL_OFFSET 0x1C0\r
c25f146d
JA		 619typedef union {\r
620 struct {\r
2f88bd3a
MK		 621 UINT32 Reserved1 : 4; // bit 0..3\r
622 UINT32 WeightedRoundRobinArbitrationWeight : 4; // bit 4..7\r
623 UINT32 Reserved2 : 24; // bit 8..31\r
c25f146d 624 } Bits;\r
2f88bd3a 625 UINT32 Uint32;\r
c25f146d 626} CXL_CACHE_MEMORY_ARBITRATION_CONTROL;\r
29d59baa
MK		 627\r
628CXL_11_SIZE_ASSERT (CXL_CACHE_MEMORY_ARBITRATION_CONTROL, 0x4);\r
629\r
c25f146d
JA		 630///@}\r
631\r
632/// The CXL.RCRB base register definition\r
633/// Based on chapter 7.3 of Compute Express Link Specification Revision: 1.1\r
634///@{\r
635typedef union {\r
636 struct {\r
2f88bd3a
MK		 637 UINT64 RcrbEnable : 1; // bit 0..0\r
638 UINT64 Reserved : 12; // bit 1..12\r
639 UINT64 RcrbBaseAddress : 51; // bit 13..63\r
c25f146d 640 } Bits;\r
2f88bd3a 641 UINT64 Uint64;\r
c25f146d 642} CXL_RCRB_BASE;\r
29d59baa
MK		 643\r
644CXL_11_SIZE_ASSERT (CXL_RCRB_BASE, 0x8);\r
645\r
c25f146d
JA		 646///@}\r
647\r
648#pragma pack()\r
649\r
650//\r
651// CXL Downstream / Upstream Port RCRB space register offsets\r
652// Compute Express Link Specification Revision: 1.1 - Chapter 7.2.1.1 - Figure 97\r
653//\r
2f88bd3a
MK		 654#define CXL_PORT_RCRB_MEMBAR0_LOW_OFFSET 0x010\r
655#define CXL_PORT_RCRB_MEMBAR0_HIGH_OFFSET 0x014\r
656#define CXL_PORT_RCRB_EXTENDED_CAPABILITY_BASE_OFFSET 0x100\r
c25f146d
JA		 657\r
658#endif\r
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