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Commit | Line | Data |
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75ce7ef7 | 1 | /** @file\r |
1e2bf55e | 2 | ACPI IO Remapping Table (IORT) as specified in ARM spec DEN0049D\r |
75ce7ef7 | 3 | \r |
1e2bf55e | 4 | http://infocenter.arm.com/help/topic/com.arm.doc.den0049d/DEN0049D_IO_Remapping_Table.pdf\r |
75ce7ef7 AB |
5 | \r |
6 | Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>\r | |
27e98391 | 7 | Copyright (c) 2018, ARM Limited. All rights reserved.<BR>\r |
75ce7ef7 | 8 | \r |
9344f092 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
75ce7ef7 AB |
10 | **/\r |
11 | \r | |
12 | #ifndef __IO_REMAPPING_TABLE_H__\r | |
13 | #define __IO_REMAPPING_TABLE_H__\r | |
14 | \r | |
15 | #include <IndustryStandard/Acpi.h>\r | |
16 | \r | |
2f88bd3a | 17 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION 0x0\r |
75ce7ef7 | 18 | \r |
2f88bd3a MK |
19 | #define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0\r |
20 | #define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1\r | |
21 | #define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2\r | |
22 | #define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3\r | |
23 | #define EFI_ACPI_IORT_TYPE_SMMUv3 0x4\r | |
24 | #define EFI_ACPI_IORT_TYPE_PMCG 0x5\r | |
75ce7ef7 | 25 | \r |
2f88bd3a | 26 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0\r |
75ce7ef7 | 27 | \r |
2f88bd3a MK |
28 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0\r |
29 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1\r | |
30 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2\r | |
31 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3\r | |
75ce7ef7 | 32 | \r |
2f88bd3a MK |
33 | #define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0\r |
34 | #define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1\r | |
75ce7ef7 AB |
35 | \r |
36 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0\r | |
37 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1\r | |
38 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2\r | |
39 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3\r | |
157fb7bf AB |
40 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4\r |
41 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5\r | |
75ce7ef7 | 42 | \r |
2f88bd3a MK |
43 | #define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0\r |
44 | #define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1\r | |
75ce7ef7 | 45 | \r |
2f88bd3a MK |
46 | #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0\r |
47 | #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1\r | |
75ce7ef7 AB |
48 | \r |
49 | #define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0\r | |
50 | #define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1\r | |
27e98391 SM |
51 | #define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3\r |
52 | \r | |
2f88bd3a MK |
53 | #define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0\r |
54 | #define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1\r | |
55 | #define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2\r | |
75ce7ef7 AB |
56 | \r |
57 | #define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0\r | |
58 | #define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED 0x1\r | |
59 | \r | |
2f88bd3a | 60 | #define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0\r |
75ce7ef7 AB |
61 | \r |
62 | #pragma pack(1)\r | |
63 | \r | |
64 | ///\r | |
65 | /// Table header\r | |
66 | ///\r | |
67 | typedef struct {\r | |
2f88bd3a MK |
68 | EFI_ACPI_DESCRIPTION_HEADER Header;\r |
69 | UINT32 NumNodes;\r | |
70 | UINT32 NodeOffset;\r | |
71 | UINT32 Reserved;\r | |
75ce7ef7 AB |
72 | } EFI_ACPI_6_0_IO_REMAPPING_TABLE;\r |
73 | \r | |
74 | ///\r | |
75 | /// Definition for ID mapping table shared by all node types\r | |
76 | ///\r | |
77 | typedef struct {\r | |
2f88bd3a MK |
78 | UINT32 InputBase;\r |
79 | UINT32 NumIds;\r | |
80 | UINT32 OutputBase;\r | |
81 | UINT32 OutputReference;\r | |
82 | UINT32 Flags;\r | |
75ce7ef7 AB |
83 | } EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;\r |
84 | \r | |
85 | ///\r | |
86 | /// Node header definition shared by all node types\r | |
87 | ///\r | |
88 | typedef struct {\r | |
2f88bd3a MK |
89 | UINT8 Type;\r |
90 | UINT16 Length;\r | |
91 | UINT8 Revision;\r | |
92 | UINT32 Reserved;\r | |
93 | UINT32 NumIdMappings;\r | |
94 | UINT32 IdReference;\r | |
75ce7ef7 AB |
95 | } EFI_ACPI_6_0_IO_REMAPPING_NODE;\r |
96 | \r | |
97 | ///\r | |
98 | /// Node type 0: ITS node\r | |
99 | ///\r | |
100 | typedef struct {\r | |
2f88bd3a | 101 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
75ce7ef7 | 102 | \r |
2f88bd3a MK |
103 | UINT32 NumItsIdentifiers;\r |
104 | // UINT32 ItsIdentifiers[NumItsIdentifiers];\r | |
75ce7ef7 AB |
105 | } EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;\r |
106 | \r | |
107 | ///\r | |
108 | /// Node type 1: root complex node\r | |
109 | ///\r | |
110 | typedef struct {\r | |
2f88bd3a | 111 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
75ce7ef7 | 112 | \r |
2f88bd3a MK |
113 | UINT32 CacheCoherent;\r |
114 | UINT8 AllocationHints;\r | |
115 | UINT16 Reserved;\r | |
116 | UINT8 MemoryAccessFlags;\r | |
75ce7ef7 | 117 | \r |
2f88bd3a MK |
118 | UINT32 AtsAttribute;\r |
119 | UINT32 PciSegmentNumber;\r | |
120 | UINT8 MemoryAddressSize;\r | |
121 | UINT8 Reserved1[3];\r | |
75ce7ef7 AB |
122 | } EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r |
123 | \r | |
124 | ///\r | |
125 | /// Node type 2: named component node\r | |
126 | ///\r | |
127 | typedef struct {\r | |
2f88bd3a MK |
128 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
129 | \r | |
130 | UINT32 Flags;\r | |
131 | UINT32 CacheCoherent;\r | |
132 | UINT8 AllocationHints;\r | |
133 | UINT16 Reserved;\r | |
134 | UINT8 MemoryAccessFlags;\r | |
135 | UINT8 AddressSizeLimit;\r | |
136 | // UINT8 ObjectName[];\r | |
75ce7ef7 AB |
137 | } EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;\r |
138 | \r | |
139 | ///\r | |
140 | /// Node type 3: SMMUv1 or SMMUv2 node\r | |
141 | ///\r | |
142 | typedef struct {\r | |
2f88bd3a MK |
143 | UINT32 Interrupt;\r |
144 | UINT32 InterruptFlags;\r | |
75ce7ef7 AB |
145 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;\r |
146 | \r | |
147 | typedef struct {\r | |
2f88bd3a MK |
148 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
149 | \r | |
150 | UINT64 Base;\r | |
151 | UINT64 Span;\r | |
152 | UINT32 Model;\r | |
153 | UINT32 Flags;\r | |
154 | UINT32 GlobalInterruptArrayRef;\r | |
155 | UINT32 NumContextInterrupts;\r | |
156 | UINT32 ContextInterruptArrayRef;\r | |
157 | UINT32 NumPmuInterrupts;\r | |
158 | UINT32 PmuInterruptArrayRef;\r | |
159 | \r | |
160 | UINT32 SMMU_NSgIrpt;\r | |
161 | UINT32 SMMU_NSgIrptFlags;\r | |
162 | UINT32 SMMU_NSgCfgIrpt;\r | |
163 | UINT32 SMMU_NSgCfgIrptFlags;\r | |
164 | \r | |
165 | // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];\r | |
166 | // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];\r | |
75ce7ef7 AB |
167 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r |
168 | \r | |
169 | ///\r | |
27e98391 | 170 | /// Node type 4: SMMUv3 node\r |
75ce7ef7 AB |
171 | ///\r |
172 | typedef struct {\r | |
2f88bd3a MK |
173 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
174 | \r | |
175 | UINT64 Base;\r | |
176 | UINT32 Flags;\r | |
177 | UINT32 Reserved;\r | |
178 | UINT64 VatosAddress;\r | |
179 | UINT32 Model;\r | |
180 | UINT32 Event;\r | |
181 | UINT32 Pri;\r | |
182 | UINT32 Gerr;\r | |
183 | UINT32 Sync;\r | |
184 | UINT32 ProximityDomain;\r | |
185 | UINT32 DeviceIdMappingIndex;\r | |
75ce7ef7 AB |
186 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r |
187 | \r | |
157fb7bf AB |
188 | ///\r |
189 | /// Node type 5: PMCG node\r | |
190 | ///\r | |
191 | typedef struct {\r | |
2f88bd3a | 192 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
157fb7bf | 193 | \r |
2f88bd3a MK |
194 | UINT64 Base;\r |
195 | UINT32 OverflowInterruptGsiv;\r | |
196 | UINT32 NodeReference;\r | |
197 | UINT64 Page1Base;\r | |
198 | // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];\r | |
157fb7bf AB |
199 | } EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r |
200 | \r | |
75ce7ef7 AB |
201 | #pragma pack()\r |
202 | \r | |
203 | #endif\r |