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75ce7ef7 | 1 | /** @file\r |
4c55f639 | 2 | ACPI IO Remapping Table (IORT) definitions.\r |
75ce7ef7 AB |
3 | \r |
4 | Copyright (c) 2017, Linaro Limited. All rights reserved.<BR>\r | |
4c55f639 | 5 | Copyright (c) 2018 - 2022, Arm Limited. All rights reserved.<BR>\r |
75ce7ef7 | 6 | \r |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
4c55f639 SM |
8 | \r |
9 | @par Reference(s):\r | |
10 | - IO Remapping Table, Platform Design Document, Revision E.d, Feb 2022\r | |
11 | (https://developer.arm.com/documentation/den0049/)\r | |
12 | \r | |
13 | @par Glossary:\r | |
14 | - Ref : Reference\r | |
15 | - Mem : Memory\r | |
16 | - Desc : Descriptor\r | |
75ce7ef7 AB |
17 | **/\r |
18 | \r | |
19 | #ifndef __IO_REMAPPING_TABLE_H__\r | |
20 | #define __IO_REMAPPING_TABLE_H__\r | |
21 | \r | |
22 | #include <IndustryStandard/Acpi.h>\r | |
23 | \r | |
4c55f639 SM |
24 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_00 0x0\r |
25 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_04 0x4 // Deprecated\r | |
26 | #define EFI_ACPI_IO_REMAPPING_TABLE_REVISION_05 0x5\r | |
75ce7ef7 | 27 | \r |
2f88bd3a MK |
28 | #define EFI_ACPI_IORT_TYPE_ITS_GROUP 0x0\r |
29 | #define EFI_ACPI_IORT_TYPE_NAMED_COMP 0x1\r | |
30 | #define EFI_ACPI_IORT_TYPE_ROOT_COMPLEX 0x2\r | |
31 | #define EFI_ACPI_IORT_TYPE_SMMUv1v2 0x3\r | |
32 | #define EFI_ACPI_IORT_TYPE_SMMUv3 0x4\r | |
33 | #define EFI_ACPI_IORT_TYPE_PMCG 0x5\r | |
4c55f639 | 34 | #define EFI_ACPI_IORT_TYPE_RMR 0x6\r |
75ce7ef7 | 35 | \r |
2f88bd3a | 36 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA BIT0\r |
75ce7ef7 | 37 | \r |
2f88bd3a MK |
38 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_TR BIT0\r |
39 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_WA BIT1\r | |
40 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_RA BIT2\r | |
41 | #define EFI_ACPI_IORT_MEM_ACCESS_PROP_AH_AHO BIT3\r | |
75ce7ef7 | 42 | \r |
2f88bd3a MK |
43 | #define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_CPM BIT0\r |
44 | #define EFI_ACPI_IORT_MEM_ACCESS_FLAGS_DACS BIT1\r | |
75ce7ef7 AB |
45 | \r |
46 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_v1 0x0\r | |
47 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_v2 0x1\r | |
48 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU400 0x2\r | |
49 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU500 0x3\r | |
157fb7bf AB |
50 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_MMU401 0x4\r |
51 | #define EFI_ACPI_IORT_SMMUv1v2_MODEL_CAVIUM_THX_v2 0x5\r | |
75ce7ef7 | 52 | \r |
2f88bd3a MK |
53 | #define EFI_ACPI_IORT_SMMUv1v2_FLAG_DVM BIT0\r |
54 | #define EFI_ACPI_IORT_SMMUv1v2_FLAG_COH_WALK BIT1\r | |
75ce7ef7 | 55 | \r |
2f88bd3a MK |
56 | #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_LEVEL 0x0\r |
57 | #define EFI_ACPI_IORT_SMMUv1v2_INT_FLAG_EDGE 0x1\r | |
75ce7ef7 AB |
58 | \r |
59 | #define EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE BIT0\r | |
60 | #define EFI_ACPI_IORT_SMMUv3_FLAG_HTTU_OVERRIDE BIT1\r | |
27e98391 SM |
61 | #define EFI_ACPI_IORT_SMMUv3_FLAG_PROXIMITY_DOMAIN BIT3\r |
62 | \r | |
2f88bd3a MK |
63 | #define EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC 0x0\r |
64 | #define EFI_ACPI_IORT_SMMUv3_MODEL_HISILICON_HI161X 0x1\r | |
65 | #define EFI_ACPI_IORT_SMMUv3_MODEL_CAVIUM_CN99XX 0x2\r | |
75ce7ef7 AB |
66 | \r |
67 | #define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED 0x0\r | |
4c55f639 SM |
68 | #define EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED BIT0\r |
69 | \r | |
70 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_UNSUPPORTED 0x0\r | |
71 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PRI_SUPPORTED BIT1\r | |
72 | \r | |
73 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_UNSUPPORTED 0x0\r | |
74 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_FWD_SUPPORTED BIT2\r | |
75 | \r | |
76 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_UNSUPPORTED 0x0\r | |
77 | #define EFI_ACPI_IORT_ROOT_COMPLEX_PASID_SUPPORTED BIT1\r | |
78 | \r | |
79 | #define EFI_ACPI_IORT_RMR_REMAP_NOT_PERMITTED 0x0\r | |
80 | #define EFI_ACPI_IORT_RMR_REMAP_PERMITTED BIT0\r | |
81 | \r | |
82 | #define EFI_ACPI_IORT_RMR_ACCESS_REQ_NOT_PRIVILEGED 0x0\r | |
83 | #define EFI_ACPI_IORT_RMR_ACCESS_REQ_PRIVILEGED BIT1\r | |
84 | \r | |
85 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRNE 0x0\r | |
86 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGNRE 0x1\r | |
87 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_NGRE 0x2\r | |
88 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_DEV_GRE 0x3\r | |
89 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_NC_OUT_NC 0x4\r | |
90 | #define EFI_ACPI_IORT_RMR_ACCESS_ATTRIB_NORM_IN_WB_OUT_WB_ISH 0x5\r | |
75ce7ef7 | 91 | \r |
2f88bd3a | 92 | #define EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE BIT0\r |
75ce7ef7 | 93 | \r |
4c55f639 SM |
94 | #define EFI_ACPI_IORT_RMR_NODE_REVISION_02 0x2 // Deprecated\r |
95 | \r | |
75ce7ef7 AB |
96 | #pragma pack(1)\r |
97 | \r | |
98 | ///\r | |
99 | /// Table header\r | |
100 | ///\r | |
101 | typedef struct {\r | |
2f88bd3a MK |
102 | EFI_ACPI_DESCRIPTION_HEADER Header;\r |
103 | UINT32 NumNodes;\r | |
104 | UINT32 NodeOffset;\r | |
105 | UINT32 Reserved;\r | |
75ce7ef7 AB |
106 | } EFI_ACPI_6_0_IO_REMAPPING_TABLE;\r |
107 | \r | |
108 | ///\r | |
109 | /// Definition for ID mapping table shared by all node types\r | |
110 | ///\r | |
111 | typedef struct {\r | |
2f88bd3a MK |
112 | UINT32 InputBase;\r |
113 | UINT32 NumIds;\r | |
114 | UINT32 OutputBase;\r | |
115 | UINT32 OutputReference;\r | |
116 | UINT32 Flags;\r | |
75ce7ef7 AB |
117 | } EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE;\r |
118 | \r | |
119 | ///\r | |
120 | /// Node header definition shared by all node types\r | |
121 | ///\r | |
122 | typedef struct {\r | |
2f88bd3a MK |
123 | UINT8 Type;\r |
124 | UINT16 Length;\r | |
125 | UINT8 Revision;\r | |
4c55f639 | 126 | UINT32 Identifier;\r |
2f88bd3a MK |
127 | UINT32 NumIdMappings;\r |
128 | UINT32 IdReference;\r | |
75ce7ef7 AB |
129 | } EFI_ACPI_6_0_IO_REMAPPING_NODE;\r |
130 | \r | |
131 | ///\r | |
132 | /// Node type 0: ITS node\r | |
133 | ///\r | |
134 | typedef struct {\r | |
2f88bd3a | 135 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
75ce7ef7 | 136 | \r |
2f88bd3a MK |
137 | UINT32 NumItsIdentifiers;\r |
138 | // UINT32 ItsIdentifiers[NumItsIdentifiers];\r | |
75ce7ef7 AB |
139 | } EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;\r |
140 | \r | |
141 | ///\r | |
142 | /// Node type 1: root complex node\r | |
143 | ///\r | |
144 | typedef struct {\r | |
2f88bd3a | 145 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
75ce7ef7 | 146 | \r |
2f88bd3a MK |
147 | UINT32 CacheCoherent;\r |
148 | UINT8 AllocationHints;\r | |
149 | UINT16 Reserved;\r | |
150 | UINT8 MemoryAccessFlags;\r | |
75ce7ef7 | 151 | \r |
2f88bd3a MK |
152 | UINT32 AtsAttribute;\r |
153 | UINT32 PciSegmentNumber;\r | |
154 | UINT8 MemoryAddressSize;\r | |
4c55f639 SM |
155 | UINT16 PasidCapabilities;\r |
156 | UINT8 Reserved1[1];\r | |
157 | UINT32 Flags;\r | |
75ce7ef7 AB |
158 | } EFI_ACPI_6_0_IO_REMAPPING_RC_NODE;\r |
159 | \r | |
160 | ///\r | |
161 | /// Node type 2: named component node\r | |
162 | ///\r | |
163 | typedef struct {\r | |
2f88bd3a MK |
164 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
165 | \r | |
166 | UINT32 Flags;\r | |
167 | UINT32 CacheCoherent;\r | |
168 | UINT8 AllocationHints;\r | |
169 | UINT16 Reserved;\r | |
170 | UINT8 MemoryAccessFlags;\r | |
171 | UINT8 AddressSizeLimit;\r | |
172 | // UINT8 ObjectName[];\r | |
75ce7ef7 AB |
173 | } EFI_ACPI_6_0_IO_REMAPPING_NAMED_COMP_NODE;\r |
174 | \r | |
175 | ///\r | |
176 | /// Node type 3: SMMUv1 or SMMUv2 node\r | |
177 | ///\r | |
178 | typedef struct {\r | |
2f88bd3a MK |
179 | UINT32 Interrupt;\r |
180 | UINT32 InterruptFlags;\r | |
75ce7ef7 AB |
181 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU_INT;\r |
182 | \r | |
183 | typedef struct {\r | |
2f88bd3a MK |
184 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
185 | \r | |
186 | UINT64 Base;\r | |
187 | UINT64 Span;\r | |
188 | UINT32 Model;\r | |
189 | UINT32 Flags;\r | |
190 | UINT32 GlobalInterruptArrayRef;\r | |
191 | UINT32 NumContextInterrupts;\r | |
192 | UINT32 ContextInterruptArrayRef;\r | |
193 | UINT32 NumPmuInterrupts;\r | |
194 | UINT32 PmuInterruptArrayRef;\r | |
195 | \r | |
196 | UINT32 SMMU_NSgIrpt;\r | |
197 | UINT32 SMMU_NSgIrptFlags;\r | |
198 | UINT32 SMMU_NSgCfgIrpt;\r | |
199 | UINT32 SMMU_NSgCfgIrptFlags;\r | |
200 | \r | |
201 | // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT ContextInterrupt[NumContextInterrupts];\r | |
202 | // EFI_ACPI_6_0_IO_REMAPPING_SMMU_CTX_INT PmuInterrupt[NumPmuInterrupts];\r | |
75ce7ef7 AB |
203 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU_NODE;\r |
204 | \r | |
205 | ///\r | |
27e98391 | 206 | /// Node type 4: SMMUv3 node\r |
75ce7ef7 AB |
207 | ///\r |
208 | typedef struct {\r | |
2f88bd3a MK |
209 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
210 | \r | |
211 | UINT64 Base;\r | |
212 | UINT32 Flags;\r | |
213 | UINT32 Reserved;\r | |
214 | UINT64 VatosAddress;\r | |
215 | UINT32 Model;\r | |
216 | UINT32 Event;\r | |
217 | UINT32 Pri;\r | |
218 | UINT32 Gerr;\r | |
219 | UINT32 Sync;\r | |
220 | UINT32 ProximityDomain;\r | |
221 | UINT32 DeviceIdMappingIndex;\r | |
75ce7ef7 AB |
222 | } EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;\r |
223 | \r | |
157fb7bf AB |
224 | ///\r |
225 | /// Node type 5: PMCG node\r | |
226 | ///\r | |
227 | typedef struct {\r | |
2f88bd3a | 228 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r |
157fb7bf | 229 | \r |
2f88bd3a MK |
230 | UINT64 Base;\r |
231 | UINT32 OverflowInterruptGsiv;\r | |
232 | UINT32 NodeReference;\r | |
233 | UINT64 Page1Base;\r | |
234 | // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE OverflowInterruptMsiMapping[1];\r | |
157fb7bf AB |
235 | } EFI_ACPI_6_0_IO_REMAPPING_PMCG_NODE;\r |
236 | \r | |
4c55f639 SM |
237 | ///\r |
238 | /// Memory Range Descriptor.\r | |
239 | ///\r | |
240 | typedef struct {\r | |
241 | /// Base address of Reserved Memory Range,\r | |
242 | /// aligned to a page size of 64K.\r | |
243 | UINT64 Base;\r | |
244 | \r | |
245 | /// Length of the Reserved Memory range.\r | |
246 | /// Must be a multiple of the page size of 64K.\r | |
247 | UINT64 Length;\r | |
248 | \r | |
249 | /// Reserved, must be zero.\r | |
250 | UINT32 Reserved;\r | |
251 | } EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC;\r | |
252 | \r | |
253 | ///\r | |
254 | /// Node type 6: Reserved Memory Range (RMR) node\r | |
255 | ///\r | |
256 | typedef struct {\r | |
257 | EFI_ACPI_6_0_IO_REMAPPING_NODE Node;\r | |
258 | \r | |
259 | /// RMR flags\r | |
260 | UINT32 Flags;\r | |
261 | \r | |
262 | /// Memory range descriptor count.\r | |
263 | UINT32 NumMemRangeDesc;\r | |
264 | \r | |
265 | /// Offset of the memory range descriptor array.\r | |
266 | UINT32 MemRangeDescRef;\r | |
267 | // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE IdMapping[1];\r | |
268 | // EFI_ACPI_6_0_IO_REMAPPING_MEM_RANGE_DESC MemRangeDesc[1];\r | |
269 | } EFI_ACPI_6_0_IO_REMAPPING_RMR_NODE;\r | |
270 | \r | |
75ce7ef7 AB |
271 | #pragma pack()\r |
272 | \r | |
273 | #endif\r |