MdePkg/Include: Add LOONGARCH related definitions EDK2 CI.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=4053

HTTP/PXE boot LOONGARCH64 related definitions for EDK2 CI.

For the LOONGARCH values, please seeing following URL section
"Processor Architecture Types":
https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml

Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Zhiguang Liu <zhiguang.liu@intel.com>
Signed-off-by: Chao Li <lichao@loongson.cn>
Reviewed-by: Michael D Kinney <michael.d.kinney@intel.com>

diff --git a/MdePkg/Include/IndustryStandard/Dhcp.h b/MdePkg/Include/IndustryStandard/Dhcp.h
index f209f1b2eb1a27fb35f8c6a0f06092e93fbf854f..46ab4f8e750139c942440b528a8c718178fdd89d 100644 (file)
--- a/MdePkg/Include/IndustryStandard/Dhcp.h
+++ b/MdePkg/Include/IndustryStandard/Dhcp.h
@@ -4,6 +4,7 @@
 \r
   Copyright (c) 2016, Intel Corporation. All rights reserved.<BR>\r
   Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+  Copyright (c) 2022, Loongson Technology Corporation Limited. All rights reserved.<BR>\r
   SPDX-License-Identifier: BSD-2-Clause-Patent\r
 **/\r
 \r
@@ -256,27 +257,31 @@ typedef enum {
 \r
 ///\r
 /// Processor Architecture Types\r
-/// These identifiers are defined by IETF:\r
-/// http://www.ietf.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xml\r
+/// These identifiers are defined by IANA:\r
+/// https://www.iana.org/assignments/dhcpv6-parameters/dhcpv6-parameters.xhtml\r
 ///\r
-#define PXE_CLIENT_ARCH_X86_BIOS  0x0000           /// x86 BIOS for PXE\r
-#define PXE_CLIENT_ARCH_IPF       0x0002           /// Itanium for PXE\r
-#define PXE_CLIENT_ARCH_IA32      0x0006           /// x86 uefi for PXE\r
-#define PXE_CLIENT_ARCH_X64       0x0007           /// x64 uefi for PXE\r
-#define PXE_CLIENT_ARCH_EBC       0x0009           /// EBC for PXE\r
-#define PXE_CLIENT_ARCH_ARM       0x000A           /// Arm uefi 32 for PXE\r
-#define PXE_CLIENT_ARCH_AARCH64   0x000B           /// Arm uefi 64 for PXE\r
-#define PXE_CLIENT_ARCH_RISCV32   0x0019           /// RISC-V uefi 32 for PXE\r
-#define PXE_CLIENT_ARCH_RISCV64   0x001B           /// RISC-V uefi 64 for PXE\r
-#define PXE_CLIENT_ARCH_RISCV128  0x001D           /// RISC-V uefi 128 for PXE\r
+#define PXE_CLIENT_ARCH_X86_BIOS     0x0000          /// x86 BIOS for PXE\r
+#define PXE_CLIENT_ARCH_IPF          0x0002          /// Itanium for PXE\r
+#define PXE_CLIENT_ARCH_IA32         0x0006          /// x86 uefi for PXE\r
+#define PXE_CLIENT_ARCH_X64          0x0007          /// x64 uefi for PXE\r
+#define PXE_CLIENT_ARCH_EBC          0x0009          /// EBC for PXE\r
+#define PXE_CLIENT_ARCH_ARM          0x000A          /// Arm uefi 32 for PXE\r
+#define PXE_CLIENT_ARCH_AARCH64      0x000B          /// Arm uefi 64 for PXE\r
+#define PXE_CLIENT_ARCH_RISCV32      0x0019          /// RISC-V uefi 32 for PXE\r
+#define PXE_CLIENT_ARCH_RISCV64      0x001B          /// RISC-V uefi 64 for PXE\r
+#define PXE_CLIENT_ARCH_RISCV128     0x001D          /// RISC-V uefi 128 for PXE\r
+#define PXE_CLIENT_ARCH_LOONGARCH32  0x0025          /// LoongArch uefi 32 for PXE\r
+#define PXE_CLIENT_ARCH_LOONGARCH64  0x0027          /// LoongArch uefi 64 for PXE\r
 \r
-#define HTTP_CLIENT_ARCH_IA32      0x000F          /// x86 uefi boot from http\r
-#define HTTP_CLIENT_ARCH_X64       0x0010          /// x64 uefi boot from http\r
-#define HTTP_CLIENT_ARCH_EBC       0x0011          /// EBC boot from http\r
-#define HTTP_CLIENT_ARCH_ARM       0x0012          /// Arm uefi 32 boot from http\r
-#define HTTP_CLIENT_ARCH_AARCH64   0x0013          /// Arm uefi 64 boot from http\r
-#define HTTP_CLIENT_ARCH_RISCV32   0x001A          /// RISC-V uefi 32 boot from http\r
-#define HTTP_CLIENT_ARCH_RISCV64   0x001C          /// RISC-V uefi 64 boot from http\r
-#define HTTP_CLIENT_ARCH_RISCV128  0x001E          /// RISC-V uefi 128 boot from http\r
+#define HTTP_CLIENT_ARCH_IA32         0x000F          /// x86 uefi boot from http\r
+#define HTTP_CLIENT_ARCH_X64          0x0010          /// x64 uefi boot from http\r
+#define HTTP_CLIENT_ARCH_EBC          0x0011          /// EBC boot from http\r
+#define HTTP_CLIENT_ARCH_ARM          0x0012          /// Arm uefi 32 boot from http\r
+#define HTTP_CLIENT_ARCH_AARCH64      0x0013          /// Arm uefi 64 boot from http\r
+#define HTTP_CLIENT_ARCH_RISCV32      0x001A          /// RISC-V uefi 32 boot from http\r
+#define HTTP_CLIENT_ARCH_RISCV64      0x001C          /// RISC-V uefi 64 boot from http\r
+#define HTTP_CLIENT_ARCH_RISCV128     0x001E          /// RISC-V uefi 128 boot from http\r
+#define HTTP_CLIENT_ARCH_LOONGARCH32  0x0026          /// LoongArch uefi 32 boot from http\r
+#define HTTP_CLIENT_ARCH_LOONGARCH64  0x0028          /// LoongArch uefi 64 boot from http\r
 \r
 #endif\r