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a7ed1e2e | 1 | /** @file\r |
7ddba202 | 2 | Industry Standard Definitions of SMBIOS Table Specification v2.7.1\r |
a7ed1e2e | 3 | \r |
7ddba202 | 4 | Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR>\r |
af2dc6a7 | 5 | This program and the accompanying materials are licensed and made available under \r |
6 | the terms and conditions of the BSD License that accompanies this distribution. \r | |
7 | The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php. \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
a7ed1e2e | 12 | \r |
a7ed1e2e | 13 | **/\r |
14 | \r | |
15 | #ifndef __SMBIOS_STANDARD_H__\r | |
16 | #define __SMBIOS_STANDARD_H__\r | |
98cb9ae8 | 17 | \r |
f2d0889f | 18 | ///\r |
19 | /// Reference SMBIOS 2.6, chapter 3.1.2.\r | |
20 | /// For v2.1 and later, handle values in the range 0FF00h to 0FFFFh are reserved for\r | |
21 | /// use by this specification.\r | |
22 | ///\r | |
23 | #define SMBIOS_HANDLE_RESERVED_BEGIN 0xFF00\r | |
24 | \r | |
7ddba202 SZ |
25 | ///\r |
26 | /// Reference SMBIOS 2.7, chapter 6.1.2.\r | |
27 | /// The UEFI Platform Initialization Specification reserves handle number FFFEh for its\r | |
28 | /// EFI_SMBIOS_PROTOCOL.Add() function to mean "assign an unused handle number automatically."\r | |
29 | /// This number is not used for any other purpose by the SMBIOS specification.\r | |
30 | ///\r | |
31 | #define SMBIOS_HANDLE_PI_RESERVED 0xFFFE\r | |
32 | \r | |
f2d0889f | 33 | ///\r |
af2dc6a7 | 34 | /// Reference SMBIOS 2.6, chapter 3.1.3.\r |
35 | /// Each text string is limited to 64 significant characters due to system MIF limitations.\r | |
7ddba202 SZ |
36 | /// Reference SMBIOS 2.7, chapter 6.1.3.\r |
37 | /// It will have no limit on the length of each individual text string.\r | |
f2d0889f | 38 | ///\r |
39 | #define SMBIOS_STRING_MAX_LENGTH 64\r | |
40 | \r | |
41 | ///\r | |
42 | /// Inactive type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.43.\r | |
43 | /// Upper-level software that interprets the SMBIOS structure-table should bypass an \r | |
44 | /// Inactive structure just like a structure type that the software does not recognize.\r | |
45 | ///\r | |
46 | #define SMBIOS_TYPE_INACTIVE 0x007E \r | |
47 | \r | |
48 | ///\r | |
49 | /// End-of-table type is added from SMBIOS 2.2. Reference SMBIOS 2.6, chapter 3.3.44.\r | |
50 | /// The end-of-table indicator is used in the last physical structure in a table\r | |
51 | ///\r | |
52 | #define SMBIOS_TYPE_END_OF_TABLE 0x007F\r | |
53 | \r | |
4135253b | 54 | ///\r |
af2dc6a7 | 55 | /// Smbios Table Entry Point Structure.\r |
4135253b | 56 | ///\r |
766f4bc1 | 57 | #pragma pack(1)\r |
a7ed1e2e | 58 | typedef struct {\r |
59 | UINT8 AnchorString[4];\r | |
60 | UINT8 EntryPointStructureChecksum;\r | |
61 | UINT8 EntryPointLength;\r | |
62 | UINT8 MajorVersion;\r | |
63 | UINT8 MinorVersion;\r | |
64 | UINT16 MaxStructureSize;\r | |
65 | UINT8 EntryPointRevision;\r | |
66 | UINT8 FormattedArea[5];\r | |
67 | UINT8 IntermediateAnchorString[5];\r | |
68 | UINT8 IntermediateChecksum;\r | |
69 | UINT16 TableLength;\r | |
70 | UINT32 TableAddress;\r | |
71 | UINT16 NumberOfSmbiosStructures;\r | |
72 | UINT8 SmbiosBcdRevision;\r | |
73 | } SMBIOS_TABLE_ENTRY_POINT;\r | |
74 | \r | |
ec8432e5 | 75 | ///\r |
af2dc6a7 | 76 | /// The Smbios structure header.\r |
ec8432e5 | 77 | ///\r |
a7ed1e2e | 78 | typedef struct {\r |
79 | UINT8 Type;\r | |
80 | UINT8 Length;\r | |
81 | UINT16 Handle;\r | |
82 | } SMBIOS_STRUCTURE;\r | |
83 | \r | |
bf7ea009 | 84 | ///\r |
85 | /// String Number for a Null terminated string, 00h stands for no string available.\r | |
86 | ///\r | |
61ce5861 | 87 | typedef UINT8 SMBIOS_TABLE_STRING;\r |
88 | \r | |
98cb9ae8 | 89 | ///\r |
7ddba202 SZ |
90 | /// BIOS Characteristics\r |
91 | /// Defines which functions the BIOS supports. PCI, PCMCIA, Flash, etc.\r | |
98cb9ae8 | 92 | ///\r |
93 | typedef struct {\r | |
af2dc6a7 | 94 | UINT32 Reserved :2; ///< Bits 0-1.\r |
7ddba202 SZ |
95 | UINT32 Unknown :1;\r |
96 | UINT32 BiosCharacteristicsNotSupported :1;\r | |
97 | UINT32 IsaIsSupported :1;\r | |
98cb9ae8 | 98 | UINT32 McaIsSupported :1;\r |
99 | UINT32 EisaIsSupported :1;\r | |
100 | UINT32 PciIsSupported :1;\r | |
101 | UINT32 PcmciaIsSupported :1;\r | |
102 | UINT32 PlugAndPlayIsSupported :1;\r | |
103 | UINT32 ApmIsSupported :1;\r | |
104 | UINT32 BiosIsUpgradable :1;\r | |
105 | UINT32 BiosShadowingAllowed :1;\r | |
106 | UINT32 VlVesaIsSupported :1;\r | |
107 | UINT32 EscdSupportIsAvailable :1;\r | |
108 | UINT32 BootFromCdIsSupported :1;\r | |
109 | UINT32 SelectableBootIsSupported :1;\r | |
110 | UINT32 RomBiosIsSocketed :1;\r | |
111 | UINT32 BootFromPcmciaIsSupported :1;\r | |
112 | UINT32 EDDSpecificationIsSupported :1;\r | |
113 | UINT32 JapaneseNecFloppyIsSupported :1;\r | |
114 | UINT32 JapaneseToshibaFloppyIsSupported :1;\r | |
115 | UINT32 Floppy525_360IsSupported :1;\r | |
116 | UINT32 Floppy525_12IsSupported :1;\r | |
117 | UINT32 Floppy35_720IsSupported :1;\r | |
118 | UINT32 Floppy35_288IsSupported :1;\r | |
119 | UINT32 PrintScreenIsSupported :1;\r | |
120 | UINT32 Keyboard8042IsSupported :1;\r | |
121 | UINT32 SerialIsSupported :1;\r | |
122 | UINT32 PrinterIsSupported :1;\r | |
123 | UINT32 CgaMonoIsSupported :1;\r | |
124 | UINT32 NecPc98 :1;\r | |
6800ac83 | 125 | UINT32 ReservedForVendor :32; ///< Bits 32-63. Bits 32-47 reserved for BIOS vendor \r |
126 | ///< and bits 48-63 reserved for System Vendor. \r | |
98cb9ae8 | 127 | } MISC_BIOS_CHARACTERISTICS;\r |
128 | \r | |
129 | ///\r | |
7ddba202 SZ |
130 | /// BIOS Characteristics Extension Byte 1.\r |
131 | /// This information, available for SMBIOS version 2.1 and later, appears at offset 12h\r | |
132 | /// within the BIOS Information structure.\r | |
98cb9ae8 | 133 | ///\r |
134 | typedef struct {\r | |
135 | UINT8 AcpiIsSupported :1;\r | |
7ddba202 SZ |
136 | UINT8 UsbLegacyIsSupported :1;\r |
137 | UINT8 AgpIsSupported :1;\r | |
119c1688 | 138 | UINT8 I2OBootIsSupported :1;\r |
98cb9ae8 | 139 | UINT8 Ls120BootIsSupported :1;\r |
140 | UINT8 AtapiZipDriveBootIsSupported :1;\r | |
141 | UINT8 Boot1394IsSupported :1;\r | |
142 | UINT8 SmartBatteryIsSupported :1;\r | |
143 | } MBCE_BIOS_RESERVED;\r | |
144 | \r | |
145 | ///\r | |
af2dc6a7 | 146 | /// BIOS Characteristics Extension Byte 2.\r |
7ddba202 | 147 | /// This information, available for SMBIOS version 2.3 and later, appears at offset 13h\r |
98cb9ae8 | 148 | /// within the BIOS Information structure.\r |
149 | ///\r | |
150 | typedef struct {\r | |
151 | UINT8 BiosBootSpecIsSupported :1;\r | |
7ddba202 SZ |
152 | UINT8 FunctionKeyNetworkBootIsSupported :1;\r |
153 | UINT8 TargetContentDistributionEnabled :1;\r | |
154 | UINT8 UefiSpecificationSupported :1;\r | |
155 | UINT8 VirtualMachineSupported :1;\r | |
156 | UINT8 ExtensionByte2Reserved :3;\r | |
98cb9ae8 | 157 | } MBCE_SYSTEM_RESERVED;\r |
158 | \r | |
159 | ///\r | |
af2dc6a7 | 160 | /// BIOS Characteristics Extension Bytes.\r |
98cb9ae8 | 161 | ///\r |
162 | typedef struct {\r | |
163 | MBCE_BIOS_RESERVED BiosReserved;\r | |
164 | MBCE_SYSTEM_RESERVED SystemReserved;\r | |
98cb9ae8 | 165 | } MISC_BIOS_CHARACTERISTICS_EXTENSION;\r |
166 | \r | |
4135253b | 167 | ///\r |
af2dc6a7 | 168 | /// BIOS Information (Type 0).\r |
4135253b | 169 | ///\r |
61ce5861 | 170 | typedef struct {\r |
98cb9ae8 | 171 | SMBIOS_STRUCTURE Hdr;\r |
172 | SMBIOS_TABLE_STRING Vendor;\r | |
173 | SMBIOS_TABLE_STRING BiosVersion;\r | |
174 | UINT16 BiosSegment;\r | |
175 | SMBIOS_TABLE_STRING BiosReleaseDate;\r | |
176 | UINT8 BiosSize;\r | |
177 | MISC_BIOS_CHARACTERISTICS BiosCharacteristics;\r | |
178 | UINT8 BIOSCharacteristicsExtensionBytes[2];\r | |
179 | UINT8 SystemBiosMajorRelease;\r | |
180 | UINT8 SystemBiosMinorRelease;\r | |
181 | UINT8 EmbeddedControllerFirmwareMajorRelease;\r | |
182 | UINT8 EmbeddedControllerFirmwareMinorRelease;\r | |
61ce5861 | 183 | } SMBIOS_TABLE_TYPE0;\r |
184 | \r | |
98cb9ae8 | 185 | ///\r |
af2dc6a7 | 186 | /// System Wake-up Type.\r |
98cb9ae8 | 187 | ///\r |
188 | typedef enum { \r | |
189 | SystemWakeupTypeReserved = 0x00,\r | |
190 | SystemWakeupTypeOther = 0x01,\r | |
191 | SystemWakeupTypeUnknown = 0x02,\r | |
192 | SystemWakeupTypeApmTimer = 0x03,\r | |
193 | SystemWakeupTypeModemRing = 0x04,\r | |
194 | SystemWakeupTypeLanRemote = 0x05,\r | |
195 | SystemWakeupTypePowerSwitch = 0x06,\r | |
196 | SystemWakeupTypePciPme = 0x07,\r | |
197 | SystemWakeupTypeAcPowerRestored = 0x08\r | |
198 | } MISC_SYSTEM_WAKEUP_TYPE;\r | |
199 | \r | |
4135253b | 200 | ///\r |
af2dc6a7 | 201 | /// System Information (Type 1).\r |
98cb9ae8 | 202 | /// \r |
203 | /// The information in this structure defines attributes of the overall system and is \r | |
204 | /// intended to be associated with the Component ID group of the system's MIF.\r | |
205 | /// An SMBIOS implementation is associated with a single system instance and contains \r | |
206 | /// one and only one System Information (Type 1) structure.\r | |
4135253b | 207 | ///\r |
61ce5861 | 208 | typedef struct {\r |
98cb9ae8 | 209 | SMBIOS_STRUCTURE Hdr;\r |
210 | SMBIOS_TABLE_STRING Manufacturer;\r | |
211 | SMBIOS_TABLE_STRING ProductName;\r | |
212 | SMBIOS_TABLE_STRING Version;\r | |
213 | SMBIOS_TABLE_STRING SerialNumber;\r | |
214 | GUID Uuid;\r | |
af2dc6a7 | 215 | UINT8 WakeUpType; ///< The enumeration value from MISC_SYSTEM_WAKEUP_TYPE.\r |
98cb9ae8 | 216 | SMBIOS_TABLE_STRING SKUNumber;\r |
217 | SMBIOS_TABLE_STRING Family;\r | |
61ce5861 | 218 | } SMBIOS_TABLE_TYPE1;\r |
219 | \r | |
98cb9ae8 | 220 | ///\r |
af2dc6a7 | 221 | /// Base Board - Feature Flags. \r |
98cb9ae8 | 222 | ///\r |
223 | typedef struct {\r | |
224 | UINT8 Motherboard :1;\r | |
225 | UINT8 RequiresDaughterCard :1;\r | |
226 | UINT8 Removable :1;\r | |
227 | UINT8 Replaceable :1;\r | |
228 | UINT8 HotSwappable :1;\r | |
229 | UINT8 Reserved :3;\r | |
230 | } BASE_BOARD_FEATURE_FLAGS;\r | |
231 | \r | |
232 | ///\r | |
af2dc6a7 | 233 | /// Base Board - Board Type.\r |
98cb9ae8 | 234 | ///\r |
235 | typedef enum { \r | |
236 | BaseBoardTypeUnknown = 0x1,\r | |
237 | BaseBoardTypeOther = 0x2,\r | |
238 | BaseBoardTypeServerBlade = 0x3,\r | |
239 | BaseBoardTypeConnectivitySwitch = 0x4,\r | |
240 | BaseBoardTypeSystemManagementModule = 0x5,\r | |
241 | BaseBoardTypeProcessorModule = 0x6,\r | |
242 | BaseBoardTypeIOModule = 0x7,\r | |
243 | BaseBoardTypeMemoryModule = 0x8,\r | |
244 | BaseBoardTypeDaughterBoard = 0x9,\r | |
245 | BaseBoardTypeMotherBoard = 0xA,\r | |
246 | BaseBoardTypeProcessorMemoryModule = 0xB,\r | |
247 | BaseBoardTypeProcessorIOModule = 0xC,\r | |
248 | BaseBoardTypeInterconnectBoard = 0xD\r | |
249 | } BASE_BOARD_TYPE;\r | |
250 | \r | |
4135253b | 251 | ///\r |
af2dc6a7 | 252 | /// Base Board (or Module) Information (Type 2).\r |
4135253b | 253 | ///\r |
1f9f8414 | 254 | /// The information in this structure defines attributes of a system baseboard - \r |
98cb9ae8 | 255 | /// for example a motherboard, planar, or server blade or other standard system module.\r |
256 | ///\r | |
61ce5861 | 257 | typedef struct {\r |
98cb9ae8 | 258 | SMBIOS_STRUCTURE Hdr;\r |
259 | SMBIOS_TABLE_STRING Manufacturer;\r | |
260 | SMBIOS_TABLE_STRING ProductName;\r | |
261 | SMBIOS_TABLE_STRING Version;\r | |
262 | SMBIOS_TABLE_STRING SerialNumber;\r | |
263 | SMBIOS_TABLE_STRING AssetTag;\r | |
264 | BASE_BOARD_FEATURE_FLAGS FeatureFlag;\r | |
265 | SMBIOS_TABLE_STRING LocationInChassis;\r | |
266 | UINT16 ChassisHandle;\r | |
af2dc6a7 | 267 | UINT8 BoardType; ///< The enumeration value from BASE_BOARD_TYPE.\r |
98cb9ae8 | 268 | UINT8 NumberOfContainedObjectHandles;\r |
269 | UINT16 ContainedObjectHandles[1];\r | |
61ce5861 | 270 | } SMBIOS_TABLE_TYPE2;\r |
271 | \r | |
98cb9ae8 | 272 | ///\r |
273 | /// System Enclosure or Chassis Types\r | |
274 | ///\r | |
275 | typedef enum { \r | |
276 | MiscChassisTypeOther = 0x01,\r | |
277 | MiscChassisTypeUnknown = 0x02,\r | |
278 | MiscChassisTypeDeskTop = 0x03,\r | |
279 | MiscChassisTypeLowProfileDesktop = 0x04,\r | |
280 | MiscChassisTypePizzaBox = 0x05,\r | |
281 | MiscChassisTypeMiniTower = 0x06,\r | |
282 | MiscChassisTypeTower = 0x07,\r | |
283 | MiscChassisTypePortable = 0x08,\r | |
284 | MiscChassisTypeLapTop = 0x09,\r | |
285 | MiscChassisTypeNotebook = 0x0A,\r | |
286 | MiscChassisTypeHandHeld = 0x0B,\r | |
287 | MiscChassisTypeDockingStation = 0x0C,\r | |
288 | MiscChassisTypeAllInOne = 0x0D,\r | |
289 | MiscChassisTypeSubNotebook = 0x0E,\r | |
290 | MiscChassisTypeSpaceSaving = 0x0F,\r | |
291 | MiscChassisTypeLunchBox = 0x10,\r | |
292 | MiscChassisTypeMainServerChassis = 0x11,\r | |
293 | MiscChassisTypeExpansionChassis = 0x12,\r | |
294 | MiscChassisTypeSubChassis = 0x13,\r | |
295 | MiscChassisTypeBusExpansionChassis = 0x14,\r | |
296 | MiscChassisTypePeripheralChassis = 0x15,\r | |
297 | MiscChassisTypeRaidChassis = 0x16,\r | |
298 | MiscChassisTypeRackMountChassis = 0x17,\r | |
299 | MiscChassisTypeSealedCasePc = 0x18,\r | |
300 | MiscChassisMultiSystemChassis = 0x19,\r | |
301 | MiscChassisCompactPCI = 0x1A,\r | |
302 | MiscChassisAdvancedTCA = 0x1B,\r | |
303 | MiscChassisBlade = 0x1C,\r | |
304 | MiscChassisBladeEnclosure = 0x1D\r | |
305 | } MISC_CHASSIS_TYPE;\r | |
306 | \r | |
307 | ///\r | |
af2dc6a7 | 308 | /// System Enclosure or Chassis States .\r |
98cb9ae8 | 309 | ///\r |
310 | typedef enum { \r | |
311 | ChassisStateOther = 0x01,\r | |
312 | ChassisStateUnknown = 0x02,\r | |
313 | ChassisStateSafe = 0x03,\r | |
314 | ChassisStateWarning = 0x04,\r | |
315 | ChassisStateCritical = 0x05,\r | |
316 | ChassisStateNonRecoverable = 0x06\r | |
317 | } MISC_CHASSIS_STATE;\r | |
318 | \r | |
319 | ///\r | |
af2dc6a7 | 320 | /// System Enclosure or Chassis Security Status.\r |
98cb9ae8 | 321 | ///\r |
322 | typedef enum { \r | |
323 | ChassisSecurityStatusOther = 0x01,\r | |
324 | ChassisSecurityStatusUnknown = 0x02,\r | |
325 | ChassisSecurityStatusNone = 0x03,\r | |
326 | ChassisSecurityStatusExternalInterfaceLockedOut = 0x04,\r | |
327 | ChassisSecurityStatusExternalInterfaceLockedEnabled = 0x05\r | |
328 | } MISC_CHASSIS_SECURITY_STATE;\r | |
329 | \r | |
bf7ea009 | 330 | ///\r |
331 | /// Contained Element record\r | |
332 | ///\r | |
61ce5861 | 333 | typedef struct {\r |
334 | UINT8 ContainedElementType;\r | |
335 | UINT8 ContainedElementMinimum;\r | |
336 | UINT8 ContainedElementMaximum;\r | |
337 | } CONTAINED_ELEMENT;\r | |
338 | \r | |
98cb9ae8 | 339 | \r |
4135253b | 340 | ///\r |
af2dc6a7 | 341 | /// System Enclosure or Chassis (Type 3).\r |
4135253b | 342 | ///\r |
98cb9ae8 | 343 | /// The information in this structure defines attributes of the system's mechanical enclosure(s). \r |
344 | /// For example, if a system included a separate enclosure for its peripheral devices, \r | |
345 | /// two structures would be returned: one for the main, system enclosure and the second for\r | |
346 | /// the peripheral device enclosure. The additions to this structure in v2.1 of this specification\r | |
347 | /// support the population of the CIM_Chassis class. \r | |
348 | ///\r | |
61ce5861 | 349 | typedef struct {\r |
98cb9ae8 | 350 | SMBIOS_STRUCTURE Hdr;\r |
351 | SMBIOS_TABLE_STRING Manufacturer;\r | |
352 | UINT8 Type;\r | |
353 | SMBIOS_TABLE_STRING Version;\r | |
354 | SMBIOS_TABLE_STRING SerialNumber;\r | |
355 | SMBIOS_TABLE_STRING AssetTag;\r | |
af2dc6a7 | 356 | UINT8 BootupState; ///< The enumeration value from MISC_CHASSIS_STATE.\r |
357 | UINT8 PowerSupplyState; ///< The enumeration value from MISC_CHASSIS_STATE.\r | |
358 | UINT8 ThermalState; ///< The enumeration value from MISC_CHASSIS_STATE.\r | |
359 | UINT8 SecurityStatus; ///< The enumeration value from MISC_CHASSIS_SECURITY_STATE.\r | |
98cb9ae8 | 360 | UINT8 OemDefined[4];\r |
361 | UINT8 Height;\r | |
362 | UINT8 NumberofPowerCords;\r | |
363 | UINT8 ContainedElementCount;\r | |
364 | UINT8 ContainedElementRecordLength;\r | |
365 | CONTAINED_ELEMENT ContainedElements[1];\r | |
61ce5861 | 366 | } SMBIOS_TABLE_TYPE3;\r |
367 | \r | |
98cb9ae8 | 368 | ///\r |
af2dc6a7 | 369 | /// Processor Information - Processor Type.\r |
98cb9ae8 | 370 | ///\r |
371 | typedef enum {\r | |
372 | ProcessorOther = 0x01,\r | |
373 | ProcessorUnknown = 0x02,\r | |
374 | CentralProcessor = 0x03,\r | |
375 | MathProcessor = 0x04,\r | |
376 | DspProcessor = 0x05,\r | |
377 | VideoProcessor = 0x06\r | |
378 | } PROCESSOR_TYPE_DATA;\r | |
379 | \r | |
380 | ///\r | |
af2dc6a7 | 381 | /// Processor Information - Processor Family.\r |
98cb9ae8 | 382 | ///\r |
383 | typedef enum {\r | |
384 | ProcessorFamilyOther = 0x01, \r | |
385 | ProcessorFamilyUnknown = 0x02,\r | |
386 | ProcessorFamily8086 = 0x03, \r | |
387 | ProcessorFamily80286 = 0x04,\r | |
388 | ProcessorFamilyIntel386 = 0x05, \r | |
389 | ProcessorFamilyIntel486 = 0x06,\r | |
390 | ProcessorFamily8087 = 0x07,\r | |
391 | ProcessorFamily80287 = 0x08,\r | |
392 | ProcessorFamily80387 = 0x09, \r | |
393 | ProcessorFamily80487 = 0x0A,\r | |
394 | ProcessorFamilyPentium = 0x0B, \r | |
395 | ProcessorFamilyPentiumPro = 0x0C,\r | |
396 | ProcessorFamilyPentiumII = 0x0D,\r | |
397 | ProcessorFamilyPentiumMMX = 0x0E,\r | |
398 | ProcessorFamilyCeleron = 0x0F,\r | |
399 | ProcessorFamilyPentiumIIXeon = 0x10,\r | |
400 | ProcessorFamilyPentiumIII = 0x11, \r | |
401 | ProcessorFamilyM1 = 0x12,\r | |
402 | ProcessorFamilyM2 = 0x13,\r | |
119c1688 SZ |
403 | ProcessorFamilyIntelCeleronM = 0x14,\r |
404 | ProcessorFamilyIntelPentium4Ht = 0x15,\r | |
98cb9ae8 | 405 | ProcessorFamilyAmdDuron = 0x18,\r |
406 | ProcessorFamilyK5 = 0x19, \r | |
407 | ProcessorFamilyK6 = 0x1A,\r | |
408 | ProcessorFamilyK6_2 = 0x1B,\r | |
409 | ProcessorFamilyK6_3 = 0x1C,\r | |
410 | ProcessorFamilyAmdAthlon = 0x1D,\r | |
411 | ProcessorFamilyAmd29000 = 0x1E,\r | |
412 | ProcessorFamilyK6_2Plus = 0x1F,\r | |
413 | ProcessorFamilyPowerPC = 0x20,\r | |
414 | ProcessorFamilyPowerPC601 = 0x21,\r | |
415 | ProcessorFamilyPowerPC603 = 0x22,\r | |
416 | ProcessorFamilyPowerPC603Plus = 0x23,\r | |
417 | ProcessorFamilyPowerPC604 = 0x24,\r | |
418 | ProcessorFamilyPowerPC620 = 0x25,\r | |
419 | ProcessorFamilyPowerPCx704 = 0x26,\r | |
420 | ProcessorFamilyPowerPC750 = 0x27,\r | |
3507ab19 | 421 | ProcessorFamilyIntelCoreDuo = 0x28,\r |
422 | ProcessorFamilyIntelCoreDuoMobile = 0x29,\r | |
423 | ProcessorFamilyIntelCoreSoloMobile = 0x2A,\r | |
424 | ProcessorFamilyIntelAtom = 0x2B,\r | |
98cb9ae8 | 425 | ProcessorFamilyAlpha3 = 0x30,\r |
426 | ProcessorFamilyAlpha21064 = 0x31,\r | |
427 | ProcessorFamilyAlpha21066 = 0x32,\r | |
428 | ProcessorFamilyAlpha21164 = 0x33,\r | |
429 | ProcessorFamilyAlpha21164PC = 0x34,\r | |
430 | ProcessorFamilyAlpha21164a = 0x35,\r | |
431 | ProcessorFamilyAlpha21264 = 0x36,\r | |
432 | ProcessorFamilyAlpha21364 = 0x37,\r | |
7ddba202 SZ |
433 | ProcessorFamilyAmdTurionIIUltraDualCoreMobileM = 0x38,\r |
434 | ProcessorFamilyAmdTurionIIDualCoreMobileM = 0x39,\r | |
435 | ProcessorFamilyAmdAthlonIIDualCoreM = 0x3A,\r | |
436 | ProcessorFamilyAmdOpteron6100Series = 0x3B,\r | |
437 | ProcessorFamilyAmdOpteron4100Series = 0x3C,\r | |
438 | ProcessorFamilyAmdOpteron6200Series = 0x3D,\r | |
439 | ProcessorFamilyAmdOpteron4200Series = 0x3E,\r | |
98cb9ae8 | 440 | ProcessorFamilyMips = 0x40,\r |
441 | ProcessorFamilyMIPSR4000 = 0x41,\r | |
442 | ProcessorFamilyMIPSR4200 = 0x42,\r | |
443 | ProcessorFamilyMIPSR4400 = 0x43,\r | |
444 | ProcessorFamilyMIPSR4600 = 0x44,\r | |
445 | ProcessorFamilyMIPSR10000 = 0x45,\r | |
7ddba202 SZ |
446 | ProcessorFamilyAmdCSeries = 0x46,\r |
447 | ProcessorFamilyAmdESeries = 0x47,\r | |
448 | ProcessorFamilyAmdSSeries = 0x48,\r | |
449 | ProcessorFamilyAmdGSeries = 0x49,\r | |
98cb9ae8 | 450 | ProcessorFamilySparc = 0x50,\r |
451 | ProcessorFamilySuperSparc = 0x51,\r | |
452 | ProcessorFamilymicroSparcII = 0x52,\r | |
453 | ProcessorFamilymicroSparcIIep = 0x53,\r | |
454 | ProcessorFamilyUltraSparc = 0x54,\r | |
455 | ProcessorFamilyUltraSparcII = 0x55,\r | |
456 | ProcessorFamilyUltraSparcIIi = 0x56,\r | |
457 | ProcessorFamilyUltraSparcIII = 0x57,\r | |
458 | ProcessorFamilyUltraSparcIIIi = 0x58,\r | |
459 | ProcessorFamily68040 = 0x60,\r | |
460 | ProcessorFamily68xxx = 0x61,\r | |
461 | ProcessorFamily68000 = 0x62,\r | |
462 | ProcessorFamily68010 = 0x63,\r | |
463 | ProcessorFamily68020 = 0x64,\r | |
464 | ProcessorFamily68030 = 0x65,\r | |
465 | ProcessorFamilyHobbit = 0x70,\r | |
466 | ProcessorFamilyCrusoeTM5000 = 0x78,\r | |
467 | ProcessorFamilyCrusoeTM3000 = 0x79,\r | |
468 | ProcessorFamilyEfficeonTM8000 = 0x7A,\r | |
469 | ProcessorFamilyWeitek = 0x80,\r | |
470 | ProcessorFamilyItanium = 0x82,\r | |
471 | ProcessorFamilyAmdAthlon64 = 0x83,\r | |
472 | ProcessorFamilyAmdOpteron = 0x84,\r | |
473 | ProcessorFamilyAmdSempron = 0x85,\r | |
474 | ProcessorFamilyAmdTurion64Mobile = 0x86,\r | |
475 | ProcessorFamilyDualCoreAmdOpteron = 0x87,\r | |
476 | ProcessorFamilyAmdAthlon64X2DualCore = 0x88,\r | |
477 | ProcessorFamilyAmdTurion64X2Mobile = 0x89,\r | |
3507ab19 | 478 | ProcessorFamilyQuadCoreAmdOpteron = 0x8A,\r |
479 | ProcessorFamilyThirdGenerationAmdOpteron = 0x8B,\r | |
480 | ProcessorFamilyAmdPhenomFxQuadCore = 0x8C,\r | |
481 | ProcessorFamilyAmdPhenomX4QuadCore = 0x8D,\r | |
482 | ProcessorFamilyAmdPhenomX2DualCore = 0x8E,\r | |
483 | ProcessorFamilyAmdAthlonX2DualCore = 0x8F, \r | |
98cb9ae8 | 484 | ProcessorFamilyPARISC = 0x90,\r |
485 | ProcessorFamilyPaRisc8500 = 0x91,\r | |
486 | ProcessorFamilyPaRisc8000 = 0x92,\r | |
487 | ProcessorFamilyPaRisc7300LC = 0x93,\r | |
488 | ProcessorFamilyPaRisc7200 = 0x94,\r | |
489 | ProcessorFamilyPaRisc7100LC = 0x95,\r | |
490 | ProcessorFamilyPaRisc7100 = 0x96,\r | |
491 | ProcessorFamilyV30 = 0xA0,\r | |
3507ab19 | 492 | ProcessorFamilyQuadCoreIntelXeon3200Series = 0xA1,\r |
493 | ProcessorFamilyDualCoreIntelXeon3000Series = 0xA2,\r | |
494 | ProcessorFamilyQuadCoreIntelXeon5300Series = 0xA3,\r | |
495 | ProcessorFamilyDualCoreIntelXeon5100Series = 0xA4,\r | |
496 | ProcessorFamilyDualCoreIntelXeon5000Series = 0xA5,\r | |
497 | ProcessorFamilyDualCoreIntelXeonLV = 0xA6,\r | |
498 | ProcessorFamilyDualCoreIntelXeonULV = 0xA7,\r | |
499 | ProcessorFamilyDualCoreIntelXeon7100Series = 0xA8,\r | |
500 | ProcessorFamilyQuadCoreIntelXeon5400Series = 0xA9,\r | |
501 | ProcessorFamilyQuadCoreIntelXeon = 0xAA,\r | |
502 | ProcessorFamilyDualCoreIntelXeon5200Series = 0xAB,\r | |
503 | ProcessorFamilyDualCoreIntelXeon7200Series = 0xAC,\r | |
504 | ProcessorFamilyQuadCoreIntelXeon7300Series = 0xAD,\r | |
505 | ProcessorFamilyQuadCoreIntelXeon7400Series = 0xAE,\r | |
506 | ProcessorFamilyMultiCoreIntelXeon7400Series = 0xAF,\r | |
98cb9ae8 | 507 | ProcessorFamilyPentiumIIIXeon = 0xB0,\r |
508 | ProcessorFamilyPentiumIIISpeedStep = 0xB1,\r | |
509 | ProcessorFamilyPentium4 = 0xB2,\r | |
510 | ProcessorFamilyIntelXeon = 0xB3,\r | |
511 | ProcessorFamilyAS400 = 0xB4,\r | |
512 | ProcessorFamilyIntelXeonMP = 0xB5,\r | |
513 | ProcessorFamilyAMDAthlonXP = 0xB6,\r | |
514 | ProcessorFamilyAMDAthlonMP = 0xB7,\r | |
515 | ProcessorFamilyIntelItanium2 = 0xB8,\r | |
516 | ProcessorFamilyIntelPentiumM = 0xB9,\r | |
517 | ProcessorFamilyIntelCeleronD = 0xBA,\r | |
518 | ProcessorFamilyIntelPentiumD = 0xBB,\r | |
519 | ProcessorFamilyIntelPentiumEx = 0xBC,\r | |
6800ac83 | 520 | ProcessorFamilyIntelCoreSolo = 0xBD, ///< SMBIOS spec 2.6 correct this value\r |
98cb9ae8 | 521 | ProcessorFamilyReserved = 0xBE,\r |
522 | ProcessorFamilyIntelCore2 = 0xBF,\r | |
3507ab19 | 523 | ProcessorFamilyIntelCore2Solo = 0xC0,\r |
524 | ProcessorFamilyIntelCore2Extreme = 0xC1,\r | |
525 | ProcessorFamilyIntelCore2Quad = 0xC2,\r | |
526 | ProcessorFamilyIntelCore2ExtremeMobile = 0xC3,\r | |
527 | ProcessorFamilyIntelCore2DuoMobile = 0xC4,\r | |
528 | ProcessorFamilyIntelCore2SoloMobile = 0xC5,\r | |
529 | ProcessorFamilyIntelCoreI7 = 0xC6,\r | |
530 | ProcessorFamilyDualCoreIntelCeleron = 0xC7, \r | |
98cb9ae8 | 531 | ProcessorFamilyIBM390 = 0xC8,\r |
532 | ProcessorFamilyG4 = 0xC9,\r | |
533 | ProcessorFamilyG5 = 0xCA,\r | |
534 | ProcessorFamilyG6 = 0xCB,\r | |
535 | ProcessorFamilyzArchitectur = 0xCC,\r | |
7ddba202 SZ |
536 | ProcessorFamilyIntelCoreI5 = 0xCD,\r |
537 | ProcessorFamilyIntelCoreI3 = 0xCE,\r | |
98cb9ae8 | 538 | ProcessorFamilyViaC7M = 0xD2,\r |
539 | ProcessorFamilyViaC7D = 0xD3,\r | |
540 | ProcessorFamilyViaC7 = 0xD4,\r | |
541 | ProcessorFamilyViaEden = 0xD5,\r | |
3507ab19 | 542 | ProcessorFamilyMultiCoreIntelXeon = 0xD6,\r |
543 | ProcessorFamilyDualCoreIntelXeon3Series = 0xD7,\r | |
544 | ProcessorFamilyQuadCoreIntelXeon3Series = 0xD8,\r | |
7ddba202 | 545 | ProcessorFamilyViaNano = 0xD9,\r |
3507ab19 | 546 | ProcessorFamilyDualCoreIntelXeon5Series = 0xDA,\r |
547 | ProcessorFamilyQuadCoreIntelXeon5Series = 0xDB,\r | |
548 | ProcessorFamilyDualCoreIntelXeon7Series = 0xDD,\r | |
549 | ProcessorFamilyQuadCoreIntelXeon7Series = 0xDE,\r | |
550 | ProcessorFamilyMultiCoreIntelXeon7Series = 0xDF,\r | |
7ddba202 | 551 | ProcessorFamilyMultiCoreIntelXeon3400Series = 0xE0,\r |
3507ab19 | 552 | ProcessorFamilyEmbeddedAmdOpteronQuadCore = 0xE6,\r |
553 | ProcessorFamilyAmdPhenomTripleCore = 0xE7,\r | |
554 | ProcessorFamilyAmdTurionUltraDualCoreMobile = 0xE8,\r | |
555 | ProcessorFamilyAmdTurionDualCoreMobile = 0xE9,\r | |
556 | ProcessorFamilyAmdAthlonDualCore = 0xEA,\r | |
557 | ProcessorFamilyAmdSempronSI = 0xEB,\r | |
7ddba202 SZ |
558 | ProcessorFamilyAmdPhenomII = 0xEC,\r |
559 | ProcessorFamilyAmdAthlonII = 0xED,\r | |
560 | ProcessorFamilySixCoreAmdOpteron = 0xEE,\r | |
561 | ProcessorFamilyAmdSempronM = 0xEF,\r | |
98cb9ae8 | 562 | ProcessorFamilyi860 = 0xFA,\r |
563 | ProcessorFamilyi960 = 0xFB,\r | |
564 | ProcessorFamilyIndicatorFamily2 = 0xFE,\r | |
565 | ProcessorFamilyReserved1 = 0xFF\r | |
566 | } PROCESSOR_FAMILY_DATA;\r | |
567 | \r | |
568 | ///\r | |
af2dc6a7 | 569 | /// Processor Information - Voltage. \r |
98cb9ae8 | 570 | ///\r |
571 | typedef struct {\r | |
6800ac83 | 572 | UINT8 ProcessorVoltageCapability5V :1; \r |
573 | UINT8 ProcessorVoltageCapability3_3V :1; \r | |
574 | UINT8 ProcessorVoltageCapability2_9V :1; \r | |
575 | UINT8 ProcessorVoltageCapabilityReserved :1; ///< Bit 3, must be zero.\r | |
576 | UINT8 ProcessorVoltageReserved :3; ///< Bits 4-6, must be zero.\r | |
577 | UINT8 ProcessorVoltageIndicateLegacy :1;\r | |
98cb9ae8 | 578 | } PROCESSOR_VOLTAGE;\r |
579 | \r | |
580 | ///\r | |
af2dc6a7 | 581 | /// Processor Information - Processor Upgrade.\r |
98cb9ae8 | 582 | ///\r |
583 | typedef enum {\r | |
584 | ProcessorUpgradeOther = 0x01,\r | |
585 | ProcessorUpgradeUnknown = 0x02,\r | |
586 | ProcessorUpgradeDaughterBoard = 0x03,\r | |
587 | ProcessorUpgradeZIFSocket = 0x04,\r | |
af2dc6a7 | 588 | ProcessorUpgradePiggyBack = 0x05, ///< Replaceable.\r |
98cb9ae8 | 589 | ProcessorUpgradeNone = 0x06,\r |
590 | ProcessorUpgradeLIFSocket = 0x07,\r | |
591 | ProcessorUpgradeSlot1 = 0x08,\r | |
592 | ProcessorUpgradeSlot2 = 0x09,\r | |
593 | ProcessorUpgrade370PinSocket = 0x0A,\r | |
594 | ProcessorUpgradeSlotA = 0x0B,\r | |
595 | ProcessorUpgradeSlotM = 0x0C,\r | |
596 | ProcessorUpgradeSocket423 = 0x0D,\r | |
af2dc6a7 | 597 | ProcessorUpgradeSocketA = 0x0E, ///< Socket 462.\r |
98cb9ae8 | 598 | ProcessorUpgradeSocket478 = 0x0F,\r |
599 | ProcessorUpgradeSocket754 = 0x10,\r | |
600 | ProcessorUpgradeSocket940 = 0x11,\r | |
601 | ProcessorUpgradeSocket939 = 0x12,\r | |
602 | ProcessorUpgradeSocketmPGA604 = 0x13,\r | |
603 | ProcessorUpgradeSocketLGA771 = 0x14,\r | |
604 | ProcessorUpgradeSocketLGA775 = 0x15,\r | |
605 | ProcessorUpgradeSocketS1 = 0x16,\r | |
606 | ProcessorUpgradeAM2 = 0x17,\r | |
3507ab19 | 607 | ProcessorUpgradeF1207 = 0x18,\r |
7ddba202 SZ |
608 | ProcessorSocketLGA1366 = 0x19,\r |
609 | ProcessorUpgradeSocketG34 = 0x1A,\r | |
610 | ProcessorUpgradeSocketAM3 = 0x1B,\r | |
611 | ProcessorUpgradeSocketC32 = 0x1C,\r | |
612 | ProcessorUpgradeSocketLGA1156 = 0x1D,\r | |
613 | ProcessorUpgradeSocketLGA1567 = 0x1E,\r | |
614 | ProcessorUpgradeSocketPGA988A = 0x1F,\r | |
615 | ProcessorUpgradeSocketBGA1288 = 0x20,\r | |
616 | ProcessorUpgradeSocketrPGA988B = 0x21,\r | |
617 | ProcessorUpgradeSocketBGA1023 = 0x22,\r | |
618 | ProcessorUpgradeSocketBGA1224 = 0x23,\r | |
619 | ProcessorUpgradeSocketBGA1155 = 0x24,\r | |
620 | ProcessorUpgradeSocketLGA1356 = 0x25,\r | |
621 | ProcessorUpgradeSocketLGA2011 = 0x26,\r | |
622 | ProcessorUpgradeSocketFS1 = 0x27,\r | |
623 | ProcessorUpgradeSocketFS2 = 0x28,\r | |
624 | ProcessorUpgradeSocketFM1 = 0x29,\r | |
625 | ProcessorUpgradeSocketFM2 = 0x2A\r | |
98cb9ae8 | 626 | } PROCESSOR_UPGRADE;\r |
627 | \r | |
628 | ///\r | |
629 | /// Processor ID Field Description\r | |
630 | ///\r | |
631 | typedef struct {\r | |
632 | UINT32 ProcessorSteppingId:4;\r | |
633 | UINT32 ProcessorModel: 4;\r | |
634 | UINT32 ProcessorFamily: 4;\r | |
635 | UINT32 ProcessorType: 2;\r | |
636 | UINT32 ProcessorReserved1: 2;\r | |
637 | UINT32 ProcessorXModel: 4;\r | |
638 | UINT32 ProcessorXFamily: 8;\r | |
639 | UINT32 ProcessorReserved2: 4;\r | |
640 | } PROCESSOR_SIGNATURE;\r | |
641 | \r | |
98cb9ae8 | 642 | typedef struct {\r |
643 | UINT32 ProcessorFpu :1;\r | |
644 | UINT32 ProcessorVme :1;\r | |
645 | UINT32 ProcessorDe :1;\r | |
646 | UINT32 ProcessorPse :1;\r | |
647 | UINT32 ProcessorTsc :1;\r | |
648 | UINT32 ProcessorMsr :1;\r | |
649 | UINT32 ProcessorPae :1;\r | |
650 | UINT32 ProcessorMce :1;\r | |
651 | UINT32 ProcessorCx8 :1;\r | |
652 | UINT32 ProcessorApic :1;\r | |
653 | UINT32 ProcessorReserved1 :1;\r | |
654 | UINT32 ProcessorSep :1;\r | |
655 | UINT32 ProcessorMtrr :1;\r | |
656 | UINT32 ProcessorPge :1;\r | |
657 | UINT32 ProcessorMca :1;\r | |
658 | UINT32 ProcessorCmov :1;\r | |
659 | UINT32 ProcessorPat :1;\r | |
660 | UINT32 ProcessorPse36 :1;\r | |
661 | UINT32 ProcessorPsn :1;\r | |
662 | UINT32 ProcessorClfsh :1;\r | |
663 | UINT32 ProcessorReserved2 :1;\r | |
664 | UINT32 ProcessorDs :1;\r | |
665 | UINT32 ProcessorAcpi :1;\r | |
666 | UINT32 ProcessorMmx :1;\r | |
667 | UINT32 ProcessorFxsr :1;\r | |
668 | UINT32 ProcessorSse :1;\r | |
669 | UINT32 ProcessorSse2 :1;\r | |
670 | UINT32 ProcessorSs :1;\r | |
671 | UINT32 ProcessorReserved3 :1;\r | |
672 | UINT32 ProcessorTm :1;\r | |
673 | UINT32 ProcessorReserved4 :2;\r | |
674 | } PROCESSOR_FEATURE_FLAGS;\r | |
675 | \r | |
676 | typedef struct {\r | |
677 | PROCESSOR_SIGNATURE Signature;\r | |
98cb9ae8 | 678 | PROCESSOR_FEATURE_FLAGS FeatureFlags;\r |
6800ac83 | 679 | } PROCESSOR_ID_DATA;\r |
98cb9ae8 | 680 | \r |
4135253b | 681 | ///\r |
af2dc6a7 | 682 | /// Processor Information (Type 4).\r |
4135253b | 683 | ///\r |
98cb9ae8 | 684 | /// The information in this structure defines the attributes of a single processor; \r |
685 | /// a separate structure instance is provided for each system processor socket/slot. \r | |
686 | /// For example, a system with an IntelDX2 processor would have a single \r | |
af2dc6a7 | 687 | /// structure instance, while a system with an IntelSX2 processor would have a structure\r |
688 | /// to describe the main CPU, and a second structure to describe the 80487 co-processor. \r | |
98cb9ae8 | 689 | ///\r |
61ce5861 | 690 | typedef struct { \r |
691 | SMBIOS_STRUCTURE Hdr;\r | |
2d5e30ef | 692 | SMBIOS_TABLE_STRING Socket;\r |
af2dc6a7 | 693 | UINT8 ProcessorType; ///< The enumeration value from PROCESSOR_TYPE_DATA.\r |
694 | UINT8 ProcessorFamily; ///< The enumeration value from PROCESSOR_FAMILY_DATA.\r | |
61ce5861 | 695 | SMBIOS_TABLE_STRING ProcessorManufacture;\r |
98cb9ae8 | 696 | PROCESSOR_ID_DATA ProcessorId;\r |
61ce5861 | 697 | SMBIOS_TABLE_STRING ProcessorVersion;\r |
98cb9ae8 | 698 | PROCESSOR_VOLTAGE Voltage;\r |
61ce5861 | 699 | UINT16 ExternalClock;\r |
700 | UINT16 MaxSpeed;\r | |
701 | UINT16 CurrentSpeed;\r | |
702 | UINT8 Status;\r | |
af2dc6a7 | 703 | UINT8 ProcessorUpgrade; ///< The enumeration value from PROCESSOR_UPGRADE.\r |
61ce5861 | 704 | UINT16 L1CacheHandle;\r |
705 | UINT16 L2CacheHandle;\r | |
706 | UINT16 L3CacheHandle;\r | |
707 | SMBIOS_TABLE_STRING SerialNumber;\r | |
708 | SMBIOS_TABLE_STRING AssetTag;\r | |
709 | SMBIOS_TABLE_STRING PartNumber;\r | |
710 | //\r | |
711 | // Add for smbios 2.5\r | |
712 | //\r | |
713 | UINT8 CoreCount;\r | |
714 | UINT8 EnabledCoreCount;\r | |
715 | UINT8 ThreadCount;\r | |
716 | UINT16 ProcessorCharacteristics;\r | |
717 | //\r | |
718 | // Add for smbios 2.6\r | |
719 | //\r | |
720 | UINT16 ProcessorFamily2;\r | |
721 | } SMBIOS_TABLE_TYPE4;\r | |
722 | \r | |
98cb9ae8 | 723 | ///\r |
af2dc6a7 | 724 | /// Memory Controller Error Detecting Method.\r |
98cb9ae8 | 725 | ///\r |
726 | typedef enum { \r | |
727 | ErrorDetectingMethodOther = 0x01,\r | |
728 | ErrorDetectingMethodUnknown = 0x02,\r | |
729 | ErrorDetectingMethodNone = 0x03,\r | |
730 | ErrorDetectingMethodParity = 0x04,\r | |
731 | ErrorDetectingMethod32Ecc = 0x05,\r | |
732 | ErrorDetectingMethod64Ecc = 0x06,\r | |
733 | ErrorDetectingMethod128Ecc = 0x07,\r | |
734 | ErrorDetectingMethodCrc = 0x08\r | |
735 | } MEMORY_ERROR_DETECT_METHOD;\r | |
736 | \r | |
737 | ///\r | |
af2dc6a7 | 738 | /// Memory Controller Error Correcting Capability.\r |
98cb9ae8 | 739 | ///\r |
740 | typedef struct {\r | |
741 | UINT8 Other :1;\r | |
742 | UINT8 Unknown :1;\r | |
743 | UINT8 None :1;\r | |
744 | UINT8 SingleBitErrorCorrect :1;\r | |
745 | UINT8 DoubleBitErrorCorrect :1;\r | |
746 | UINT8 ErrorScrubbing :1;\r | |
747 | UINT8 Reserved :2;\r | |
748 | } MEMORY_ERROR_CORRECT_CAPABILITY;\r | |
749 | \r | |
750 | ///\r | |
af2dc6a7 | 751 | /// Memory Controller Information - Interleave Support.\r |
98cb9ae8 | 752 | ///\r |
753 | typedef enum { \r | |
754 | MemoryInterleaveOther = 0x01,\r | |
755 | MemoryInterleaveUnknown = 0x02,\r | |
756 | MemoryInterleaveOneWay = 0x03,\r | |
757 | MemoryInterleaveTwoWay = 0x04,\r | |
758 | MemoryInterleaveFourWay = 0x05,\r | |
759 | MemoryInterleaveEightWay = 0x06,\r | |
760 | MemoryInterleaveSixteenWay = 0x07\r | |
761 | } MEMORY_SUPPORT_INTERLEAVE_TYPE;\r | |
762 | \r | |
763 | ///\r | |
af2dc6a7 | 764 | /// Memory Controller Information - Memory Speeds.\r |
98cb9ae8 | 765 | ///\r |
766 | typedef struct {\r | |
767 | UINT16 Other :1;\r | |
768 | UINT16 Unknown :1;\r | |
769 | UINT16 SeventyNs:1;\r | |
770 | UINT16 SixtyNs :1;\r | |
771 | UINT16 FiftyNs :1;\r | |
772 | UINT16 Reserved :11;\r | |
773 | } MEMORY_SPEED_TYPE;\r | |
774 | \r | |
4135253b | 775 | ///\r |
af2dc6a7 | 776 | /// Memory Controller Information (Type 5, Obsolete).\r |
4135253b | 777 | ///\r |
98cb9ae8 | 778 | /// The information in this structure defines the attributes of the system's memory controller(s) \r |
779 | /// and the supported attributes of any memory-modules present in the sockets controlled by \r | |
780 | /// this controller. \r | |
781 | /// Note: This structure, and its companion Memory Module Information (Type 6, Obsolete), \r | |
af2dc6a7 | 782 | /// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)\r |
98cb9ae8 | 783 | /// and Memory Device (Type 17) structures should be used instead. BIOS providers might\r |
784 | /// choose to implement both memory description types to allow existing DMI browsers\r | |
785 | /// to properly display the system's memory attributes.\r | |
786 | ///\r | |
61ce5861 | 787 | typedef struct {\r |
98cb9ae8 | 788 | SMBIOS_STRUCTURE Hdr;\r |
af2dc6a7 | 789 | UINT8 ErrDetectMethod; ///< The enumeration value from MEMORY_ERROR_DETECT_METHOD.\r |
98cb9ae8 | 790 | MEMORY_ERROR_CORRECT_CAPABILITY ErrCorrectCapability;\r |
af2dc6a7 | 791 | UINT8 SupportInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE.\r |
792 | UINT8 CurrentInterleave; ///< The enumeration value from MEMORY_SUPPORT_INTERLEAVE_TYPE . \r | |
98cb9ae8 | 793 | UINT8 MaxMemoryModuleSize;\r |
794 | MEMORY_SPEED_TYPE SupportSpeed;\r | |
795 | UINT16 SupportMemoryType;\r | |
796 | UINT8 MemoryModuleVoltage;\r | |
797 | UINT8 AssociatedMemorySlotNum;\r | |
798 | UINT16 MemoryModuleConfigHandles[1];\r | |
61ce5861 | 799 | } SMBIOS_TABLE_TYPE5;\r |
800 | \r | |
98cb9ae8 | 801 | ///\r |
802 | /// Memory Module Information - Memory Types\r | |
803 | ///\r | |
804 | typedef struct {\r | |
805 | UINT16 Other :1;\r | |
806 | UINT16 Unknown :1;\r | |
807 | UINT16 Standard :1;\r | |
808 | UINT16 FastPageMode:1;\r | |
b4ab47ec | 809 | UINT16 Edo :1;\r |
98cb9ae8 | 810 | UINT16 Parity :1;\r |
b4ab47ec | 811 | UINT16 Ecc :1;\r |
812 | UINT16 Simm :1;\r | |
813 | UINT16 Dimm :1;\r | |
98cb9ae8 | 814 | UINT16 BurstEdo :1;\r |
b4ab47ec | 815 | UINT16 Sdram :1;\r |
98cb9ae8 | 816 | UINT16 Reserved :5;\r |
817 | } MEMORY_CURRENT_TYPE;\r | |
818 | \r | |
819 | ///\r | |
af2dc6a7 | 820 | /// Memory Module Information - Memory Size.\r |
98cb9ae8 | 821 | ///\r |
822 | typedef struct {\r | |
6800ac83 | 823 | UINT8 InstalledOrEnabledSize :7; ///< Size (n), where 2**n is the size in MB.\r |
98cb9ae8 | 824 | UINT8 SingleOrDoubleBank :1;\r |
825 | } MEMORY_INSTALLED_ENABLED_SIZE;\r | |
826 | \r | |
4135253b | 827 | ///\r |
828 | /// Memory Module Information (Type 6, Obsolete)\r | |
829 | ///\r | |
98cb9ae8 | 830 | /// One Memory Module Information structure is included for each memory-module socket \r |
831 | /// in the system. The structure describes the speed, type, size, and error status\r | |
832 | /// of each system memory module. The supported attributes of each module are described \r | |
833 | /// by the "owning" Memory Controller Information structure. \r | |
834 | /// Note: This structure, and its companion Memory Controller Information (Type 5, Obsolete), \r | |
af2dc6a7 | 835 | /// are obsolete starting with version 2.1 of this specification. The Physical Memory Array (Type 16)\r |
98cb9ae8 | 836 | /// and Memory Device (Type 17) structures should be used instead.\r |
837 | ///\r | |
61ce5861 | 838 | typedef struct {\r |
98cb9ae8 | 839 | SMBIOS_STRUCTURE Hdr;\r |
840 | SMBIOS_TABLE_STRING SocketDesignation;\r | |
841 | UINT8 BankConnections;\r | |
842 | UINT8 CurrentSpeed;\r | |
843 | MEMORY_CURRENT_TYPE CurrentMemoryType;\r | |
844 | MEMORY_INSTALLED_ENABLED_SIZE InstalledSize;\r | |
845 | MEMORY_INSTALLED_ENABLED_SIZE EnabledSize;\r | |
846 | UINT8 ErrorStatus;\r | |
61ce5861 | 847 | } SMBIOS_TABLE_TYPE6;\r |
848 | \r | |
98cb9ae8 | 849 | ///\r |
af2dc6a7 | 850 | /// Cache Information - SRAM Type.\r |
98cb9ae8 | 851 | ///\r |
852 | typedef struct {\r | |
853 | UINT16 Other :1;\r | |
854 | UINT16 Unknown :1;\r | |
855 | UINT16 NonBurst :1;\r | |
856 | UINT16 Burst :1;\r | |
857 | UINT16 PipelineBurst :1;\r | |
98cb9ae8 | 858 | UINT16 Synchronous :1;\r |
53d90f04 | 859 | UINT16 Asynchronous :1;\r |
98cb9ae8 | 860 | UINT16 Reserved :9;\r |
861 | } CACHE_SRAM_TYPE_DATA;\r | |
862 | \r | |
863 | ///\r | |
af2dc6a7 | 864 | /// Cache Information - Error Correction Type.\r |
98cb9ae8 | 865 | ///\r |
866 | typedef enum {\r | |
867 | CacheErrorOther = 0x01,\r | |
868 | CacheErrorUnknown = 0x02,\r | |
869 | CacheErrorNone = 0x03,\r | |
870 | CacheErrorParity = 0x04,\r | |
6800ac83 | 871 | CacheErrorSingleBit = 0x05, ///< ECC\r |
872 | CacheErrorMultiBit = 0x06 ///< ECC\r | |
98cb9ae8 | 873 | } CACHE_ERROR_TYPE_DATA;\r |
874 | \r | |
875 | ///\r | |
af2dc6a7 | 876 | /// Cache Information - System Cache Type. \r |
98cb9ae8 | 877 | ///\r |
878 | typedef enum {\r | |
879 | CacheTypeOther = 0x01,\r | |
880 | CacheTypeUnknown = 0x02,\r | |
881 | CacheTypeInstruction = 0x03,\r | |
882 | CacheTypeData = 0x04,\r | |
883 | CacheTypeUnified = 0x05\r | |
884 | } CACHE_TYPE_DATA;\r | |
885 | \r | |
886 | ///\r | |
af2dc6a7 | 887 | /// Cache Information - Associativity. \r |
98cb9ae8 | 888 | ///\r |
889 | typedef enum {\r | |
890 | CacheAssociativityOther = 0x01,\r | |
891 | CacheAssociativityUnknown = 0x02,\r | |
892 | CacheAssociativityDirectMapped = 0x03,\r | |
893 | CacheAssociativity2Way = 0x04,\r | |
894 | CacheAssociativity4Way = 0x05,\r | |
895 | CacheAssociativityFully = 0x06,\r | |
896 | CacheAssociativity8Way = 0x07,\r | |
897 | CacheAssociativity16Way = 0x08,\r | |
3507ab19 | 898 | CacheAssociativity12Way = 0x09,\r |
899 | CacheAssociativity24Way = 0x0A,\r | |
900 | CacheAssociativity32Way = 0x0B,\r | |
901 | CacheAssociativity48Way = 0x0C,\r | |
7ddba202 SZ |
902 | CacheAssociativity64Way = 0x0D,\r |
903 | CacheAssociativity20Way = 0x0E\r | |
98cb9ae8 | 904 | } CACHE_ASSOCIATIVITY_DATA;\r |
905 | \r | |
4135253b | 906 | ///\r |
af2dc6a7 | 907 | /// Cache Information (Type 7).\r |
4135253b | 908 | ///\r |
af2dc6a7 | 909 | /// The information in this structure defines the attributes of CPU cache device in the system. \r |
98cb9ae8 | 910 | /// One structure is specified for each such device, whether the device is internal to\r |
911 | /// or external to the CPU module. Cache modules can be associated with a processor structure\r | |
af2dc6a7 | 912 | /// in one or two ways, depending on the SMBIOS version.\r |
98cb9ae8 | 913 | ///\r |
61ce5861 | 914 | typedef struct {\r |
98cb9ae8 | 915 | SMBIOS_STRUCTURE Hdr;\r |
916 | SMBIOS_TABLE_STRING SocketDesignation;\r | |
917 | UINT16 CacheConfiguration;\r | |
918 | UINT16 MaximumCacheSize;\r | |
919 | UINT16 InstalledSize;\r | |
920 | CACHE_SRAM_TYPE_DATA SupportedSRAMType;\r | |
921 | CACHE_SRAM_TYPE_DATA CurrentSRAMType;\r | |
922 | UINT8 CacheSpeed;\r | |
af2dc6a7 | 923 | UINT8 ErrorCorrectionType; ///< The enumeration value from CACHE_ERROR_TYPE_DATA.\r |
924 | UINT8 SystemCacheType; ///< The enumeration value from CACHE_TYPE_DATA.\r | |
925 | UINT8 Associativity; ///< The enumeration value from CACHE_ASSOCIATIVITY_DATA.\r | |
61ce5861 | 926 | } SMBIOS_TABLE_TYPE7;\r |
927 | \r | |
98cb9ae8 | 928 | ///\r |
af2dc6a7 | 929 | /// Port Connector Information - Connector Types. \r |
98cb9ae8 | 930 | ///\r |
931 | typedef enum {\r | |
932 | PortConnectorTypeNone = 0x00,\r | |
933 | PortConnectorTypeCentronics = 0x01,\r | |
934 | PortConnectorTypeMiniCentronics = 0x02,\r | |
935 | PortConnectorTypeProprietary = 0x03,\r | |
936 | PortConnectorTypeDB25Male = 0x04,\r | |
937 | PortConnectorTypeDB25Female = 0x05,\r | |
938 | PortConnectorTypeDB15Male = 0x06,\r | |
939 | PortConnectorTypeDB15Female = 0x07,\r | |
940 | PortConnectorTypeDB9Male = 0x08,\r | |
941 | PortConnectorTypeDB9Female = 0x09,\r | |
942 | PortConnectorTypeRJ11 = 0x0A,\r | |
943 | PortConnectorTypeRJ45 = 0x0B,\r | |
944 | PortConnectorType50PinMiniScsi = 0x0C,\r | |
945 | PortConnectorTypeMiniDin = 0x0D,\r | |
119c1688 | 946 | PortConnectorTypeMicroDin = 0x0E,\r |
98cb9ae8 | 947 | PortConnectorTypePS2 = 0x0F,\r |
948 | PortConnectorTypeInfrared = 0x10,\r | |
949 | PortConnectorTypeHpHil = 0x11,\r | |
950 | PortConnectorTypeUsb = 0x12,\r | |
951 | PortConnectorTypeSsaScsi = 0x13,\r | |
952 | PortConnectorTypeCircularDin8Male = 0x14,\r | |
953 | PortConnectorTypeCircularDin8Female = 0x15,\r | |
954 | PortConnectorTypeOnboardIde = 0x16,\r | |
955 | PortConnectorTypeOnboardFloppy = 0x17,\r | |
956 | PortConnectorType9PinDualInline = 0x18,\r | |
957 | PortConnectorType25PinDualInline = 0x19,\r | |
958 | PortConnectorType50PinDualInline = 0x1A,\r | |
959 | PortConnectorType68PinDualInline = 0x1B,\r | |
960 | PortConnectorTypeOnboardSoundInput = 0x1C,\r | |
961 | PortConnectorTypeMiniCentronicsType14 = 0x1D,\r | |
962 | PortConnectorTypeMiniCentronicsType26 = 0x1E,\r | |
963 | PortConnectorTypeHeadPhoneMiniJack = 0x1F,\r | |
964 | PortConnectorTypeBNC = 0x20,\r | |
965 | PortConnectorType1394 = 0x21,\r | |
119c1688 | 966 | PortConnectorTypeSasSata = 0x22,\r |
98cb9ae8 | 967 | PortConnectorTypePC98 = 0xA0,\r |
968 | PortConnectorTypePC98Hireso = 0xA1,\r | |
969 | PortConnectorTypePCH98 = 0xA2,\r | |
970 | PortConnectorTypePC98Note = 0xA3,\r | |
971 | PortConnectorTypePC98Full = 0xA4,\r | |
972 | PortConnectorTypeOther = 0xFF\r | |
973 | } MISC_PORT_CONNECTOR_TYPE;\r | |
974 | \r | |
975 | ///\r | |
976 | /// Port Connector Information - Port Types \r | |
977 | ///\r | |
978 | typedef enum {\r | |
979 | PortTypeNone = 0x00,\r | |
980 | PortTypeParallelXtAtCompatible = 0x01,\r | |
981 | PortTypeParallelPortPs2 = 0x02,\r | |
982 | PortTypeParallelPortEcp = 0x03,\r | |
983 | PortTypeParallelPortEpp = 0x04,\r | |
984 | PortTypeParallelPortEcpEpp = 0x05,\r | |
985 | PortTypeSerialXtAtCompatible = 0x06,\r | |
986 | PortTypeSerial16450Compatible = 0x07,\r | |
987 | PortTypeSerial16550Compatible = 0x08,\r | |
988 | PortTypeSerial16550ACompatible = 0x09,\r | |
989 | PortTypeScsi = 0x0A,\r | |
990 | PortTypeMidi = 0x0B,\r | |
991 | PortTypeJoyStick = 0x0C,\r | |
992 | PortTypeKeyboard = 0x0D,\r | |
993 | PortTypeMouse = 0x0E,\r | |
994 | PortTypeSsaScsi = 0x0F,\r | |
995 | PortTypeUsb = 0x10,\r | |
996 | PortTypeFireWire = 0x11,\r | |
997 | PortTypePcmciaTypeI = 0x12,\r | |
998 | PortTypePcmciaTypeII = 0x13,\r | |
999 | PortTypePcmciaTypeIII = 0x14,\r | |
1000 | PortTypeCardBus = 0x15,\r | |
1001 | PortTypeAccessBusPort = 0x16,\r | |
1002 | PortTypeScsiII = 0x17,\r | |
1003 | PortTypeScsiWide = 0x18,\r | |
1004 | PortTypePC98 = 0x19,\r | |
1005 | PortTypePC98Hireso = 0x1A,\r | |
1006 | PortTypePCH98 = 0x1B,\r | |
1007 | PortTypeVideoPort = 0x1C,\r | |
1008 | PortTypeAudioPort = 0x1D,\r | |
1009 | PortTypeModemPort = 0x1E,\r | |
1010 | PortTypeNetworkPort = 0x1F,\r | |
1011 | PortType8251Compatible = 0xA0,\r | |
1012 | PortType8251FifoCompatible = 0xA1,\r | |
1013 | PortTypeOther = 0xFF\r | |
1014 | } MISC_PORT_TYPE;\r | |
1015 | \r | |
4135253b | 1016 | ///\r |
af2dc6a7 | 1017 | /// Port Connector Information (Type 8).\r |
4135253b | 1018 | ///\r |
98cb9ae8 | 1019 | /// The information in this structure defines the attributes of a system port connector, \r |
1f9f8414 | 1020 | /// e.g. parallel, serial, keyboard, or mouse ports. The port's type and connector information \r |
98cb9ae8 | 1021 | /// are provided. One structure is present for each port provided by the system.\r |
1022 | ///\r | |
61ce5861 | 1023 | typedef struct {\r |
98cb9ae8 | 1024 | SMBIOS_STRUCTURE Hdr;\r |
1025 | SMBIOS_TABLE_STRING InternalReferenceDesignator;\r | |
af2dc6a7 | 1026 | UINT8 InternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r |
98cb9ae8 | 1027 | SMBIOS_TABLE_STRING ExternalReferenceDesignator;\r |
af2dc6a7 | 1028 | UINT8 ExternalConnectorType; ///< The enumeration value from MISC_PORT_CONNECTOR_TYPE.\r |
1029 | UINT8 PortType; ///< The enumeration value from MISC_PORT_TYPE.\r | |
61ce5861 | 1030 | } SMBIOS_TABLE_TYPE8;\r |
1031 | \r | |
98cb9ae8 | 1032 | ///\r |
1033 | /// System Slots - Slot Type\r | |
1034 | ///\r | |
1035 | typedef enum {\r | |
1036 | SlotTypeOther = 0x01,\r | |
1037 | SlotTypeUnknown = 0x02,\r | |
1038 | SlotTypeIsa = 0x03,\r | |
1039 | SlotTypeMca = 0x04,\r | |
1040 | SlotTypeEisa = 0x05,\r | |
1041 | SlotTypePci = 0x06,\r | |
1042 | SlotTypePcmcia = 0x07,\r | |
1043 | SlotTypeVlVesa = 0x08,\r | |
1044 | SlotTypeProprietary = 0x09,\r | |
1045 | SlotTypeProcessorCardSlot = 0x0A,\r | |
1046 | SlotTypeProprietaryMemoryCardSlot = 0x0B,\r | |
1047 | SlotTypeIORiserCardSlot = 0x0C,\r | |
1048 | SlotTypeNuBus = 0x0D,\r | |
1049 | SlotTypePci66MhzCapable = 0x0E,\r | |
1050 | SlotTypeAgp = 0x0F,\r | |
1051 | SlotTypeApg2X = 0x10,\r | |
1052 | SlotTypeAgp4X = 0x11,\r | |
1053 | SlotTypePciX = 0x12,\r | |
1054 | SlotTypeAgp4x = 0x13,\r | |
1055 | SlotTypePC98C20 = 0xA0,\r | |
1056 | SlotTypePC98C24 = 0xA1,\r | |
1057 | SlotTypePC98E = 0xA2,\r | |
1058 | SlotTypePC98LocalBus = 0xA3,\r | |
1059 | SlotTypePC98Card = 0xA4,\r | |
1060 | SlotTypePciExpress = 0xA5,\r | |
1061 | SlotTypePciExpressX1 = 0xA6,\r | |
1062 | SlotTypePciExpressX2 = 0xA7,\r | |
1063 | SlotTypePciExpressX4 = 0xA8,\r | |
1064 | SlotTypePciExpressX8 = 0xA9,\r | |
3507ab19 | 1065 | SlotTypePciExpressX16 = 0xAA,\r |
1066 | SlotTypePciExpressGen2 = 0xAB,\r | |
1067 | SlotTypePciExpressGen2X1 = 0xAC,\r | |
1068 | SlotTypePciExpressGen2X2 = 0xAD,\r | |
1069 | SlotTypePciExpressGen2X4 = 0xAE,\r | |
1070 | SlotTypePciExpressGen2X8 = 0xAF,\r | |
7ddba202 SZ |
1071 | SlotTypePciExpressGen2X16 = 0xB0,\r |
1072 | SlotTypePciExpressGen3 = 0xB1,\r | |
1073 | SlotTypePciExpressGen3X1 = 0xB2,\r | |
1074 | SlotTypePciExpressGen3X2 = 0xB3,\r | |
1075 | SlotTypePciExpressGen3X4 = 0xB4,\r | |
1076 | SlotTypePciExpressGen3X8 = 0xB5,\r | |
1077 | SlotTypePciExpressGen3X16 = 0xB6\r | |
98cb9ae8 | 1078 | } MISC_SLOT_TYPE;\r |
1079 | \r | |
1080 | ///\r | |
af2dc6a7 | 1081 | /// System Slots - Slot Data Bus Width.\r |
98cb9ae8 | 1082 | ///\r |
1083 | typedef enum {\r | |
1084 | SlotDataBusWidthOther = 0x01,\r | |
1085 | SlotDataBusWidthUnknown = 0x02,\r | |
1086 | SlotDataBusWidth8Bit = 0x03,\r | |
1087 | SlotDataBusWidth16Bit = 0x04,\r | |
1088 | SlotDataBusWidth32Bit = 0x05,\r | |
1089 | SlotDataBusWidth64Bit = 0x06,\r | |
1090 | SlotDataBusWidth128Bit = 0x07,\r | |
6800ac83 | 1091 | SlotDataBusWidth1X = 0x08, ///< Or X1\r |
1092 | SlotDataBusWidth2X = 0x09, ///< Or X2\r | |
1093 | SlotDataBusWidth4X = 0x0A, ///< Or X4\r | |
1094 | SlotDataBusWidth8X = 0x0B, ///< Or X8\r | |
1095 | SlotDataBusWidth12X = 0x0C, ///< Or X12\r | |
1096 | SlotDataBusWidth16X = 0x0D, ///< Or X16\r | |
1097 | SlotDataBusWidth32X = 0x0E ///< Or X32\r | |
98cb9ae8 | 1098 | } MISC_SLOT_DATA_BUS_WIDTH;\r |
1099 | \r | |
1100 | ///\r | |
af2dc6a7 | 1101 | /// System Slots - Current Usage.\r |
98cb9ae8 | 1102 | ///\r |
1103 | typedef enum {\r | |
1104 | SlotUsageOther = 0x01,\r | |
1105 | SlotUsageUnknown = 0x02,\r | |
1106 | SlotUsageAvailable = 0x03,\r | |
1107 | SlotUsageInUse = 0x04\r | |
1108 | } MISC_SLOT_USAGE;\r | |
1109 | \r | |
1110 | ///\r | |
af2dc6a7 | 1111 | /// System Slots - Slot Length. \r |
98cb9ae8 | 1112 | ///\r |
1113 | typedef enum {\r | |
1114 | SlotLengthOther = 0x01,\r | |
1115 | SlotLengthUnknown = 0x02,\r | |
1116 | SlotLengthShort = 0x03,\r | |
1117 | SlotLengthLong = 0x04\r | |
1118 | } MISC_SLOT_LENGTH;\r | |
1119 | \r | |
1120 | ///\r | |
af2dc6a7 | 1121 | /// System Slots - Slot Characteristics 1. \r |
98cb9ae8 | 1122 | ///\r |
1123 | typedef struct {\r | |
1124 | UINT8 CharacteristicsUnknown :1;\r | |
1125 | UINT8 Provides50Volts :1;\r | |
1126 | UINT8 Provides33Volts :1;\r | |
1127 | UINT8 SharedSlot :1;\r | |
1128 | UINT8 PcCard16Supported :1;\r | |
1129 | UINT8 CardBusSupported :1;\r | |
1130 | UINT8 ZoomVideoSupported :1;\r | |
1131 | UINT8 ModemRingResumeSupported:1;\r | |
1132 | } MISC_SLOT_CHARACTERISTICS1;\r | |
1133 | ///\r | |
af2dc6a7 | 1134 | /// System Slots - Slot Characteristics 2. \r |
98cb9ae8 | 1135 | ///\r |
1136 | typedef struct {\r | |
1137 | UINT8 PmeSignalSupported :1;\r | |
1138 | UINT8 HotPlugDevicesSupported :1;\r | |
1139 | UINT8 SmbusSignalSupported :1;\r | |
6800ac83 | 1140 | UINT8 Reserved :5; ///< Set to 0.\r |
98cb9ae8 | 1141 | } MISC_SLOT_CHARACTERISTICS2;\r |
1142 | \r | |
4135253b | 1143 | ///\r |
1144 | /// System Slots (Type 9)\r | |
1145 | ///\r | |
98cb9ae8 | 1146 | /// The information in this structure defines the attributes of a system slot. \r |
1147 | /// One structure is provided for each slot in the system.\r | |
1148 | ///\r | |
1149 | ///\r | |
61ce5861 | 1150 | typedef struct {\r |
98cb9ae8 | 1151 | SMBIOS_STRUCTURE Hdr;\r |
1152 | SMBIOS_TABLE_STRING SlotDesignation;\r | |
af2dc6a7 | 1153 | UINT8 SlotType; ///< The enumeration value from MISC_SLOT_TYPE.\r |
1154 | UINT8 SlotDataBusWidth; ///< The enumeration value from MISC_SLOT_DATA_BUS_WIDTH.\r | |
1155 | UINT8 CurrentUsage; ///< The enumeration value from MISC_SLOT_USAGE.\r | |
1156 | UINT8 SlotLength; ///< The enumeration value from MISC_SLOT_LENGTH.\r | |
98cb9ae8 | 1157 | UINT16 SlotID;\r |
1158 | MISC_SLOT_CHARACTERISTICS1 SlotCharacteristics1;\r | |
1159 | MISC_SLOT_CHARACTERISTICS2 SlotCharacteristics2;\r | |
61ce5861 | 1160 | //\r |
1161 | // Add for smbios 2.6\r | |
1162 | //\r | |
98cb9ae8 | 1163 | UINT16 SegmentGroupNum;\r |
1164 | UINT8 BusNum;\r | |
1165 | UINT8 DevFuncNum;\r | |
61ce5861 | 1166 | } SMBIOS_TABLE_TYPE9;\r |
1167 | \r | |
98cb9ae8 | 1168 | ///\r |
af2dc6a7 | 1169 | /// On Board Devices Information - Device Types. \r |
98cb9ae8 | 1170 | ///\r |
1171 | typedef enum {\r | |
1172 | OnBoardDeviceTypeOther = 0x01,\r | |
1173 | OnBoardDeviceTypeUnknown = 0x02,\r | |
1174 | OnBoardDeviceTypeVideo = 0x03,\r | |
1175 | OnBoardDeviceTypeScsiController = 0x04,\r | |
1176 | OnBoardDeviceTypeEthernet = 0x05,\r | |
1177 | OnBoardDeviceTypeTokenRing = 0x06,\r | |
119c1688 SZ |
1178 | OnBoardDeviceTypeSound = 0x07,\r |
1179 | OnBoardDeviceTypePATAController = 0x08,\r | |
1180 | OnBoardDeviceTypeSATAController = 0x09,\r | |
1181 | OnBoardDeviceTypeSASController = 0x0A\r | |
98cb9ae8 | 1182 | } MISC_ONBOARD_DEVICE_TYPE;\r |
1183 | \r | |
bf7ea009 | 1184 | ///\r |
1185 | /// Device Item Entry\r | |
1186 | ///\r | |
61ce5861 | 1187 | typedef struct {\r |
af2dc6a7 | 1188 | UINT8 DeviceType; ///< Bit [6:0] - enumeration type of device from MISC_ONBOARD_DEVICE_TYPE.\r |
1189 | ///< Bit 7 - 1 : device enabled, 0 : device disabled.\r | |
98cb9ae8 | 1190 | SMBIOS_TABLE_STRING DescriptionString;\r |
61ce5861 | 1191 | } DEVICE_STRUCT;\r |
1192 | \r | |
4135253b | 1193 | ///\r |
af2dc6a7 | 1194 | /// On Board Devices Information (Type 10, obsolete).\r |
4135253b | 1195 | ///\r |
98cb9ae8 | 1196 | /// Note: This structure is obsolete starting with version 2.6 specification; the Onboard Devices Extended \r |
1197 | /// Information (Type 41) structure should be used instead . BIOS providers can choose to implement both \r | |
1198 | /// types to allow existing SMBIOS browsers to properly display the system's onboard devices information. \r | |
1199 | /// The information in this structure defines the attributes of devices that are onboard (soldered onto) \r | |
1200 | /// a system element, usually the baseboard. In general, an entry in this table implies that the BIOS\r | |
1201 | /// has some level of control over the enabling of the associated device for use by the system.\r | |
1202 | ///\r | |
61ce5861 | 1203 | typedef struct {\r |
1204 | SMBIOS_STRUCTURE Hdr;\r | |
1205 | DEVICE_STRUCT Device[1];\r | |
1206 | } SMBIOS_TABLE_TYPE10;\r | |
1207 | \r | |
4135253b | 1208 | ///\r |
af2dc6a7 | 1209 | /// OEM Strings (Type 11).\r |
98cb9ae8 | 1210 | /// This structure contains free form strings defined by the OEM. Examples of this are: \r |
1211 | /// Part Numbers for Reference Documents for the system, contact information for the manufacturer, etc. \r | |
4135253b | 1212 | ///\r |
61ce5861 | 1213 | typedef struct {\r |
1214 | SMBIOS_STRUCTURE Hdr;\r | |
1215 | UINT8 StringCount;\r | |
1216 | } SMBIOS_TABLE_TYPE11;\r | |
1217 | \r | |
4135253b | 1218 | ///\r |
af2dc6a7 | 1219 | /// System Configuration Options (Type 12).\r |
4135253b | 1220 | ///\r |
98cb9ae8 | 1221 | /// This structure contains information required to configure the base board's Jumpers and Switches. \r |
1222 | ///\r | |
61ce5861 | 1223 | typedef struct {\r |
1224 | SMBIOS_STRUCTURE Hdr;\r | |
1225 | UINT8 StringCount;\r | |
1226 | } SMBIOS_TABLE_TYPE12;\r | |
1227 | \r | |
98cb9ae8 | 1228 | \r |
4135253b | 1229 | ///\r |
af2dc6a7 | 1230 | /// BIOS Language Information (Type 13).\r |
4135253b | 1231 | ///\r |
98cb9ae8 | 1232 | /// The information in this structure defines the installable language attributes of the BIOS. \r |
1233 | /// \r | |
61ce5861 | 1234 | typedef struct {\r |
1235 | SMBIOS_STRUCTURE Hdr;\r | |
1236 | UINT8 InstallableLanguages;\r | |
1237 | UINT8 Flags;\r | |
fbfa4a1d | 1238 | UINT8 Reserved[15];\r |
61ce5861 | 1239 | SMBIOS_TABLE_STRING CurrentLanguages;\r |
1240 | } SMBIOS_TABLE_TYPE13;\r | |
1241 | \r | |
119c1688 SZ |
1242 | ///\r |
1243 | /// Group Item Entry\r | |
1244 | ///\r | |
1245 | typedef struct {\r | |
1246 | UINT8 ItemType;\r | |
1247 | UINT16 ItemHandle;\r | |
1248 | } GROUP_STRUCT;\r | |
1249 | \r | |
1250 | ///\r | |
1251 | /// Group Associations (Type 14).\r | |
1252 | ///\r | |
1253 | /// The Group Associations structure is provided for OEMs who want to specify \r | |
1254 | /// the arrangement or hierarchy of certain components (including other Group Associations) \r | |
1255 | /// within the system. \r | |
1256 | ///\r | |
1257 | typedef struct {\r | |
1258 | SMBIOS_STRUCTURE Hdr;\r | |
1259 | SMBIOS_TABLE_STRING GroupName;\r | |
1260 | GROUP_STRUCT Group[1];\r | |
1261 | } SMBIOS_TABLE_TYPE14;\r | |
1262 | \r | |
98cb9ae8 | 1263 | ///\r |
af2dc6a7 | 1264 | /// System Event Log - Event Log Types.\r |
98cb9ae8 | 1265 | /// \r |
1266 | typedef enum {\r | |
1267 | EventLogTypeReserved = 0x00,\r | |
1268 | EventLogTypeSingleBitECC = 0x01,\r | |
1269 | EventLogTypeMultiBitECC = 0x02,\r | |
1270 | EventLogTypeParityMemErr = 0x03,\r | |
1271 | EventLogTypeBusTimeOut = 0x04,\r | |
1272 | EventLogTypeIOChannelCheck = 0x05,\r | |
1273 | EventLogTypeSoftwareNMI = 0x06,\r | |
1274 | EventLogTypePOSTMemResize = 0x07,\r | |
1275 | EventLogTypePOSTErr = 0x08,\r | |
1276 | EventLogTypePCIParityErr = 0x09,\r | |
1277 | EventLogTypePCISystemErr = 0x0A,\r | |
1278 | EventLogTypeCPUFailure = 0x0B,\r | |
1279 | EventLogTypeEISATimeOut = 0x0C,\r | |
1280 | EventLogTypeMemLogDisabled = 0x0D,\r | |
1281 | EventLogTypeLoggingDisabled = 0x0E,\r | |
1282 | EventLogTypeSysLimitExce = 0x10,\r | |
1283 | EventLogTypeAsyncHWTimer = 0x11,\r | |
1284 | EventLogTypeSysConfigInfo = 0x12,\r | |
1285 | EventLogTypeHDInfo = 0x13,\r | |
1286 | EventLogTypeSysReconfig = 0x14,\r | |
1287 | EventLogTypeUncorrectCPUErr = 0x15,\r | |
1288 | EventLogTypeAreaResetAndClr = 0x16,\r | |
1289 | EventLogTypeSystemBoot = 0x17,\r | |
6800ac83 | 1290 | EventLogTypeUnused = 0x18, ///< 0x18 - 0x7F\r |
1291 | EventLogTypeAvailForSys = 0x80, ///< 0x80 - 0xFE\r | |
98cb9ae8 | 1292 | EventLogTypeEndOfLog = 0xFF\r |
1293 | } EVENT_LOG_TYPE_DATA;\r | |
1294 | \r | |
1295 | ///\r | |
af2dc6a7 | 1296 | /// System Event Log - Variable Data Format Types. \r |
98cb9ae8 | 1297 | /// \r |
1298 | typedef enum {\r | |
1299 | EventLogVariableNone = 0x00,\r | |
1300 | EventLogVariableHandle = 0x01,\r | |
1301 | EventLogVariableMutilEvent = 0x02,\r | |
1302 | EventLogVariableMutilEventHandle = 0x03,\r | |
1303 | EventLogVariablePOSTResultBitmap = 0x04,\r | |
1304 | EventLogVariableSysManagementType = 0x05,\r | |
1305 | EventLogVariableMutliEventSysManagmentType = 0x06, \r | |
1306 | EventLogVariableUnused = 0x07,\r | |
1307 | EventLogVariableOEMAssigned = 0x80\r | |
55deb978 | 1308 | } EVENT_LOG_VARIABLE_DATA;\r |
98cb9ae8 | 1309 | \r |
98cb9ae8 | 1310 | ///\r |
1311 | /// Event Log Type Descriptors\r | |
1312 | ///\r | |
1313 | typedef struct {\r | |
af2dc6a7 | 1314 | UINT8 LogType; ///< The enumeration value from EVENT_LOG_TYPE_DATA.\r |
98cb9ae8 | 1315 | UINT8 DataFormatType;\r |
1316 | } EVENT_LOG_TYPE;\r | |
1317 | \r | |
4135253b | 1318 | ///\r |
af2dc6a7 | 1319 | /// System Event Log (Type 15).\r |
4135253b | 1320 | ///\r |
98cb9ae8 | 1321 | /// The presence of this structure within the SMBIOS data returned for a system indicates \r |
1322 | /// that the system supports an event log. An event log is a fixed-length area within a \r | |
1323 | /// non-volatile storage element, starting with a fixed-length (and vendor-specific) header \r | |
1324 | /// record, followed by one or more variable-length log records. \r | |
1325 | ///\r | |
61ce5861 | 1326 | typedef struct {\r |
1327 | SMBIOS_STRUCTURE Hdr;\r | |
1328 | UINT16 LogAreaLength;\r | |
1329 | UINT16 LogHeaderStartOffset;\r | |
1330 | UINT16 LogDataStartOffset;\r | |
1331 | UINT8 AccessMethod;\r | |
1332 | UINT8 LogStatus;\r | |
1333 | UINT32 LogChangeToken;\r | |
1334 | UINT32 AccessMethodAddress;\r | |
1335 | UINT8 LogHeaderFormat;\r | |
1336 | UINT8 NumberOfSupportedLogTypeDescriptors;\r | |
1337 | UINT8 LengthOfLogTypeDescriptor;\r | |
1338 | EVENT_LOG_TYPE EventLogTypeDescriptors[1];\r | |
1339 | } SMBIOS_TABLE_TYPE15;\r | |
1340 | \r | |
98cb9ae8 | 1341 | ///\r |
af2dc6a7 | 1342 | /// Physical Memory Array - Location.\r |
98cb9ae8 | 1343 | ///\r |
1344 | typedef enum {\r | |
1345 | MemoryArrayLocationOther = 0x01,\r | |
1346 | MemoryArrayLocationUnknown = 0x02,\r | |
1347 | MemoryArrayLocationSystemBoard = 0x03,\r | |
1348 | MemoryArrayLocationIsaAddonCard = 0x04,\r | |
1349 | MemoryArrayLocationEisaAddonCard = 0x05,\r | |
1350 | MemoryArrayLocationPciAddonCard = 0x06,\r | |
1351 | MemoryArrayLocationMcaAddonCard = 0x07,\r | |
1352 | MemoryArrayLocationPcmciaAddonCard = 0x08,\r | |
1353 | MemoryArrayLocationProprietaryAddonCard = 0x09,\r | |
1354 | MemoryArrayLocationNuBus = 0x0A,\r | |
1355 | MemoryArrayLocationPc98C20AddonCard = 0xA0,\r | |
1356 | MemoryArrayLocationPc98C24AddonCard = 0xA1,\r | |
1357 | MemoryArrayLocationPc98EAddonCard = 0xA2,\r | |
1358 | MemoryArrayLocationPc98LocalBusAddonCard = 0xA3\r | |
1359 | } MEMORY_ARRAY_LOCATION;\r | |
1360 | \r | |
1361 | ///\r | |
af2dc6a7 | 1362 | /// Physical Memory Array - Use.\r |
98cb9ae8 | 1363 | ///\r |
1364 | typedef enum {\r | |
1365 | MemoryArrayUseOther = 0x01,\r | |
1366 | MemoryArrayUseUnknown = 0x02,\r | |
1367 | MemoryArrayUseSystemMemory = 0x03,\r | |
1368 | MemoryArrayUseVideoMemory = 0x04,\r | |
1369 | MemoryArrayUseFlashMemory = 0x05,\r | |
1370 | MemoryArrayUseNonVolatileRam = 0x06,\r | |
1371 | MemoryArrayUseCacheMemory = 0x07\r | |
1372 | } MEMORY_ARRAY_USE;\r | |
1373 | \r | |
1374 | ///\r | |
af2dc6a7 | 1375 | /// Physical Memory Array - Error Correction Types. \r |
98cb9ae8 | 1376 | ///\r |
1377 | typedef enum {\r | |
1378 | MemoryErrorCorrectionOther = 0x01,\r | |
1379 | MemoryErrorCorrectionUnknown = 0x02,\r | |
1380 | MemoryErrorCorrectionNone = 0x03,\r | |
1381 | MemoryErrorCorrectionParity = 0x04,\r | |
1382 | MemoryErrorCorrectionSingleBitEcc = 0x05,\r | |
1383 | MemoryErrorCorrectionMultiBitEcc = 0x06,\r | |
1384 | MemoryErrorCorrectionCrc = 0x07\r | |
1385 | } MEMORY_ERROR_CORRECTION;\r | |
1386 | \r | |
4135253b | 1387 | ///\r |
af2dc6a7 | 1388 | /// Physical Memory Array (Type 16).\r |
4135253b | 1389 | ///\r |
98cb9ae8 | 1390 | /// This structure describes a collection of memory devices that operate \r |
1391 | /// together to form a memory address space. \r | |
1392 | ///\r | |
61ce5861 | 1393 | typedef struct {\r |
98cb9ae8 | 1394 | SMBIOS_STRUCTURE Hdr;\r |
af2dc6a7 | 1395 | UINT8 Location; ///< The enumeration value from MEMORY_ARRAY_LOCATION.\r |
1396 | UINT8 Use; ///< The enumeration value from MEMORY_ARRAY_USE.\r | |
1397 | UINT8 MemoryErrorCorrection; ///< The enumeration value from MEMORY_ERROR_CORRECTION.\r | |
98cb9ae8 | 1398 | UINT32 MaximumCapacity;\r |
1399 | UINT16 MemoryErrorInformationHandle;\r | |
1400 | UINT16 NumberOfMemoryDevices;\r | |
7ddba202 SZ |
1401 | //\r |
1402 | // Add for smbios 2.7\r | |
1403 | //\r | |
1404 | UINT64 ExtendedMaximumCapacity;\r | |
61ce5861 | 1405 | } SMBIOS_TABLE_TYPE16;\r |
1406 | \r | |
98cb9ae8 | 1407 | ///\r |
af2dc6a7 | 1408 | /// Memory Device - Form Factor.\r |
98cb9ae8 | 1409 | ///\r |
1410 | typedef enum {\r | |
1411 | MemoryFormFactorOther = 0x01,\r | |
1412 | MemoryFormFactorUnknown = 0x02,\r | |
1413 | MemoryFormFactorSimm = 0x03,\r | |
1414 | MemoryFormFactorSip = 0x04,\r | |
1415 | MemoryFormFactorChip = 0x05,\r | |
1416 | MemoryFormFactorDip = 0x06,\r | |
1417 | MemoryFormFactorZip = 0x07,\r | |
1418 | MemoryFormFactorProprietaryCard = 0x08,\r | |
1419 | MemoryFormFactorDimm = 0x09,\r | |
1420 | MemoryFormFactorTsop = 0x0A,\r | |
1421 | MemoryFormFactorRowOfChips = 0x0B,\r | |
1422 | MemoryFormFactorRimm = 0x0C,\r | |
1423 | MemoryFormFactorSodimm = 0x0D,\r | |
1424 | MemoryFormFactorSrimm = 0x0E,\r | |
1425 | MemoryFormFactorFbDimm = 0x0F\r | |
1426 | } MEMORY_FORM_FACTOR;\r | |
1427 | \r | |
1428 | ///\r | |
1429 | /// Memory Device - Type\r | |
1430 | ///\r | |
1431 | typedef enum {\r | |
1432 | MemoryTypeOther = 0x01,\r | |
1433 | MemoryTypeUnknown = 0x02,\r | |
1434 | MemoryTypeDram = 0x03,\r | |
1435 | MemoryTypeEdram = 0x04,\r | |
1436 | MemoryTypeVram = 0x05,\r | |
1437 | MemoryTypeSram = 0x06,\r | |
1438 | MemoryTypeRam = 0x07,\r | |
1439 | MemoryTypeRom = 0x08,\r | |
1440 | MemoryTypeFlash = 0x09,\r | |
1441 | MemoryTypeEeprom = 0x0A,\r | |
1442 | MemoryTypeFeprom = 0x0B,\r | |
1443 | MemoryTypeEprom = 0x0C,\r | |
1444 | MemoryTypeCdram = 0x0D,\r | |
1445 | MemoryType3Dram = 0x0E,\r | |
1446 | MemoryTypeSdram = 0x0F,\r | |
1447 | MemoryTypeSgram = 0x10,\r | |
1448 | MemoryTypeRdram = 0x11,\r | |
1449 | MemoryTypeDdr = 0x12,\r | |
1450 | MemoryTypeDdr2 = 0x13,\r | |
3507ab19 | 1451 | MemoryTypeDdr2FbDimm = 0x14,\r |
1452 | MemoryTypeDdr3 = 0x18,\r | |
1453 | MemoryTypeFbd2 = 0x19\r | |
98cb9ae8 | 1454 | } MEMORY_DEVICE_TYPE;\r |
1455 | \r | |
1456 | typedef struct {\r | |
1457 | UINT16 Reserved :1;\r | |
1458 | UINT16 Other :1;\r | |
1459 | UINT16 Unknown :1;\r | |
1460 | UINT16 FastPaged :1;\r | |
1461 | UINT16 StaticColumn :1;\r | |
1462 | UINT16 PseudoStatic :1;\r | |
1463 | UINT16 Rambus :1;\r | |
1464 | UINT16 Synchronous :1;\r | |
1465 | UINT16 Cmos :1;\r | |
1466 | UINT16 Edo :1;\r | |
1467 | UINT16 WindowDram :1;\r | |
1468 | UINT16 CacheDram :1;\r | |
1469 | UINT16 Nonvolatile :1;\r | |
7ddba202 SZ |
1470 | UINT16 Registered :1;\r |
1471 | UINT16 Unbuffered :1;\r | |
1472 | UINT16 Reserved1 :1;\r | |
98cb9ae8 | 1473 | } MEMORY_DEVICE_TYPE_DETAIL;\r |
1474 | \r | |
4135253b | 1475 | ///\r |
af2dc6a7 | 1476 | /// Memory Device (Type 17).\r |
4135253b | 1477 | ///\r |
98cb9ae8 | 1478 | /// This structure describes a single memory device that is part of \r |
1479 | /// a larger Physical Memory Array (Type 16).\r | |
1480 | /// Note: If a system includes memory-device sockets, the SMBIOS implementation \r | |
af2dc6a7 | 1481 | /// includes a Memory Device structure instance for each slot, whether or not the \r |
98cb9ae8 | 1482 | /// socket is currently populated.\r |
1483 | ///\r | |
61ce5861 | 1484 | typedef struct {\r |
98cb9ae8 | 1485 | SMBIOS_STRUCTURE Hdr;\r |
1486 | UINT16 MemoryArrayHandle;\r | |
1487 | UINT16 MemoryErrorInformationHandle;\r | |
1488 | UINT16 TotalWidth;\r | |
1489 | UINT16 DataWidth;\r | |
1490 | UINT16 Size;\r | |
af2dc6a7 | 1491 | UINT8 FormFactor; ///< The enumeration value from MEMORY_FORM_FACTOR.\r |
98cb9ae8 | 1492 | UINT8 DeviceSet;\r |
1493 | SMBIOS_TABLE_STRING DeviceLocator;\r | |
1494 | SMBIOS_TABLE_STRING BankLocator;\r | |
af2dc6a7 | 1495 | UINT8 MemoryType; ///< The enumeration value from MEMORY_DEVICE_TYPE.\r |
98cb9ae8 | 1496 | MEMORY_DEVICE_TYPE_DETAIL TypeDetail;\r |
1497 | UINT16 Speed;\r | |
1498 | SMBIOS_TABLE_STRING Manufacturer;\r | |
1499 | SMBIOS_TABLE_STRING SerialNumber;\r | |
1500 | SMBIOS_TABLE_STRING AssetTag;\r | |
1501 | SMBIOS_TABLE_STRING PartNumber;\r | |
61ce5861 | 1502 | //\r |
1503 | // Add for smbios 2.6\r | |
1504 | // \r | |
7ddba202 SZ |
1505 | UINT8 Attributes;\r |
1506 | //\r | |
1507 | // Add for smbios 2.7\r | |
1508 | //\r | |
1509 | UINT32 ExtendedSize;\r | |
1510 | UINT16 ConfiguredMemoryClockSpeed;\r | |
61ce5861 | 1511 | } SMBIOS_TABLE_TYPE17;\r |
1512 | \r | |
98cb9ae8 | 1513 | ///\r |
af2dc6a7 | 1514 | /// 32-bit Memory Error Information - Error Type. \r |
98cb9ae8 | 1515 | ///\r |
1516 | typedef enum { \r | |
1517 | MemoryErrorOther = 0x01,\r | |
1518 | MemoryErrorUnknown = 0x02,\r | |
1519 | MemoryErrorOk = 0x03,\r | |
1520 | MemoryErrorBadRead = 0x04,\r | |
1521 | MemoryErrorParity = 0x05,\r | |
1522 | MemoryErrorSigleBit = 0x06,\r | |
1523 | MemoryErrorDoubleBit = 0x07,\r | |
1524 | MemoryErrorMultiBit = 0x08,\r | |
1525 | MemoryErrorNibble = 0x09,\r | |
1526 | MemoryErrorChecksum = 0x0A,\r | |
1527 | MemoryErrorCrc = 0x0B,\r | |
1528 | MemoryErrorCorrectSingleBit = 0x0C,\r | |
1529 | MemoryErrorCorrected = 0x0D,\r | |
1530 | MemoryErrorUnCorrectable = 0x0E\r | |
1531 | } MEMORY_ERROR_TYPE;\r | |
1532 | \r | |
1533 | ///\r | |
af2dc6a7 | 1534 | /// 32-bit Memory Error Information - Error Granularity. \r |
98cb9ae8 | 1535 | ///\r |
1536 | typedef enum { \r | |
1537 | MemoryGranularityOther = 0x01,\r | |
1538 | MemoryGranularityOtherUnknown = 0x02,\r | |
1539 | MemoryGranularityDeviceLevel = 0x03,\r | |
1540 | MemoryGranularityMemPartitionLevel = 0x04\r | |
1541 | } MEMORY_ERROR_GRANULARITY;\r | |
1542 | \r | |
1543 | ///\r | |
af2dc6a7 | 1544 | /// 32-bit Memory Error Information - Error Operation. \r |
98cb9ae8 | 1545 | ///\r |
1546 | typedef enum { \r | |
1547 | MemoryErrorOperationOther = 0x01,\r | |
1548 | MemoryErrorOperationUnknown = 0x02,\r | |
1549 | MemoryErrorOperationRead = 0x03,\r | |
1550 | MemoryErrorOperationWrite = 0x04,\r | |
1551 | MemoryErrorOperationPartialWrite = 0x05\r | |
1552 | } MEMORY_ERROR_OPERATION;\r | |
1553 | \r | |
4135253b | 1554 | ///\r |
af2dc6a7 | 1555 | /// 32-bit Memory Error Information (Type 18).\r |
98cb9ae8 | 1556 | /// \r |
1557 | /// This structure identifies the specifics of an error that might be detected \r | |
1558 | /// within a Physical Memory Array.\r | |
4135253b | 1559 | ///\r |
61ce5861 | 1560 | typedef struct {\r |
98cb9ae8 | 1561 | SMBIOS_STRUCTURE Hdr;\r |
af2dc6a7 | 1562 | UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.\r |
1563 | UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r | |
1564 | UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.\r | |
98cb9ae8 | 1565 | UINT32 VendorSyndrome;\r |
1566 | UINT32 MemoryArrayErrorAddress;\r | |
1567 | UINT32 DeviceErrorAddress;\r | |
1568 | UINT32 ErrorResolution;\r | |
61ce5861 | 1569 | } SMBIOS_TABLE_TYPE18;\r |
1570 | \r | |
4135253b | 1571 | ///\r |
af2dc6a7 | 1572 | /// Memory Array Mapped Address (Type 19).\r |
4135253b | 1573 | ///\r |
98cb9ae8 | 1574 | /// This structure provides the address mapping for a Physical Memory Array. \r |
1575 | /// One structure is present for each contiguous address range described.\r | |
1576 | ///\r | |
61ce5861 | 1577 | typedef struct {\r |
1578 | SMBIOS_STRUCTURE Hdr;\r | |
1579 | UINT32 StartingAddress;\r | |
1580 | UINT32 EndingAddress;\r | |
1581 | UINT16 MemoryArrayHandle;\r | |
1582 | UINT8 PartitionWidth;\r | |
7ddba202 SZ |
1583 | //\r |
1584 | // Add for smbios 2.7\r | |
1585 | //\r | |
1586 | UINT64 ExtendedStartingAddress;\r | |
1587 | UINT64 ExtendedEndingAddress;\r | |
61ce5861 | 1588 | } SMBIOS_TABLE_TYPE19;\r |
1589 | \r | |
4135253b | 1590 | ///\r |
af2dc6a7 | 1591 | /// Memory Device Mapped Address (Type 20).\r |
4135253b | 1592 | ///\r |
98cb9ae8 | 1593 | /// This structure maps memory address space usually to a device-level granularity. \r |
1594 | /// One structure is present for each contiguous address range described. \r | |
1595 | ///\r | |
61ce5861 | 1596 | typedef struct {\r |
1597 | SMBIOS_STRUCTURE Hdr;\r | |
1598 | UINT32 StartingAddress;\r | |
1599 | UINT32 EndingAddress;\r | |
1600 | UINT16 MemoryDeviceHandle;\r | |
1601 | UINT16 MemoryArrayMappedAddressHandle;\r | |
1602 | UINT8 PartitionRowPosition;\r | |
1603 | UINT8 InterleavePosition;\r | |
1604 | UINT8 InterleavedDataDepth;\r | |
7ddba202 SZ |
1605 | //\r |
1606 | // Add for smbios 2.7\r | |
1607 | //\r | |
1608 | UINT64 ExtendedStartingAddress;\r | |
1609 | UINT64 ExtendedEndingAddress;\r | |
61ce5861 | 1610 | } SMBIOS_TABLE_TYPE20;\r |
1611 | \r | |
98cb9ae8 | 1612 | ///\r |
1613 | /// Built-in Pointing Device - Type\r | |
1614 | ///\r | |
1615 | typedef enum {\r | |
1616 | PointingDeviceTypeOther = 0x01,\r | |
1617 | PointingDeviceTypeUnknown = 0x02,\r | |
1618 | PointingDeviceTypeMouse = 0x03,\r | |
1619 | PointingDeviceTypeTrackBall = 0x04,\r | |
1620 | PointingDeviceTypeTrackPoint = 0x05,\r | |
1621 | PointingDeviceTypeGlidePoint = 0x06,\r | |
1622 | PointingDeviceTouchPad = 0x07,\r | |
1623 | PointingDeviceTouchScreen = 0x08,\r | |
1624 | PointingDeviceOpticalSensor = 0x09\r | |
1625 | } BUILTIN_POINTING_DEVICE_TYPE;\r | |
1626 | \r | |
1627 | ///\r | |
af2dc6a7 | 1628 | /// Built-in Pointing Device - Interface.\r |
98cb9ae8 | 1629 | ///\r |
1630 | typedef enum {\r | |
1631 | PointingDeviceInterfaceOther = 0x01,\r | |
1632 | PointingDeviceInterfaceUnknown = 0x02,\r | |
1633 | PointingDeviceInterfaceSerial = 0x03,\r | |
1634 | PointingDeviceInterfacePs2 = 0x04,\r | |
1635 | PointingDeviceInterfaceInfrared = 0x05,\r | |
1636 | PointingDeviceInterfaceHpHil = 0x06,\r | |
1637 | PointingDeviceInterfaceBusMouse = 0x07,\r | |
1638 | PointingDeviceInterfaceADB = 0x08,\r | |
1639 | PointingDeviceInterfaceBusMouseDB9 = 0xA0,\r | |
1640 | PointingDeviceInterfaceBusMouseMicroDin = 0xA1,\r | |
1641 | PointingDeviceInterfaceUsb = 0xA2\r | |
1642 | } BUILTIN_POINTING_DEVICE_INTERFACE;\r | |
1643 | \r | |
4135253b | 1644 | ///\r |
af2dc6a7 | 1645 | /// Built-in Pointing Device (Type 21).\r |
4135253b | 1646 | ///\r |
98cb9ae8 | 1647 | /// This structure describes the attributes of the built-in pointing device for the \r |
af2dc6a7 | 1648 | /// system. The presence of this structure does not imply that the built-in\r |
98cb9ae8 | 1649 | /// pointing device is active for the system's use! \r |
1650 | ///\r | |
61ce5861 | 1651 | typedef struct {\r |
98cb9ae8 | 1652 | SMBIOS_STRUCTURE Hdr;\r |
af2dc6a7 | 1653 | UINT8 Type; ///< The enumeration value from BUILTIN_POINTING_DEVICE_TYPE.\r |
1654 | UINT8 Interface; ///< The enumeration value from BUILTIN_POINTING_DEVICE_INTERFACE.\r | |
98cb9ae8 | 1655 | UINT8 NumberOfButtons;\r |
61ce5861 | 1656 | } SMBIOS_TABLE_TYPE21;\r |
1657 | \r | |
98cb9ae8 | 1658 | ///\r |
1659 | /// Portable Battery - Device Chemistry\r | |
1660 | ///\r | |
1661 | typedef enum { \r | |
1662 | PortableBatteryDeviceChemistryOther = 0x01,\r | |
1663 | PortableBatteryDeviceChemistryUnknown = 0x02,\r | |
1664 | PortableBatteryDeviceChemistryLeadAcid = 0x03,\r | |
1665 | PortableBatteryDeviceChemistryNickelCadmium = 0x04,\r | |
1666 | PortableBatteryDeviceChemistryNickelMetalHydride = 0x05,\r | |
1667 | PortableBatteryDeviceChemistryLithiumIon = 0x06,\r | |
1668 | PortableBatteryDeviceChemistryZincAir = 0x07,\r | |
1669 | PortableBatteryDeviceChemistryLithiumPolymer = 0x08\r | |
1670 | } PORTABLE_BATTERY_DEVICE_CHEMISTRY;\r | |
1671 | \r | |
4135253b | 1672 | ///\r |
af2dc6a7 | 1673 | /// Portable Battery (Type 22).\r |
4135253b | 1674 | ///\r |
98cb9ae8 | 1675 | /// This structure describes the attributes of the portable battery(s) for the system. \r |
1676 | /// The structure contains the static attributes for the group. Each structure describes \r | |
1f9f8414 | 1677 | /// a single battery pack's attributes.\r |
98cb9ae8 | 1678 | ///\r |
61ce5861 | 1679 | typedef struct {\r |
98cb9ae8 | 1680 | SMBIOS_STRUCTURE Hdr;\r |
1681 | SMBIOS_TABLE_STRING Location;\r | |
1682 | SMBIOS_TABLE_STRING Manufacturer;\r | |
1683 | SMBIOS_TABLE_STRING ManufactureDate;\r | |
1684 | SMBIOS_TABLE_STRING SerialNumber;\r | |
1685 | SMBIOS_TABLE_STRING DeviceName;\r | |
af2dc6a7 | 1686 | UINT8 DeviceChemistry; ///< The enumeration value from PORTABLE_BATTERY_DEVICE_CHEMISTRY.\r |
98cb9ae8 | 1687 | UINT16 DeviceCapacity;\r |
1688 | UINT16 DesignVoltage;\r | |
1689 | SMBIOS_TABLE_STRING SBDSVersionNumber;\r | |
1690 | UINT8 MaximumErrorInBatteryData;\r | |
1691 | UINT16 SBDSSerialNumber;\r | |
1692 | UINT16 SBDSManufactureDate;\r | |
1693 | SMBIOS_TABLE_STRING SBDSDeviceChemistry;\r | |
1694 | UINT8 DesignCapacityMultiplier;\r | |
1695 | UINT32 OEMSpecific;\r | |
61ce5861 | 1696 | } SMBIOS_TABLE_TYPE22;\r |
1697 | \r | |
4135253b | 1698 | ///\r |
1699 | /// System Reset (Type 23)\r | |
1700 | ///\r | |
98cb9ae8 | 1701 | /// This structure describes whether Automatic System Reset functions enabled (Status). \r |
1702 | /// If the system has a watchdog Timer and the timer is not reset (Timer Reset)\r | |
1703 | /// before the Interval elapses, an automatic system reset will occur. The system will re-boot \r | |
1704 | /// according to the Boot Option. This function may repeat until the Limit is reached, at which time \r | |
1705 | /// the system will re-boot according to the Boot Option at Limit. \r | |
1706 | ///\r | |
61ce5861 | 1707 | typedef struct {\r |
1708 | SMBIOS_STRUCTURE Hdr;\r | |
1709 | UINT8 Capabilities;\r | |
1710 | UINT16 ResetCount;\r | |
1711 | UINT16 ResetLimit;\r | |
1712 | UINT16 TimerInterval;\r | |
1713 | UINT16 Timeout;\r | |
1714 | } SMBIOS_TABLE_TYPE23;\r | |
1715 | \r | |
4135253b | 1716 | ///\r |
af2dc6a7 | 1717 | /// Hardware Security (Type 24).\r |
4135253b | 1718 | ///\r |
98cb9ae8 | 1719 | /// This structure describes the system-wide hardware security settings. \r |
1720 | ///\r | |
61ce5861 | 1721 | typedef struct {\r |
1722 | SMBIOS_STRUCTURE Hdr;\r | |
1723 | UINT8 HardwareSecuritySettings;\r | |
1724 | } SMBIOS_TABLE_TYPE24;\r | |
1725 | \r | |
4135253b | 1726 | ///\r |
af2dc6a7 | 1727 | /// System Power Controls (Type 25).\r |
4135253b | 1728 | ///\r |
98cb9ae8 | 1729 | /// This structure describes the attributes for controlling the main power supply to the system. \r |
1730 | /// Software that interprets this structure uses the month, day, hour, minute, and second values \r | |
1731 | /// to determine the number of seconds until the next power-on of the system. The presence of \r | |
1732 | /// this structure implies that a timed power-on facility is available for the system. \r | |
1733 | ///\r | |
61ce5861 | 1734 | typedef struct {\r |
1735 | SMBIOS_STRUCTURE Hdr;\r | |
1736 | UINT8 NextScheduledPowerOnMonth;\r | |
1737 | UINT8 NextScheduledPowerOnDayOfMonth;\r | |
1738 | UINT8 NextScheduledPowerOnHour;\r | |
1739 | UINT8 NextScheduledPowerOnMinute;\r | |
1740 | UINT8 NextScheduledPowerOnSecond;\r | |
1741 | } SMBIOS_TABLE_TYPE25;\r | |
1742 | \r | |
98cb9ae8 | 1743 | ///\r |
af2dc6a7 | 1744 | /// Voltage Probe - Location and Status.\r |
98cb9ae8 | 1745 | ///\r |
1746 | typedef struct {\r | |
1747 | UINT8 VoltageProbeSite :5;\r | |
1748 | UINT8 VoltageProbeStatus :3;\r | |
1749 | } MISC_VOLTAGE_PROBE_LOCATION;\r | |
1750 | \r | |
4135253b | 1751 | ///\r |
1752 | /// Voltage Probe (Type 26)\r | |
1753 | ///\r | |
98cb9ae8 | 1754 | /// This describes the attributes for a voltage probe in the system. \r |
1755 | /// Each structure describes a single voltage probe.\r | |
1756 | ///\r | |
61ce5861 | 1757 | typedef struct {\r |
98cb9ae8 | 1758 | SMBIOS_STRUCTURE Hdr;\r |
1759 | SMBIOS_TABLE_STRING Description;\r | |
1760 | MISC_VOLTAGE_PROBE_LOCATION LocationAndStatus;\r | |
1761 | UINT16 MaximumValue;\r | |
1762 | UINT16 MinimumValue;\r | |
1763 | UINT16 Resolution;\r | |
1764 | UINT16 Tolerance;\r | |
1765 | UINT16 Accuracy;\r | |
1766 | UINT32 OEMDefined;\r | |
1767 | UINT16 NominalValue;\r | |
61ce5861 | 1768 | } SMBIOS_TABLE_TYPE26;\r |
1769 | \r | |
98cb9ae8 | 1770 | ///\r |
af2dc6a7 | 1771 | /// Cooling Device - Device Type and Status.\r |
98cb9ae8 | 1772 | ///\r |
1773 | typedef struct {\r | |
1774 | UINT8 CoolingDevice :5;\r | |
1775 | UINT8 CoolingDeviceStatus :3;\r | |
1776 | } MISC_COOLING_DEVICE_TYPE;\r | |
1777 | \r | |
4135253b | 1778 | ///\r |
1779 | /// Cooling Device (Type 27)\r | |
1780 | ///\r | |
98cb9ae8 | 1781 | /// This structure describes the attributes for a cooling device in the system. \r |
1782 | /// Each structure describes a single cooling device. \r | |
1783 | /// \r | |
61ce5861 | 1784 | typedef struct {\r |
98cb9ae8 | 1785 | SMBIOS_STRUCTURE Hdr;\r |
1786 | UINT16 TemperatureProbeHandle;\r | |
1787 | MISC_COOLING_DEVICE_TYPE DeviceTypeAndStatus;\r | |
1788 | UINT8 CoolingUnitGroup;\r | |
1789 | UINT32 OEMDefined;\r | |
1790 | UINT16 NominalSpeed;\r | |
7ddba202 SZ |
1791 | //\r |
1792 | // Add for smbios 2.7\r | |
1793 | //\r | |
1794 | SMBIOS_TABLE_STRING Description;\r | |
61ce5861 | 1795 | } SMBIOS_TABLE_TYPE27;\r |
1796 | \r | |
98cb9ae8 | 1797 | ///\r |
af2dc6a7 | 1798 | /// Temperature Probe - Location and Status.\r |
98cb9ae8 | 1799 | ///\r |
1800 | typedef struct {\r | |
1801 | UINT8 TemperatureProbeSite :5;\r | |
1802 | UINT8 TemperatureProbeStatus :3;\r | |
1803 | } MISC_TEMPERATURE_PROBE_LOCATION;\r | |
1804 | \r | |
4135253b | 1805 | ///\r |
af2dc6a7 | 1806 | /// Temperature Probe (Type 28).\r |
4135253b | 1807 | ///\r |
98cb9ae8 | 1808 | /// This structure describes the attributes for a temperature probe in the system. \r |
1809 | /// Each structure describes a single temperature probe. \r | |
1810 | ///\r | |
61ce5861 | 1811 | typedef struct {\r |
98cb9ae8 | 1812 | SMBIOS_STRUCTURE Hdr;\r |
1813 | SMBIOS_TABLE_STRING Description;\r | |
1814 | MISC_TEMPERATURE_PROBE_LOCATION LocationAndStatus;\r | |
1815 | UINT16 MaximumValue;\r | |
1816 | UINT16 MinimumValue;\r | |
1817 | UINT16 Resolution;\r | |
1818 | UINT16 Tolerance;\r | |
1819 | UINT16 Accuracy;\r | |
1820 | UINT32 OEMDefined;\r | |
1821 | UINT16 NominalValue;\r | |
61ce5861 | 1822 | } SMBIOS_TABLE_TYPE28;\r |
1823 | \r | |
98cb9ae8 | 1824 | ///\r |
af2dc6a7 | 1825 | /// Electrical Current Probe - Location and Status.\r |
98cb9ae8 | 1826 | ///\r |
1827 | typedef struct {\r | |
1828 | UINT8 ElectricalCurrentProbeSite :5;\r | |
1829 | UINT8 ElectricalCurrentProbeStatus :3;\r | |
1830 | } MISC_ELECTRICAL_CURRENT_PROBE_LOCATION;\r | |
1831 | \r | |
4135253b | 1832 | ///\r |
af2dc6a7 | 1833 | /// Electrical Current Probe (Type 29).\r |
4135253b | 1834 | ///\r |
98cb9ae8 | 1835 | /// This structure describes the attributes for an electrical current probe in the system.\r |
1836 | /// Each structure describes a single electrical current probe. \r | |
1837 | ///\r | |
61ce5861 | 1838 | typedef struct {\r |
98cb9ae8 | 1839 | SMBIOS_STRUCTURE Hdr;\r |
1840 | SMBIOS_TABLE_STRING Description;\r | |
1841 | MISC_ELECTRICAL_CURRENT_PROBE_LOCATION LocationAndStatus;\r | |
1842 | UINT16 MaximumValue;\r | |
1843 | UINT16 MinimumValue;\r | |
1844 | UINT16 Resolution;\r | |
1845 | UINT16 Tolerance;\r | |
1846 | UINT16 Accuracy;\r | |
1847 | UINT32 OEMDefined;\r | |
1848 | UINT16 NominalValue;\r | |
61ce5861 | 1849 | } SMBIOS_TABLE_TYPE29;\r |
1850 | \r | |
4135253b | 1851 | ///\r |
af2dc6a7 | 1852 | /// Out-of-Band Remote Access (Type 30).\r |
4135253b | 1853 | ///\r |
98cb9ae8 | 1854 | /// This structure describes the attributes and policy settings of a hardware facility \r |
1855 | /// that may be used to gain remote access to a hardware system when the operating system \r | |
1856 | /// is not available due to power-down status, hardware failures, or boot failures. \r | |
1857 | ///\r | |
61ce5861 | 1858 | typedef struct {\r |
1859 | SMBIOS_STRUCTURE Hdr;\r | |
1860 | SMBIOS_TABLE_STRING ManufacturerName;\r | |
1861 | UINT8 Connections;\r | |
1862 | } SMBIOS_TABLE_TYPE30;\r | |
1863 | \r | |
4135253b | 1864 | ///\r |
af2dc6a7 | 1865 | /// Boot Integrity Services (BIS) Entry Point (Type 31).\r |
4135253b | 1866 | ///\r |
98cb9ae8 | 1867 | /// Structure type 31 (decimal) is reserved for use by the Boot Integrity Services (BIS). \r |
1868 | /// \r | |
61ce5861 | 1869 | typedef struct {\r |
1870 | SMBIOS_STRUCTURE Hdr;\r | |
1871 | UINT8 Checksum;\r | |
1872 | UINT8 Reserved1;\r | |
1873 | UINT16 Reserved2;\r | |
1874 | UINT32 BisEntry16;\r | |
1875 | UINT32 BisEntry32;\r | |
1876 | UINT64 Reserved3;\r | |
1877 | UINT32 Reserved4;\r | |
1878 | } SMBIOS_TABLE_TYPE31;\r | |
1879 | \r | |
98cb9ae8 | 1880 | ///\r |
af2dc6a7 | 1881 | /// System Boot Information - System Boot Status.\r |
98cb9ae8 | 1882 | ///\r |
1883 | typedef enum {\r | |
1884 | BootInformationStatusNoError = 0x00,\r | |
1885 | BootInformationStatusNoBootableMedia = 0x01,\r | |
1886 | BootInformationStatusNormalOSFailedLoading = 0x02,\r | |
1887 | BootInformationStatusFirmwareDetectedFailure = 0x03,\r | |
1888 | BootInformationStatusOSDetectedFailure = 0x04,\r | |
1889 | BootInformationStatusUserRequestedBoot = 0x05,\r | |
1890 | BootInformationStatusSystemSecurityViolation = 0x06,\r | |
1891 | BootInformationStatusPreviousRequestedImage = 0x07,\r | |
1892 | BootInformationStatusWatchdogTimerExpired = 0x08,\r | |
1893 | BootInformationStatusStartReserved = 0x09,\r | |
1894 | BootInformationStatusStartOemSpecific = 0x80,\r | |
1895 | BootInformationStatusStartProductSpecific = 0xC0\r | |
1896 | } MISC_BOOT_INFORMATION_STATUS_DATA_TYPE;\r | |
1897 | \r | |
4135253b | 1898 | ///\r |
af2dc6a7 | 1899 | /// System Boot Information (Type 32).\r |
4135253b | 1900 | ///\r |
98cb9ae8 | 1901 | /// The client system firmware, e.g. BIOS, communicates the System Boot Status to the \r |
1902 | /// client's Pre-boot Execution Environment (PXE) boot image or OS-present management \r | |
1903 | /// application via this structure. When used in the PXE environment, for example, \r | |
1904 | /// this code identifies the reason the PXE was initiated and can be used by boot-image \r | |
1f9f8414 | 1905 | /// software to further automate an enterprise's PXE sessions. For example, an enterprise \r |
98cb9ae8 | 1906 | /// could choose to automatically download a hardware-diagnostic image to a client whose \r |
1907 | /// reason code indicated either a firmware- or operating system-detected hardware failure.\r | |
1908 | ///\r | |
61ce5861 | 1909 | typedef struct {\r |
98cb9ae8 | 1910 | SMBIOS_STRUCTURE Hdr;\r |
1911 | UINT8 Reserved[6];\r | |
af2dc6a7 | 1912 | UINT8 BootStatus; ///< The enumeration value from MISC_BOOT_INFORMATION_STATUS_DATA_TYPE.\r |
61ce5861 | 1913 | } SMBIOS_TABLE_TYPE32;\r |
1914 | \r | |
4135253b | 1915 | ///\r |
af2dc6a7 | 1916 | /// 64-bit Memory Error Information (Type 33).\r |
4135253b | 1917 | ///\r |
98cb9ae8 | 1918 | /// This structure describes an error within a Physical Memory Array, \r |
1919 | /// when the error address is above 4G (0xFFFFFFFF).\r | |
1920 | /// \r | |
61ce5861 | 1921 | typedef struct {\r |
98cb9ae8 | 1922 | SMBIOS_STRUCTURE Hdr;\r |
af2dc6a7 | 1923 | UINT8 ErrorType; ///< The enumeration value from MEMORY_ERROR_TYPE.\r |
1924 | UINT8 ErrorGranularity; ///< The enumeration value from MEMORY_ERROR_GRANULARITY.\r | |
1925 | UINT8 ErrorOperation; ///< The enumeration value from MEMORY_ERROR_OPERATION.\r | |
98cb9ae8 | 1926 | UINT32 VendorSyndrome;\r |
1927 | UINT64 MemoryArrayErrorAddress;\r | |
1928 | UINT64 DeviceErrorAddress;\r | |
1929 | UINT32 ErrorResolution;\r | |
61ce5861 | 1930 | } SMBIOS_TABLE_TYPE33;\r |
1931 | \r | |
98cb9ae8 | 1932 | ///\r |
af2dc6a7 | 1933 | /// Management Device - Type. \r |
98cb9ae8 | 1934 | ///\r |
1935 | typedef enum {\r | |
1936 | ManagementDeviceTypeOther = 0x01,\r | |
1937 | ManagementDeviceTypeUnknown = 0x02,\r | |
1938 | ManagementDeviceTypeLm75 = 0x03,\r | |
1939 | ManagementDeviceTypeLm78 = 0x04,\r | |
1940 | ManagementDeviceTypeLm79 = 0x05,\r | |
1941 | ManagementDeviceTypeLm80 = 0x06,\r | |
1942 | ManagementDeviceTypeLm81 = 0x07,\r | |
1943 | ManagementDeviceTypeAdm9240 = 0x08,\r | |
1944 | ManagementDeviceTypeDs1780 = 0x09,\r | |
1945 | ManagementDeviceTypeMaxim1617 = 0x0A,\r | |
1946 | ManagementDeviceTypeGl518Sm = 0x0B,\r | |
1947 | ManagementDeviceTypeW83781D = 0x0C,\r | |
1948 | ManagementDeviceTypeHt82H791 = 0x0D\r | |
1949 | } MISC_MANAGEMENT_DEVICE_TYPE;\r | |
1950 | \r | |
1951 | ///\r | |
af2dc6a7 | 1952 | /// Management Device - Address Type. \r |
98cb9ae8 | 1953 | ///\r |
1954 | typedef enum {\r | |
1955 | ManagementDeviceAddressTypeOther = 0x01,\r | |
1956 | ManagementDeviceAddressTypeUnknown = 0x02,\r | |
1957 | ManagementDeviceAddressTypeIOPort = 0x03,\r | |
1958 | ManagementDeviceAddressTypeMemory = 0x04,\r | |
1959 | ManagementDeviceAddressTypeSmbus = 0x05\r | |
1960 | } MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE;\r | |
1961 | \r | |
4135253b | 1962 | ///\r |
af2dc6a7 | 1963 | /// Management Device (Type 34).\r |
4135253b | 1964 | ///\r |
98cb9ae8 | 1965 | /// The information in this structure defines the attributes of a Management Device. \r |
1966 | /// A Management Device might control one or more fans or voltage, current, or temperature\r | |
1967 | /// probes as defined by one or more Management Device Component structures.\r | |
1968 | ///\r | |
61ce5861 | 1969 | typedef struct {\r |
98cb9ae8 | 1970 | SMBIOS_STRUCTURE Hdr;\r |
1971 | SMBIOS_TABLE_STRING Description;\r | |
af2dc6a7 | 1972 | UINT8 Type; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_TYPE.\r |
98cb9ae8 | 1973 | UINT32 Address;\r |
af2dc6a7 | 1974 | UINT8 AddressType; ///< The enumeration value from MISC_MANAGEMENT_DEVICE_ADDRESS_TYPE.\r |
61ce5861 | 1975 | } SMBIOS_TABLE_TYPE34;\r |
1976 | \r | |
4135253b | 1977 | ///\r |
1978 | /// Management Device Component (Type 35)\r | |
1979 | ///\r | |
98cb9ae8 | 1980 | /// This structure associates a cooling device or environmental probe with structures \r |
1981 | /// that define the controlling hardware device and (optionally) the component's thresholds. \r | |
1982 | ///\r | |
61ce5861 | 1983 | typedef struct {\r |
1984 | SMBIOS_STRUCTURE Hdr;\r | |
1985 | SMBIOS_TABLE_STRING Description;\r | |
1986 | UINT16 ManagementDeviceHandle;\r | |
1987 | UINT16 ComponentHandle;\r | |
1988 | UINT16 ThresholdHandle;\r | |
1989 | } SMBIOS_TABLE_TYPE35;\r | |
1990 | \r | |
4135253b | 1991 | ///\r |
af2dc6a7 | 1992 | /// Management Device Threshold Data (Type 36).\r |
4135253b | 1993 | ///\r |
98cb9ae8 | 1994 | /// The information in this structure defines threshold information for \r |
1995 | /// a component (probe or cooling-unit) contained within a Management Device. \r | |
1996 | ///\r | |
61ce5861 | 1997 | typedef struct {\r |
1998 | SMBIOS_STRUCTURE Hdr;\r | |
1999 | UINT16 LowerThresholdNonCritical;\r | |
2000 | UINT16 UpperThresholdNonCritical;\r | |
2001 | UINT16 LowerThresholdCritical;\r | |
2002 | UINT16 UpperThresholdCritical;\r | |
2003 | UINT16 LowerThresholdNonRecoverable;\r | |
2004 | UINT16 UpperThresholdNonRecoverable;\r | |
2005 | } SMBIOS_TABLE_TYPE36;\r | |
2006 | \r | |
bf7ea009 | 2007 | ///\r |
af2dc6a7 | 2008 | /// Memory Channel Entry.\r |
bf7ea009 | 2009 | ///\r |
61ce5861 | 2010 | typedef struct {\r |
2011 | UINT8 DeviceLoad;\r | |
2012 | UINT16 DeviceHandle;\r | |
2013 | } MEMORY_DEVICE;\r | |
2014 | \r | |
98cb9ae8 | 2015 | ///\r |
af2dc6a7 | 2016 | /// Memory Channel - Channel Type.\r |
98cb9ae8 | 2017 | ///\r |
2018 | typedef enum {\r | |
2019 | MemoryChannelTypeOther = 0x01,\r | |
2020 | MemoryChannelTypeUnknown = 0x02,\r | |
2021 | MemoryChannelTypeRambus = 0x03,\r | |
2022 | MemoryChannelTypeSyncLink = 0x04\r | |
2023 | } MEMORY_CHANNEL_TYPE;\r | |
2024 | \r | |
4135253b | 2025 | ///\r |
2026 | /// Memory Channel (Type 37)\r | |
2027 | ///\r | |
98cb9ae8 | 2028 | /// The information in this structure provides the correlation between a Memory Channel\r |
af2dc6a7 | 2029 | /// and its associated Memory Devices. Each device presents one or more loads to the channel. \r |
2030 | /// The sum of all device loads cannot exceed the channel's defined maximum.\r | |
98cb9ae8 | 2031 | ///\r |
61ce5861 | 2032 | typedef struct {\r |
2033 | SMBIOS_STRUCTURE Hdr;\r | |
2034 | UINT8 ChannelType;\r | |
2035 | UINT8 MaximumChannelLoad;\r | |
2036 | UINT8 MemoryDeviceCount;\r | |
2037 | MEMORY_DEVICE MemoryDevice[1];\r | |
2038 | } SMBIOS_TABLE_TYPE37;\r | |
2039 | \r | |
98cb9ae8 | 2040 | ///\r |
2041 | /// IPMI Device Information - BMC Interface Type\r | |
2042 | ///\r | |
2043 | typedef enum {\r | |
2044 | IPMIDeviceInfoInterfaceTypeUnknown = 0x00,\r | |
af2dc6a7 | 2045 | IPMIDeviceInfoInterfaceTypeKCS = 0x01, ///< The Keyboard Controller Style.\r |
2046 | IPMIDeviceInfoInterfaceTypeSMIC = 0x02, ///< The Server Management Interface Chip.\r | |
2047 | IPMIDeviceInfoInterfaceTypeBT = 0x03, ///< The Block Transfer\r | |
98cb9ae8 | 2048 | IPMIDeviceInfoInterfaceTypeReserved = 0x04\r |
2049 | } BMC_INTERFACE_TYPE;\r | |
2050 | \r | |
4135253b | 2051 | ///\r |
af2dc6a7 | 2052 | /// IPMI Device Information (Type 38).\r |
4135253b | 2053 | ///\r |
7ddba202 | 2054 | /// The information in this structure defines the attributes of an\r |
98cb9ae8 | 2055 | /// Intelligent Platform Management Interface (IPMI) Baseboard Management Controller (BMC).\r |
7ddba202 SZ |
2056 | ///\r |
2057 | /// The Type 42 structure can also be used to describe a physical management controller\r | |
2058 | /// host interface and one or more protocols that share that interface. If IPMI is not\r | |
2059 | /// shared with other protocols, either the Type 38 or Type 42 structures can be used.\r | |
2060 | /// Providing Type 38 is recommended for backward compatibility.\r | |
2061 | ///\r | |
61ce5861 | 2062 | typedef struct {\r |
2063 | SMBIOS_STRUCTURE Hdr;\r | |
af2dc6a7 | 2064 | UINT8 InterfaceType; ///< The enumeration value from BMC_INTERFACE_TYPE.\r |
61ce5861 | 2065 | UINT8 IPMISpecificationRevision;\r |
2066 | UINT8 I2CSlaveAddress;\r | |
2067 | UINT8 NVStorageDeviceAddress;\r | |
2068 | UINT64 BaseAddress;\r | |
2069 | UINT8 BaseAddressModifier_InterruptInfo;\r | |
2070 | UINT8 InterruptNumber;\r | |
2071 | } SMBIOS_TABLE_TYPE38;\r | |
2072 | \r | |
98cb9ae8 | 2073 | ///\r |
af2dc6a7 | 2074 | /// System Power Supply - Power Supply Characteristics.\r |
98cb9ae8 | 2075 | ///\r |
2076 | typedef struct {\r | |
2077 | UINT16 PowerSupplyHotReplaceable:1;\r | |
2078 | UINT16 PowerSupplyPresent :1;\r | |
2079 | UINT16 PowerSupplyUnplugged :1;\r | |
2080 | UINT16 InputVoltageRangeSwitch :4;\r | |
2081 | UINT16 PowerSupplyStatus :3;\r | |
2082 | UINT16 PowerSupplyType :4;\r | |
2083 | UINT16 Reserved :2;\r | |
2084 | } SYS_POWER_SUPPLY_CHARACTERISTICS;\r | |
2085 | \r | |
4135253b | 2086 | ///\r |
af2dc6a7 | 2087 | /// System Power Supply (Type 39).\r |
4135253b | 2088 | ///\r |
7ddba202 SZ |
2089 | /// This structure identifies attributes of a system power supply. One instance\r |
2090 | /// of this record is present for each possible power supply in a system.\r | |
98cb9ae8 | 2091 | ///\r |
61ce5861 | 2092 | typedef struct {\r |
98cb9ae8 | 2093 | SMBIOS_STRUCTURE Hdr;\r |
2094 | UINT8 PowerUnitGroup;\r | |
2095 | SMBIOS_TABLE_STRING Location;\r | |
2096 | SMBIOS_TABLE_STRING DeviceName;\r | |
2097 | SMBIOS_TABLE_STRING Manufacturer;\r | |
2098 | SMBIOS_TABLE_STRING SerialNumber;\r | |
2099 | SMBIOS_TABLE_STRING AssetTagNumber;\r | |
2100 | SMBIOS_TABLE_STRING ModelPartNumber;\r | |
2101 | SMBIOS_TABLE_STRING RevisionLevel;\r | |
2102 | UINT16 MaxPowerCapacity;\r | |
2103 | SYS_POWER_SUPPLY_CHARACTERISTICS PowerSupplyCharacteristics;\r | |
2104 | UINT16 InputVoltageProbeHandle;\r | |
2105 | UINT16 CoolingDeviceHandle;\r | |
2106 | UINT16 InputCurrentProbeHandle;\r | |
61ce5861 | 2107 | } SMBIOS_TABLE_TYPE39;\r |
2108 | \r | |
bf7ea009 | 2109 | ///\r |
af2dc6a7 | 2110 | /// Additional Information Entry Format. \r |
bf7ea009 | 2111 | ///\r |
61ce5861 | 2112 | typedef struct { \r |
2113 | UINT8 EntryLength; \r | |
2114 | UINT16 ReferencedHandle;\r | |
2115 | UINT8 ReferencedOffset;\r | |
2116 | SMBIOS_TABLE_STRING EntryString;\r | |
2117 | UINT8 Value[1];\r | |
2118 | }ADDITIONAL_INFORMATION_ENTRY;\r | |
2119 | \r | |
4135253b | 2120 | ///\r |
af2dc6a7 | 2121 | /// Additional Information (Type 40).\r |
4135253b | 2122 | ///\r |
98cb9ae8 | 2123 | /// This structure is intended to provide additional information for handling unspecified \r |
2124 | /// enumerated values and interim field updates in another structure. \r | |
2125 | ///\r | |
61ce5861 | 2126 | typedef struct {\r |
2127 | SMBIOS_STRUCTURE Hdr;\r | |
2128 | UINT8 NumberOfAdditionalInformationEntries;\r | |
2129 | ADDITIONAL_INFORMATION_ENTRY AdditionalInfoEntries[1]; \r | |
2130 | } SMBIOS_TABLE_TYPE40;\r | |
2131 | \r | |
98cb9ae8 | 2132 | ///\r |
af2dc6a7 | 2133 | /// Onboard Devices Extended Information - Onboard Device Types.\r |
98cb9ae8 | 2134 | ///\r |
2135 | typedef enum{\r | |
2136 | OnBoardDeviceExtendedTypeOther = 0x01,\r | |
2137 | OnBoardDeviceExtendedTypeUnknown = 0x02,\r | |
2138 | OnBoardDeviceExtendedTypeVideo = 0x03,\r | |
2139 | OnBoardDeviceExtendedTypeScsiController = 0x04,\r | |
2140 | OnBoardDeviceExtendedTypeEthernet = 0x05,\r | |
2141 | OnBoardDeviceExtendedTypeTokenRing = 0x06,\r | |
2142 | OnBoardDeviceExtendedTypeSound = 0x07,\r | |
2143 | OnBoardDeviceExtendedTypePATAController = 0x08,\r | |
2144 | OnBoardDeviceExtendedTypeSATAController = 0x09,\r | |
2145 | OnBoardDeviceExtendedTypeSASController = 0x0A\r | |
2146 | } ONBOARD_DEVICE_EXTENDED_INFO_TYPE;\r | |
2147 | \r | |
4135253b | 2148 | ///\r |
af2dc6a7 | 2149 | /// Onboard Devices Extended Information (Type 41).\r |
4135253b | 2150 | ///\r |
98cb9ae8 | 2151 | /// The information in this structure defines the attributes of devices that \r |
2152 | /// are onboard (soldered onto) a system element, usually the baseboard. \r | |
2153 | /// In general, an entry in this table implies that the BIOS has some level of \r | |
2154 | /// control over the enabling of the associated device for use by the system. \r | |
2155 | ///\r | |
61ce5861 | 2156 | typedef struct {\r |
98cb9ae8 | 2157 | SMBIOS_STRUCTURE Hdr;\r |
2158 | SMBIOS_TABLE_STRING ReferenceDesignation;\r | |
af2dc6a7 | 2159 | UINT8 DeviceType; ///< The enumeration value from ONBOARD_DEVICE_EXTENDED_INFO_TYPE\r |
98cb9ae8 | 2160 | UINT8 DeviceTypeInstance;\r |
2161 | UINT16 SegmentGroupNum;\r | |
2162 | UINT8 BusNum;\r | |
7ddba202 | 2163 | UINT8 DevFuncNum;\r |
61ce5861 | 2164 | } SMBIOS_TABLE_TYPE41;\r |
2165 | \r | |
7ddba202 SZ |
2166 | ///\r |
2167 | /// Management Controller Host Interface (Type 42).\r | |
2168 | ///\r | |
2169 | /// The information in this structure defines the attributes of a Management\r | |
2170 | /// Controller Host Interface that is not discoverable by "Plug and Play" mechanisms.\r | |
2171 | ///\r | |
2172 | /// Type 42 should be used for management controller host interfaces that use protocols\r | |
2173 | /// other than IPMI or that use multiple protocols on a single host interface type.\r | |
2174 | ///\r | |
2175 | /// This structure should also be provided if IPMI is shared with other protocols\r | |
2176 | /// over the same interface hardware. If IPMI is not shared with other protocols,\r | |
2177 | /// either the Type 38 or Type 42 structures can be used. Providing Type 38 is\r | |
2178 | /// recommended for backward compatibility. The structures are not required to\r | |
2179 | /// be mutually exclusive. Type 38 and Type 42 structures may be implemented\r | |
2180 | /// simultaneously to provide backward compatibility with IPMI applications or drivers\r | |
2181 | /// that do not yet recognize the Type 42 structure.\r | |
2182 | ///\r | |
2183 | typedef struct {\r | |
2184 | SMBIOS_STRUCTURE Hdr;\r | |
2185 | UINT8 InterfaceType;\r | |
2186 | UINT8 MCHostInterfaceData[1]; ///< This field has a minimum of four bytes\r | |
2187 | } SMBIOS_TABLE_TYPE42;\r | |
2188 | \r | |
4135253b | 2189 | ///\r |
2190 | /// Inactive (Type 126)\r | |
2191 | ///\r | |
61ce5861 | 2192 | typedef struct {\r |
2193 | SMBIOS_STRUCTURE Hdr;\r | |
2194 | } SMBIOS_TABLE_TYPE126;\r | |
2195 | \r | |
4135253b | 2196 | ///\r |
2197 | /// End-of-Table (Type 127)\r | |
2198 | ///\r | |
61ce5861 | 2199 | typedef struct {\r |
2200 | SMBIOS_STRUCTURE Hdr;\r | |
2201 | } SMBIOS_TABLE_TYPE127;\r | |
2202 | \r | |
4135253b | 2203 | ///\r |
af2dc6a7 | 2204 | /// Union of all the possible SMBIOS record types.\r |
4135253b | 2205 | ///\r |
61ce5861 | 2206 | typedef union {\r |
2207 | SMBIOS_STRUCTURE *Hdr;\r | |
2208 | SMBIOS_TABLE_TYPE0 *Type0;\r | |
2209 | SMBIOS_TABLE_TYPE1 *Type1;\r | |
2210 | SMBIOS_TABLE_TYPE2 *Type2;\r | |
2211 | SMBIOS_TABLE_TYPE3 *Type3;\r | |
2212 | SMBIOS_TABLE_TYPE4 *Type4;\r | |
2213 | SMBIOS_TABLE_TYPE5 *Type5;\r | |
2214 | SMBIOS_TABLE_TYPE6 *Type6;\r | |
2215 | SMBIOS_TABLE_TYPE7 *Type7;\r | |
2216 | SMBIOS_TABLE_TYPE8 *Type8;\r | |
2217 | SMBIOS_TABLE_TYPE9 *Type9;\r | |
2218 | SMBIOS_TABLE_TYPE10 *Type10;\r | |
2219 | SMBIOS_TABLE_TYPE11 *Type11;\r | |
2220 | SMBIOS_TABLE_TYPE12 *Type12;\r | |
2221 | SMBIOS_TABLE_TYPE13 *Type13;\r | |
2222 | SMBIOS_TABLE_TYPE14 *Type14;\r | |
2223 | SMBIOS_TABLE_TYPE15 *Type15;\r | |
2224 | SMBIOS_TABLE_TYPE16 *Type16;\r | |
2225 | SMBIOS_TABLE_TYPE17 *Type17;\r | |
2226 | SMBIOS_TABLE_TYPE18 *Type18;\r | |
2227 | SMBIOS_TABLE_TYPE19 *Type19;\r | |
2228 | SMBIOS_TABLE_TYPE20 *Type20;\r | |
2229 | SMBIOS_TABLE_TYPE21 *Type21;\r | |
2230 | SMBIOS_TABLE_TYPE22 *Type22;\r | |
2231 | SMBIOS_TABLE_TYPE23 *Type23;\r | |
2232 | SMBIOS_TABLE_TYPE24 *Type24;\r | |
2233 | SMBIOS_TABLE_TYPE25 *Type25;\r | |
2234 | SMBIOS_TABLE_TYPE26 *Type26;\r | |
2235 | SMBIOS_TABLE_TYPE27 *Type27;\r | |
2236 | SMBIOS_TABLE_TYPE28 *Type28;\r | |
2237 | SMBIOS_TABLE_TYPE29 *Type29;\r | |
2238 | SMBIOS_TABLE_TYPE30 *Type30;\r | |
2239 | SMBIOS_TABLE_TYPE31 *Type31;\r | |
2240 | SMBIOS_TABLE_TYPE32 *Type32;\r | |
2241 | SMBIOS_TABLE_TYPE33 *Type33;\r | |
2242 | SMBIOS_TABLE_TYPE34 *Type34;\r | |
2243 | SMBIOS_TABLE_TYPE35 *Type35;\r | |
2244 | SMBIOS_TABLE_TYPE36 *Type36;\r | |
2245 | SMBIOS_TABLE_TYPE37 *Type37;\r | |
2246 | SMBIOS_TABLE_TYPE38 *Type38;\r | |
2247 | SMBIOS_TABLE_TYPE39 *Type39;\r | |
2248 | SMBIOS_TABLE_TYPE40 *Type40;\r | |
2249 | SMBIOS_TABLE_TYPE41 *Type41;\r | |
884f9295 | 2250 | SMBIOS_TABLE_TYPE42 *Type42;\r |
61ce5861 | 2251 | SMBIOS_TABLE_TYPE126 *Type126;\r |
2252 | SMBIOS_TABLE_TYPE127 *Type127;\r | |
2253 | UINT8 *Raw;\r | |
2254 | } SMBIOS_STRUCTURE_POINTER;\r | |
2255 | \r | |
766f4bc1 | 2256 | #pragma pack()\r |
2257 | \r | |
a7ed1e2e | 2258 | #endif\r |