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1 | /** @file\r |
2 | Platform TPM Profile Specification definition for TPM2.0.\r | |
3 | It covers both FIFO and CRB interface.\r | |
4 | \r | |
714eedc5 | 5 | Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r |
fb7abaca JY |
6 | This program and the accompanying materials\r |
7 | are licensed and made available under the terms and conditions of the BSD License\r | |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #ifndef _TPM_PTP_H_\r | |
17 | #define _TPM_PTP_H_\r | |
18 | \r | |
19 | //\r | |
20 | // PTP FIFO definition\r | |
21 | //\r | |
22 | \r | |
23 | //\r | |
24 | // Set structure alignment to 1-byte\r | |
25 | //\r | |
26 | #pragma pack (1)\r | |
27 | \r | |
28 | //\r | |
29 | // Register set map as specified in PTP specification Chapter 5\r | |
30 | //\r | |
31 | typedef struct {\r | |
32 | ///\r | |
33 | /// Used to gain ownership for this particular port.\r | |
34 | ///\r | |
35 | UINT8 Access; // 0\r | |
36 | UINT8 Reserved1[7]; // 1\r | |
37 | ///\r | |
38 | /// Controls interrupts.\r | |
39 | ///\r | |
40 | UINT32 IntEnable; // 8\r | |
41 | ///\r | |
42 | /// SIRQ vector to be used by the TPM.\r | |
43 | ///\r | |
44 | UINT8 IntVector; // 0ch\r | |
45 | UINT8 Reserved2[3]; // 0dh\r | |
46 | ///\r | |
47 | /// What caused interrupt.\r | |
48 | ///\r | |
49 | UINT32 IntSts; // 10h\r | |
50 | ///\r | |
51 | /// Shows which interrupts are supported by that particular TPM.\r | |
52 | ///\r | |
53 | UINT32 InterfaceCapability;// 14h\r | |
54 | ///\r | |
55 | /// Status Register. Provides status of the TPM.\r | |
56 | ///\r | |
57 | UINT8 Status; // 18h\r | |
58 | ///\r | |
59 | /// Number of consecutive writes that can be done to the TPM.\r | |
60 | ///\r | |
61 | UINT16 BurstCount; // 19h\r | |
62 | ///\r | |
63 | /// Additional Status Register.\r | |
64 | ///\r | |
65 | UINT8 StatusEx; // 1Bh\r | |
66 | UINT8 Reserved3[8];\r | |
67 | ///\r | |
68 | /// Read or write FIFO, depending on transaction.\r | |
69 | ///\r | |
70 | UINT32 DataFifo; // 24h\r | |
71 | UINT8 Reserved4[8]; // 28h\r | |
72 | ///\r | |
73 | /// Used to identify the Interface types supported by the TPM.\r | |
74 | ///\r | |
75 | UINT32 InterfaceId; // 30h\r | |
76 | UINT8 Reserved5[0x4c]; // 34h\r | |
77 | ///\r | |
78 | /// Extended ReadFIFO or WriteFIFO, depending on the current bus cycle (read or write)\r | |
79 | ///\r | |
80 | UINT32 XDataFifo; // 80h\r | |
81 | UINT8 Reserved6[0xe7c]; // 84h\r | |
82 | ///\r | |
83 | /// Vendor ID\r | |
84 | ///\r | |
85 | UINT16 Vid; // 0f00h\r | |
86 | ///\r | |
87 | /// Device ID\r | |
88 | ///\r | |
89 | UINT16 Did; // 0f02h\r | |
90 | ///\r | |
91 | /// Revision ID\r | |
92 | ///\r | |
93 | UINT8 Rid; // 0f04h\r | |
94 | UINT8 Reserved[0xfb]; // 0f05h\r | |
95 | } PTP_FIFO_REGISTERS;\r | |
96 | \r | |
97 | //\r | |
98 | // Restore original structure alignment\r | |
99 | //\r | |
100 | #pragma pack ()\r | |
101 | \r | |
102 | //\r | |
103 | // Define pointer types used to access TIS registers on PC\r | |
104 | //\r | |
105 | typedef PTP_FIFO_REGISTERS *PTP_FIFO_REGISTERS_PTR;\r | |
106 | \r | |
107 | //\r | |
108 | // Define bits of FIFO Interface Identifier Register\r | |
109 | //\r | |
110 | typedef union {\r | |
111 | struct {\r | |
112 | UINT32 InterfaceType:4;\r | |
113 | UINT32 InterfaceVersion:4;\r | |
114 | UINT32 CapLocality:1;\r | |
115 | UINT32 Reserved1:2;\r | |
116 | UINT32 CapDataXferSizeSupport:2;\r | |
117 | UINT32 CapFIFO:1;\r | |
118 | UINT32 CapCRB:1;\r | |
119 | UINT32 CapIFRes:2;\r | |
120 | UINT32 InterfaceSelector:2;\r | |
121 | UINT32 IntfSelLock:1;\r | |
122 | UINT32 Reserved2:4;\r | |
123 | UINT32 Reserved3:8;\r | |
124 | } Bits;\r | |
125 | UINT32 Uint32;\r | |
126 | } PTP_FIFO_INTERFACE_IDENTIFIER;\r | |
127 | \r | |
128 | //\r | |
129 | // Define bits of FIFO Interface Capability Register\r | |
130 | //\r | |
131 | typedef union {\r | |
132 | struct {\r | |
133 | UINT32 DataAvailIntSupport:1;\r | |
134 | UINT32 StsValidIntSupport:1;\r | |
135 | UINT32 LocalityChangeIntSupport:1;\r | |
136 | UINT32 InterruptLevelHigh:1;\r | |
137 | UINT32 InterruptLevelLow:1;\r | |
138 | UINT32 InterruptEdgeRising:1;\r | |
139 | UINT32 InterruptEdgeFalling:1;\r | |
140 | UINT32 CommandReadyIntSupport:1;\r | |
141 | UINT32 BurstCountStatic:1;\r | |
142 | UINT32 DataTransferSizeSupport:2;\r | |
143 | UINT32 Reserved:17;\r | |
144 | UINT32 InterfaceVersion:3;\r | |
145 | UINT32 Reserved2:1;\r | |
146 | } Bits;\r | |
147 | UINT32 Uint32;\r | |
148 | } PTP_FIFO_INTERFACE_CAPABILITY;\r | |
149 | \r | |
150 | ///\r | |
151 | /// InterfaceVersion\r | |
152 | ///\r | |
153 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_12 0x0\r | |
154 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_TIS_13 0x2\r | |
155 | #define INTERFACE_CAPABILITY_INTERFACE_VERSION_PTP 0x3\r | |
156 | \r | |
157 | \r | |
158 | //\r | |
159 | // Define bits of ACCESS and STATUS registers\r | |
160 | //\r | |
161 | \r | |
162 | ///\r | |
163 | /// This bit is a 1 to indicate that the other bits in this register are valid.\r | |
164 | ///\r | |
165 | #define PTP_FIFO_VALID BIT7\r | |
166 | ///\r | |
167 | /// Indicate that this locality is active.\r | |
168 | ///\r | |
169 | #define PTP_FIFO_ACC_ACTIVE BIT5\r | |
170 | ///\r | |
171 | /// Set to 1 to indicate that this locality had the TPM taken away while\r | |
172 | /// this locality had the TIS_PC_ACC_ACTIVE bit set.\r | |
173 | ///\r | |
174 | #define PTP_FIFO_ACC_SEIZED BIT4\r | |
175 | ///\r | |
176 | /// Set to 1 to indicate that TPM MUST reset the\r | |
177 | /// TIS_PC_ACC_ACTIVE bit and remove ownership for localities less than the\r | |
178 | /// locality that is writing this bit.\r | |
179 | ///\r | |
180 | #define PTP_FIFO_ACC_SEIZE BIT3\r | |
181 | ///\r | |
182 | /// When this bit is 1, another locality is requesting usage of the TPM.\r | |
183 | ///\r | |
184 | #define PTP_FIFO_ACC_PENDIND BIT2\r | |
185 | ///\r | |
186 | /// Set to 1 to indicate that this locality is requesting to use TPM.\r | |
187 | ///\r | |
188 | #define PTP_FIFO_ACC_RQUUSE BIT1\r | |
189 | ///\r | |
190 | /// A value of 1 indicates that a T/OS has not been established on the platform\r | |
191 | ///\r | |
192 | #define PTP_FIFO_ACC_ESTABLISH BIT0\r | |
193 | \r | |
194 | ///\r | |
195 | /// This field indicates that STS_DATA and STS_EXPECT are valid\r | |
196 | ///\r | |
197 | #define PTP_FIFO_STS_VALID BIT7\r | |
198 | ///\r | |
199 | /// When this bit is 1, TPM is in the Ready state,\r | |
200 | /// indicating it is ready to receive a new command.\r | |
201 | ///\r | |
202 | #define PTP_FIFO_STS_READY BIT6\r | |
203 | ///\r | |
204 | /// Write a 1 to this bit to cause the TPM to execute that command.\r | |
205 | ///\r | |
206 | #define PTP_FIFO_STS_GO BIT5\r | |
207 | ///\r | |
208 | /// This bit indicates that the TPM has data available as a response.\r | |
209 | ///\r | |
210 | #define PTP_FIFO_STS_DATA BIT4\r | |
211 | ///\r | |
212 | /// The TPM sets this bit to a value of 1 when it expects another byte of data for a command.\r | |
213 | ///\r | |
214 | #define PTP_FIFO_STS_EXPECT BIT3\r | |
215 | ///\r | |
216 | /// Indicates that the TPM has completed all self-test actions following a TPM_ContinueSelfTest command.\r | |
217 | ///\r | |
218 | #define PTP_FIFO_STS_SELFTEST_DONE BIT2\r | |
219 | ///\r | |
220 | /// Writes a 1 to this bit to force the TPM to re-send the response.\r | |
221 | ///\r | |
222 | #define PTP_FIFO_STS_RETRY BIT1\r | |
223 | \r | |
224 | ///\r | |
225 | /// TPM Family Identifier.\r | |
226 | /// 00: TPM 1.2 Family\r | |
227 | /// 01: TPM 2.0 Family\r | |
228 | ///\r | |
229 | #define PTP_FIFO_STS_EX_TPM_FAMILY (BIT2 | BIT3)\r | |
230 | #define PTP_FIFO_STS_EX_TPM_FAMILY_OFFSET (2)\r | |
231 | #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM12 (0)\r | |
232 | #define PTP_FIFO_STS_EX_TPM_FAMILY_TPM20 (BIT2)\r | |
233 | ///\r | |
234 | /// A write of 1 after tpmGo and before dataAvail aborts the currently executing command, resulting in a response of TPM_RC_CANCELLED.\r | |
235 | /// A write of 1 after dataAvail and before tpmGo is ignored by the TPM.\r | |
236 | ///\r | |
237 | #define PTP_FIFO_STS_EX_CANCEL BIT0\r | |
238 | \r | |
239 | \r | |
240 | //\r | |
241 | // PTP CRB definition\r | |
242 | //\r | |
243 | \r | |
244 | //\r | |
245 | // Set structure alignment to 1-byte\r | |
246 | //\r | |
247 | #pragma pack (1)\r | |
248 | \r | |
249 | //\r | |
250 | // Register set map as specified in PTP specification Chapter 5\r | |
251 | //\r | |
252 | typedef struct {\r | |
253 | ///\r | |
254 | /// Used to determine current state of Locality of the TPM.\r | |
255 | ///\r | |
256 | UINT32 LocalityState; // 0\r | |
257 | UINT8 Reserved1[4]; // 4\r | |
258 | ///\r | |
259 | /// Used to gain control of the TPM by this Locality.\r | |
260 | ///\r | |
261 | UINT32 LocalityControl; // 8\r | |
262 | ///\r | |
263 | /// Used to determine whether Locality has been granted or Seized.\r | |
264 | ///\r | |
265 | UINT32 LocalityStatus; // 0ch\r | |
266 | UINT8 Reserved2[0x20]; // 10h\r | |
267 | ///\r | |
268 | /// Used to identify the Interface types supported by the TPM.\r | |
269 | ///\r | |
270 | UINT32 InterfaceId; // 30h\r | |
271 | ///\r | |
272 | /// Vendor ID\r | |
273 | ///\r | |
274 | UINT16 Vid; // 34h\r | |
275 | ///\r | |
276 | /// Device ID\r | |
277 | ///\r | |
278 | UINT16 Did; // 36h\r | |
279 | ///\r | |
280 | /// Optional Register used in low memory environments prior to CRB_DATA_BUFFER availability.\r | |
281 | ///\r | |
282 | UINT64 CrbControlExtension; // 38h\r | |
283 | ///\r | |
284 | /// Register used to initiate transactions for the CRB interface.\r | |
285 | ///\r | |
286 | UINT32 CrbControlRequest; // 40h\r | |
287 | ///\r | |
288 | /// Register used by the TPM to provide status of the CRB interface.\r | |
289 | ///\r | |
290 | UINT32 CrbControlStatus; // 44h\r | |
291 | ///\r | |
292 | /// Register used by software to cancel command processing.\r | |
293 | ///\r | |
294 | UINT32 CrbControlCancel; // 48h\r | |
295 | ///\r | |
296 | /// Register used to indicate presence of command or response data in the CRB buffer.\r | |
297 | ///\r | |
298 | UINT32 CrbControlStart; // 4Ch\r | |
299 | ///\r | |
300 | /// Register used to configure and respond to interrupts.\r | |
301 | ///\r | |
302 | UINT32 CrbInterruptEnable; // 50h\r | |
303 | UINT32 CrbInterruptStatus; // 54h\r | |
304 | ///\r | |
305 | /// Size of the Command buffer.\r | |
306 | ///\r | |
307 | UINT32 CrbControlCommandSize; // 58h\r | |
308 | ///\r | |
309 | /// Command buffer start address\r | |
310 | ///\r | |
311 | UINT32 CrbControlCommandAddressLow; // 5Ch\r | |
312 | UINT32 CrbControlCommandAddressHigh; // 60h\r | |
313 | ///\r | |
314 | /// Size of the Response buffer\r | |
315 | ///\r | |
316 | UINT32 CrbControlResponseSize; // 64h\r | |
317 | ///\r | |
318 | /// Address of the start of the Response buffer\r | |
319 | ///\r | |
320 | UINT64 CrbControlResponseAddrss; // 68h\r | |
321 | UINT8 Reserved4[0x10]; // 70h\r | |
322 | ///\r | |
323 | /// Command/Response Data may be defined as large as 3968 (0xF80).\r | |
324 | ///\r | |
325 | UINT8 CrbDataBuffer[0xF80]; // 80h\r | |
326 | } PTP_CRB_REGISTERS;\r | |
327 | \r | |
328 | //\r | |
329 | // Define pointer types used to access CRB registers on PTP\r | |
330 | //\r | |
331 | typedef PTP_CRB_REGISTERS *PTP_CRB_REGISTERS_PTR;\r | |
332 | \r | |
333 | //\r | |
334 | // Define bits of CRB Interface Identifier Register\r | |
335 | //\r | |
336 | typedef union {\r | |
337 | struct {\r | |
338 | UINT32 InterfaceType:4;\r | |
339 | UINT32 InterfaceVersion:4;\r | |
340 | UINT32 CapLocality:1;\r | |
714eedc5 ZC |
341 | UINT32 CapCRBIdleBypass:1;\r |
342 | UINT32 Reserved1:1;\r | |
fb7abaca JY |
343 | UINT32 CapDataXferSizeSupport:2;\r |
344 | UINT32 CapFIFO:1;\r | |
345 | UINT32 CapCRB:1;\r | |
346 | UINT32 CapIFRes:2;\r | |
347 | UINT32 InterfaceSelector:2;\r | |
348 | UINT32 IntfSelLock:1;\r | |
349 | UINT32 Reserved2:4;\r | |
350 | UINT32 Rid:8;\r | |
351 | } Bits;\r | |
352 | UINT32 Uint32;\r | |
353 | } PTP_CRB_INTERFACE_IDENTIFIER;\r | |
354 | \r | |
355 | ///\r | |
356 | /// InterfaceType\r | |
357 | ///\r | |
358 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_FIFO 0x0\r | |
359 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_CRB 0x1\r | |
360 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_TYPE_TIS 0xF\r | |
361 | \r | |
362 | ///\r | |
363 | /// InterfaceVersion\r | |
364 | ///\r | |
365 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_FIFO 0x0\r | |
366 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_VERSION_CRB 0x1\r | |
367 | \r | |
368 | ///\r | |
369 | /// InterfaceSelector\r | |
370 | ///\r | |
371 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_FIFO 0x0\r | |
372 | #define PTP_INTERFACE_IDENTIFIER_INTERFACE_SELECTOR_CRB 0x1\r | |
373 | \r | |
374 | //\r | |
375 | // Define bits of Locality State Register\r | |
376 | //\r | |
377 | \r | |
378 | ///\r | |
379 | /// This bit indicates whether all other bits of this register contain valid values, if it is a 1.\r | |
380 | ///\r | |
381 | #define PTP_CRB_LOCALITY_STATE_TPM_REG_VALID_STATUS BIT7\r | |
382 | \r | |
383 | ///\r | |
384 | /// 000 - Locality 0\r | |
385 | /// 001 - Locality 1\r | |
386 | /// 010 - Locality 2\r | |
387 | /// 011 - Locality 3\r | |
388 | /// 100 - Locality 4\r | |
389 | ///\r | |
390 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_MASK (BIT2 | BIT3 | BIT4)\r | |
391 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_0 (0)\r | |
392 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_1 (BIT2)\r | |
393 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_2 (BIT3)\r | |
394 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_3 (BIT2 | BIT3)\r | |
395 | #define PTP_CRB_LOCALITY_STATE_ACTIVE_LOCALITY_4 (BIT4)\r | |
396 | \r | |
397 | ///\r | |
398 | /// A 0 indicates to the host that no locality is assigned.\r | |
399 | /// A 1 indicates a locality has been assigned.\r | |
400 | ///\r | |
401 | #define PTP_CRB_LOCALITY_STATE_LOCALITY_ASSIGNED BIT1\r | |
402 | \r | |
403 | ///\r | |
404 | /// The TPM clears this bit to 0 upon receipt of _TPM_Hash_End\r | |
405 | /// The TPM sets this bit to a 1 when the TPM_LOC_CTRL_x.resetEstablishment field is set to 1.\r | |
406 | ///\r | |
407 | #define PTP_CRB_LOCALITY_STATE_TPM_ESTABLISHED BIT0\r | |
408 | \r | |
409 | //\r | |
410 | // Define bits of Locality Control Register\r | |
411 | //\r | |
412 | \r | |
413 | ///\r | |
414 | /// Writes (1): Reset TPM_LOC_STATE_x.tpmEstablished bit if the write occurs from Locality 3 or 4.\r | |
415 | ///\r | |
416 | #define PTP_CRB_LOCALITY_CONTROL_RESET_ESTABLISHMENT_BIT BIT3\r | |
417 | \r | |
418 | ///\r | |
419 | /// Writes (1): The TPM gives control of the TPM to the locality setting this bit if it is the higher priority locality.\r | |
420 | ///\r | |
421 | #define PTP_CRB_LOCALITY_CONTROL_SEIZE BIT2\r | |
422 | \r | |
423 | ///\r | |
424 | /// Writes (1): The active Locality is done with the TPM.\r | |
425 | ///\r | |
426 | #define PTP_CRB_LOCALITY_CONTROL_RELINQUISH BIT1\r | |
427 | \r | |
428 | ///\r | |
429 | /// Writes (1): Interrupt the TPM and generate a locality arbitration algorithm.\r | |
430 | ///\r | |
431 | #define PTP_CRB_LOCALITY_CONTROL_REQUEST_ACCESS BIT0\r | |
432 | \r | |
433 | //\r | |
434 | // Define bits of Locality Status Register\r | |
435 | //\r | |
436 | \r | |
437 | ///\r | |
438 | /// 0: A higher locality has not initiated a Seize arbitration process.\r | |
439 | /// 1: A higher locality has Seized the TPM from this locality.\r | |
440 | ///\r | |
441 | #define PTP_CRB_LOCALITY_STATUS_BEEN_SEIZED BIT1\r | |
442 | \r | |
443 | ///\r | |
444 | /// 0: Locality has not been granted to the TPM.\r | |
445 | /// 1: Locality has been granted access to the TPM\r | |
446 | ///\r | |
447 | #define PTP_CRB_LOCALITY_STATUS_GRANTED BIT0\r | |
448 | \r | |
449 | //\r | |
450 | // Define bits of CRB Control Area Request Register\r | |
451 | //\r | |
452 | \r | |
453 | ///\r | |
454 | /// Used by Software to indicate transition the TPM to and from the Idle state\r | |
455 | /// 1: Set by Software to indicate response has been read from the response buffer and TPM can transition to Idle\r | |
456 | /// 0: Cleared to 0 by TPM to acknowledge the request when TPM enters Idle state.\r | |
457 | /// TPM SHALL complete this transition within TIMEOUT_C.\r | |
458 | ///\r | |
459 | #define PTP_CRB_CONTROL_AREA_REQUEST_GO_IDLE BIT1\r | |
460 | \r | |
461 | ///\r | |
462 | /// Used by Software to request the TPM transition to the Ready State.\r | |
463 | /// 1: Set to 1 by Software to indicate the TPM should be ready to receive a command.\r | |
464 | /// 0: Cleared to 0 by TPM to acknowledge the request.\r | |
465 | /// TPM SHALL complete this transition within TIMEOUT_C.\r | |
466 | ///\r | |
467 | #define PTP_CRB_CONTROL_AREA_REQUEST_COMMAND_READY BIT0\r | |
468 | \r | |
469 | //\r | |
470 | // Define bits of CRB Control Area Status Register\r | |
471 | //\r | |
472 | \r | |
473 | ///\r | |
474 | /// Used by TPM to indicate it is in the Idle State\r | |
475 | /// 1: Set by TPM when in the Idle State\r | |
476 | /// 0: Cleared by TPM on receipt of TPM_CRB_CTRL_REQ_x.cmdReady when TPM transitions to the Ready State.\r | |
477 | /// SHALL be cleared by TIMEOUT_C.\r | |
478 | ///\r | |
479 | #define PTP_CRB_CONTROL_AREA_STATUS_TPM_IDLE BIT1\r | |
480 | \r | |
481 | ///\r | |
482 | /// Used by the TPM to indicate current status.\r | |
483 | /// 1: Set by TPM to indicate a FATAL Error\r | |
484 | /// 0: Indicates TPM is operational\r | |
485 | ///\r | |
486 | #define PTP_CRB_CONTROL_AREA_STATUS_TPM_STATUS BIT0\r | |
487 | \r | |
488 | //\r | |
489 | // Define bits of CRB Control Cancel Register\r | |
490 | //\r | |
491 | \r | |
492 | ///\r | |
493 | /// Used by software to cancel command processing Reads return correct value\r | |
494 | /// Writes (0000 0001h): Cancel a command\r | |
495 | /// Writes (0000 0000h): Clears field when command has been cancelled\r | |
496 | ///\r | |
497 | #define PTP_CRB_CONTROL_CANCEL BIT0\r | |
498 | \r | |
499 | //\r | |
500 | // Define bits of CRB Control Start Register\r | |
501 | //\r | |
502 | \r | |
503 | ///\r | |
504 | /// When set by software, indicates a command is ready for processing.\r | |
505 | /// Writes (0000 0001h): TPM transitions to Command Execution\r | |
506 | /// Writes (0000 0000h): TPM clears this field and transitions to Command Completion\r | |
507 | ///\r | |
508 | #define PTP_CRB_CONTROL_START BIT0\r | |
509 | \r | |
510 | //\r | |
511 | // Restore original structure alignment\r | |
512 | //\r | |
513 | #pragma pack ()\r | |
514 | \r | |
515 | //\r | |
516 | // Default TimeOut value\r | |
517 | //\r | |
518 | #define PTP_TIMEOUT_A (750 * 1000) // 750ms\r | |
519 | #define PTP_TIMEOUT_B (2000 * 1000) // 2s\r | |
520 | #define PTP_TIMEOUT_C (200 * 1000) // 200ms\r | |
521 | #define PTP_TIMEOUT_D (30 * 1000) // 30ms\r | |
522 | \r | |
9095d37b | 523 | #endif\r |