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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides CPU architecture specific functions that can not be defined\r |
3 | in the Base Library due to dependencies on the PAL Library\r | |
9095d37b | 4 | \r |
d80b2f71 | 5 | The CPU Library provides services to flush CPU TLBs and place the CPU in a sleep state.\r |
1a2f870c | 6 | The implementation of these services on Itanium processors requires the use of PAL Calls.\r |
d80b2f71 | 7 | PAL Calls require PEI and DXE specific mechanisms to look up PAL Entry Point.\r |
8 | As a result, these services could not be defined in the Base Library.\r | |
fb3df220 | 9 | \r |
9095d37b | 10 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 11 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
fb3df220 | 12 | \r |
fb3df220 | 13 | **/\r |
14 | \r | |
15 | #ifndef __CPU_LIB_H__\r | |
16 | #define __CPU_LIB_H__\r | |
17 | \r | |
7270fe87 | 18 | /**\r |
19 | Places the CPU in a sleep state until an interrupt is received.\r | |
20 | \r | |
21 | Places the CPU in a sleep state until an interrupt is received. If interrupts\r | |
22 | are disabled prior to calling this function, then the CPU will be placed in a\r | |
23 | sleep state indefinitely.\r | |
24 | \r | |
25 | **/\r | |
26 | VOID\r | |
27 | EFIAPI\r | |
28 | CpuSleep (\r | |
29 | VOID\r | |
30 | );\r | |
31 | \r | |
32 | /**\r | |
33 | Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r | |
34 | \r | |
35 | Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r | |
36 | \r | |
37 | **/\r | |
38 | VOID\r | |
39 | EFIAPI\r | |
40 | CpuFlushTlb (\r | |
41 | VOID\r | |
42 | );\r | |
43 | \r | |
58867095 | 44 | \r |
8336fd87 | 45 | #endif\r |