--- /dev/null
+/** @file\r
+ Public include file for the Port IO/MMIO/MSR RegisterFilterLib.\r
+\r
+Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+\r
+SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#ifndef REGISTER_FILTER_LIB_H_\r
+#define REGISTER_FILTER_LIB_H_\r
+\r
+typedef enum {\r
+ FilterWidth8,\r
+ FilterWidth16,\r
+ FilterWidth32,\r
+ FilterWidth64\r
+} FILTER_IO_WIDTH;\r
+\r
+/**\r
+ Filter IO read operation before read IO port.\r
+ It is used to filter IO read operation.\r
+\r
+ It will return the flag to decide whether require read real IO port.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Buffer The destination buffer to store the results.\r
+\r
+ @retval TRUE Need to excute the IO read.\r
+ @retval FALSE Skip the IO read.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Trace IO read operation after read IO port.\r
+ It is used to trace IO operation.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Buffer The destination buffer to store the results.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ );\r
+/**\r
+ Filter IO Write operation before wirte IO port.\r
+ It is used to filter IO operation.\r
+\r
+ It will return the flag to decide whether require read write IO port.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Buffer The source buffer from which to BeforeWrite data.\r
+\r
+ @retval TRUE Need to excute the IO write.\r
+ @retval FALSE Skip the IO write.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+ /**\r
+ Trace IO Write operation after wirte IO port.\r
+ It is used to trace IO operation.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Buffer The source buffer from which to BeforeWrite data.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Filter memory IO before Read operation.\r
+\r
+ It will return the flag to decide whether require read real MMIO.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in] Buffer The destination buffer to store the results.\r
+\r
+ @retval TRUE Need to excute the MMIO read.\r
+ @retval FALSE Skip the MMIO read.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMmIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN OUT VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Tracer memory IO after read operation\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in] Buffer The destination buffer to store the results.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMmIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Filter memory IO before write operation\r
+\r
+ It will return the flag to decide whether require wirte real MMIO.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in] Buffer The source buffer from which to BeforeWrite data.\r
+\r
+ @retval TRUE Need to excute the MMIO write.\r
+ @retval FALSE Skip the MMIO write.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMmIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Tracer memory IO after write operation\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in] Buffer The source buffer from which to BeforeWrite data.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMmIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ );\r
+\r
+/**\r
+ Filter MSR before read operation.\r
+\r
+ It will return the flag to decide whether require read real MSR.\r
+ It can be used for emulation environment.\r
+\r
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.\r
+ @param Value The 64-bit value to BeforeRead from the Machine Specific Register.\r
+\r
+ @retval TRUE Need to excute the MSR read.\r
+ @retval FALSE Skip the MSR read.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMsrRead (\r
+ IN UINT32 Index,\r
+ IN OUT UINT64 *Value\r
+ );\r
+\r
+/**\r
+ Trace MSR after read operation\r
+\r
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.\r
+ @param Value The 64-bit value to BeforeRead from the Machine Specific Register.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMsrRead (\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
+ );\r
+\r
+/**\r
+ Filter MSR before write operation\r
+\r
+ It will return the flag to decide whether require write real MSR.\r
+ It can be used for emulation environment.\r
+\r
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.\r
+ @param Value The 64-bit value to BeforeWrite to the Machine Specific Register.\r
+\r
+ @retval TRUE Need to excute the MSR write.\r
+ @retval FALSE Skip the MSR write.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMsrWrite (\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
+ );\r
+\r
+/**\r
+ Trace MSR after write operation\r
+\r
+ @param Index The 8-bit Machine Specific Register index to BeforeWrite.\r
+ @param Value The 64-bit value to BeforeWrite to the Machine Specific Register.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMsrWrite (\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
+ );\r
+\r
+#endif // REGISTER_FILTER_LIB_H_\r
--- /dev/null
+/** @file\r
+ Null instance of RegisterFilterLib.\r
+\r
+ Copyright (c) 2021 Intel Corporation. All rights reserved.<BR>\r
+\r
+ SPDX-License-Identifier: BSD-2-Clause-Patent\r
+\r
+**/\r
+\r
+#include <Library/RegisterFilterLib.h>\r
+\r
+/**\r
+ Filter IO read operation before read IO port.\r
+ It is used to filter IO read operation.\r
+\r
+ It will return the flag to decide whether require read real IO port.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in,out] Buffer The destination buffer to store the results.\r
+\r
+ @retval TRUE Need to excute the IO read.\r
+ @retval FALSE Skip the IO read.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Trace IO read operation after read IO port.\r
+ It is used to trace IO operation.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Buffer The destination buffer to store the results.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
+/**\r
+ Filter IO Write operation before wirte IO port.\r
+ It is used to filter IO operation.\r
+\r
+ It will return the flag to decide whether require read write IO port.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Buffer The source buffer from which to write data.\r
+\r
+ @retval TRUE Need to excute the IO write.\r
+ @retval FALSE Skip the IO write.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return TRUE;\r
+}\r
+\r
+ /**\r
+ Trace IO Write operation after wirte IO port.\r
+ It is used to trace IO operation.\r
+\r
+ @param[in] Width Signifies the width of the I/O operation.\r
+ @param[in] Address The base address of the I/O operation.\r
+ @param[in] Buffer The source buffer from which to Write data.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
+/**\r
+ Filter memory IO before Read operation.\r
+\r
+ It will return the flag to decide whether require read real MMIO.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in,out] Buffer The destination buffer to store the results.\r
+\r
+ @retval TRUE Need to excute the MMIO read.\r
+ @retval FALSE Skip the MMIO read.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMmIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN OUT VOID *Buffer\r
+ )\r
+{\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Tracer memory IO after read operation.\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in] Buffer The destination buffer to store the results.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMmIoRead (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
+/**\r
+ Filter memory IO before write operation.\r
+\r
+ It will return the flag to decide whether require wirte real MMIO.\r
+ It can be used for emulation environment.\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in] Buffer The source buffer from which to write data.\r
+\r
+ @retval TRUE Need to excute the MMIO write.\r
+ @retval FALSE Skip the MMIO write.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMmIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Tracer memory IO after write operation.\r
+\r
+ @param[in] Width Signifies the width of the memory I/O operation.\r
+ @param[in] Address The base address of the memory I/O operation.\r
+ @param[in] Buffer The source buffer from which to write data.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMmIoWrite (\r
+ IN FILTER_IO_WIDTH Width,\r
+ IN UINTN Address,\r
+ IN VOID *Buffer\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
+/**\r
+ Filter MSR before read operation.\r
+\r
+ It will return the flag to decide whether require read real MSR.\r
+ It can be used for emulation environment.\r
+\r
+ @param Index The Register index of the MSR.\r
+ @param Value Point to the data will be read from the MSR.\r
+\r
+ @retval TRUE Need to excute the MSR read.\r
+ @retval FALSE Skip the MSR read.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMsrRead (\r
+ IN UINT32 Index,\r
+ IN OUT UINT64 *Value\r
+ )\r
+{\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Trace MSR after read operation.\r
+\r
+ @param Index The Register index of the MSR.\r
+ @param Value Point to the data has been be read from the MSR.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMsrRead (\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
+/**\r
+ Filter MSR before write operation.\r
+\r
+ It will return the flag to decide whether require write real MSR.\r
+ It can be used for emulation environment.\r
+\r
+ @param Index The Register index of the MSR.\r
+ @param Value Point to the data want to be written to the MSR.\r
+\r
+ @retval TRUE Need to excute the MSR write.\r
+ @retval FALSE Skip the MSR write.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+FilterBeforeMsrWrite (\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
+ )\r
+{\r
+ return TRUE;\r
+}\r
+\r
+/**\r
+ Trace MSR after write operation.\r
+\r
+ @param Index The Register index of the MSR.\r
+ @param Value Point to the data has been be written to the MSR.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+FilterAfterMsrWrite (\r
+ IN UINT32 Index,\r
+ IN UINT64 *Value\r
+ )\r
+{\r
+ return;\r
+}\r
+\r
--- /dev/null
+## @file\r
+# Null instance of RegisterFilterLib.\r
+#\r
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+#\r
+# SPDX-License-Identifier: BSD-2-Clause-Patent\r
+#\r
+##\r
+\r
+[Defines]\r
+ INF_VERSION = 0x00010005\r
+ BASE_NAME = FilterLibNull\r
+ MODULE_UNI_FILE = FilterLibNull.uni\r
+ FILE_GUID = 9F555194-A410-4AD6-B3FC-53F6E10FA793\r
+ MODULE_TYPE = BASE\r
+ VERSION_STRING = 1.0\r
+ LIBRARY_CLASS = RegisterFilterLib\r
+\r
+[Sources]\r
+ RegisterFilterLibNull.c\r
+\r
+[Packages]\r
+ MdePkg/MdePkg.dec\r
--- /dev/null
+// /** @file\r
+// Null instance of RegisterFilterLib.\r
+//\r
+// Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+// **/\r
+\r
+\r
+#string STR_MODULE_ABSTRACT #language en-US "Null instance of RegisterFilterLib."\r
+#string STR_MODULE_DESCRIPTION #language en-US "Null instance of RegisterFilterLib."\r
+\r
# It also provides the definitions(including PPIs/PROTOCOLs/GUIDs) of\r
# EFI1.10/UEFI2.7/PI1.7 and some Industry Standards.\r
#\r
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# (C) Copyright 2016 - 2021 Hewlett Packard Enterprise Development LP<BR>\r
#\r
#\r
MmUnblockMemoryLib|Include/Library/MmUnblockMemoryLib.h\r
\r
+ ## @libraryclass This library provides interfances to filter and trace port IO/MMIO/MSR access.\r
+ #\r
+ #\r
+ RegisterFilterLib|Include/Library/RegisterFilterLib.h\r
+\r
[LibraryClasses.IA32, LibraryClasses.X64]\r
## @libraryclass Abstracts both S/W SMI generation and detection.\r
##\r
## @file\r
# EFI/PI MdePkg Package\r
#\r
-# Copyright (c) 2007 - 2020, Intel Corporation. All rights reserved.<BR>\r
+# Copyright (c) 2007 - 2021, Intel Corporation. All rights reserved.<BR>\r
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
# (C) Copyright 2020 Hewlett Packard Enterprise Development LP<BR>\r
#\r
MdePkg/Library/StandaloneMmDriverEntryPoint/StandaloneMmDriverEntryPoint.inf\r
MdePkg/Library/StandaloneMmServicesTableLib/StandaloneMmServicesTableLib.inf\r
\r
+ MdePkg/Library/RegisterFilterLibNull/RegisterFilterLibNull.inf\r
+\r
[Components.IA32, Components.X64, Components.ARM, Components.AARCH64]\r
#\r
# Add UEFI Target Based Unit Tests\r