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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space using the I/O ports 0xCF8 and 0xCFC.\r |
badcbfb2 | 3 | \r |
4 | This library is identical to the PCI Library, except the access method for performing PCI \r | |
1a2f870c | 5 | configuration cycles must be through I/O ports 0xCF8 and 0xCFC. This library only allows \r |
badcbfb2 | 6 | access to PCI Segment #0.\r |
fb3df220 | 7 | \r |
94952554 | 8 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r |
9df063a0 | 9 | This program and the accompanying materials\r |
50a64e5b | 10 | are licensed and made available under the terms and conditions of the BSD License\r |
11 | which accompanies this distribution. The full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 13 | \r |
50a64e5b | 14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 16 | \r |
fb3df220 | 17 | **/\r |
18 | \r | |
19 | #ifndef __PCI_CF8_LIB_H__\r | |
20 | #define __PCI_CF8_LIB_H__\r | |
21 | \r | |
22 | \r | |
23 | /**\r | |
24 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
25 | address that can be passed to the PCI Library functions.\r | |
26 | \r | |
27 | Computes an address that is compatible with the PCI Library functions. The\r | |
28 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
29 | the generation of the address.\r | |
30 | \r | |
31 | @param Bus PCI Bus number. Range 0..255.\r | |
32 | @param Device PCI Device number. Range 0..31.\r | |
33 | @param Function PCI Function number. Range 0..7.\r | |
34 | @param Register PCI Register number. Range 0..255.\r | |
35 | \r | |
36 | @return The encode PCI address.\r | |
37 | \r | |
38 | **/\r | |
39 | #define PCI_CF8_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
40 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
41 | \r | |
f926e538 | 42 | /**\r |
d11195a3 | 43 | Registers a PCI device so PCI configuration registers may be accessed after \r |
f926e538 | 44 | SetVirtualAddressMap().\r |
45 | \r | |
d11195a3 | 46 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
47 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
48 | \r | |
f926e538 | 49 | If Address > 0x0FFFFFFF, then ASSERT().\r |
59ceeabe | 50 | If the register specified by Address >= 0x100, then ASSERT().\r |
f926e538 | 51 | \r |
52 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
53 | Register.\r | |
54 | \r | |
55 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
56 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
57 | after ExitBootServices().\r | |
58 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
59 | at runtime could not be mapped.\r | |
60 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
61 | complete the registration.\r | |
62 | \r | |
63 | **/\r | |
64 | RETURN_STATUS\r | |
65 | EFIAPI\r | |
66 | PciCf8RegisterForRuntimeAccess (\r | |
67 | IN UINTN Address\r | |
68 | );\r | |
69 | \r | |
fb3df220 | 70 | /**\r |
71 | Reads an 8-bit PCI configuration register.\r | |
72 | \r | |
73 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
74 | This function must guarantee that all PCI read and write operations are\r | |
75 | serialized.\r | |
76 | \r | |
77 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
78 | If the register specified by Address >= 0x100, then ASSERT().\r | |
79 | \r | |
80 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
81 | Register.\r | |
82 | \r | |
83 | @return The read value from the PCI configuration register.\r | |
84 | \r | |
85 | **/\r | |
86 | UINT8\r | |
87 | EFIAPI\r | |
88 | PciCf8Read8 (\r | |
89 | IN UINTN Address\r | |
90 | );\r | |
91 | \r | |
92 | /**\r | |
93 | Writes an 8-bit PCI configuration register.\r | |
94 | \r | |
95 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
96 | value specified by Value. Value is returned. This function must guarantee\r | |
97 | that all PCI read and write operations are serialized.\r | |
98 | \r | |
99 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
100 | If the register specified by Address >= 0x100, then ASSERT().\r | |
101 | \r | |
102 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
103 | Register.\r | |
104 | @param Value The value to write.\r | |
105 | \r | |
106 | @return The value written to the PCI configuration register.\r | |
107 | \r | |
108 | **/\r | |
109 | UINT8\r | |
110 | EFIAPI\r | |
111 | PciCf8Write8 (\r | |
112 | IN UINTN Address,\r | |
94646ec0 | 113 | IN UINT8 Value\r |
fb3df220 | 114 | );\r |
115 | \r | |
116 | /**\r | |
62991af2 | 117 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
fb3df220 | 118 | an 8-bit value.\r |
119 | \r | |
120 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 121 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 122 | OrData, and writes the result to the 8-bit PCI configuration register\r |
123 | specified by Address. The value written to the PCI configuration register is\r | |
124 | returned. This function must guarantee that all PCI read and write operations\r | |
125 | are serialized.\r | |
126 | \r | |
127 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
128 | If the register specified by Address >= 0x100, then ASSERT().\r | |
129 | \r | |
130 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
131 | Register.\r | |
132 | @param OrData The value to OR with the PCI configuration register.\r | |
133 | \r | |
134 | @return The value written back to the PCI configuration register.\r | |
135 | \r | |
136 | **/\r | |
137 | UINT8\r | |
138 | EFIAPI\r | |
139 | PciCf8Or8 (\r | |
140 | IN UINTN Address,\r | |
141 | IN UINT8 OrData\r | |
142 | );\r | |
143 | \r | |
144 | /**\r | |
145 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
146 | value.\r | |
147 | \r | |
148 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
149 | bitwise AND between the read result and the value specified by AndData, and\r | |
150 | writes the result to the 8-bit PCI configuration register specified by\r | |
151 | Address. The value written to the PCI configuration register is returned.\r | |
152 | This function must guarantee that all PCI read and write operations are\r | |
153 | serialized.\r | |
154 | \r | |
155 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
156 | If the register specified by Address >= 0x100, then ASSERT().\r | |
157 | \r | |
158 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
159 | Register.\r | |
160 | @param AndData The value to AND with the PCI configuration register.\r | |
161 | \r | |
162 | @return The value written back to the PCI configuration register.\r | |
163 | \r | |
164 | **/\r | |
165 | UINT8\r | |
166 | EFIAPI\r | |
167 | PciCf8And8 (\r | |
168 | IN UINTN Address,\r | |
169 | IN UINT8 AndData\r | |
170 | );\r | |
171 | \r | |
172 | /**\r | |
173 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 174 | value, followed a bitwise OR with another 8-bit value.\r |
fb3df220 | 175 | \r |
176 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
177 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 178 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 179 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
180 | configuration register specified by Address. The value written to the PCI\r | |
181 | configuration register is returned. This function must guarantee that all PCI\r | |
182 | read and write operations are serialized.\r | |
183 | \r | |
184 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
185 | If the register specified by Address >= 0x100, then ASSERT().\r | |
186 | \r | |
187 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
188 | Register.\r | |
189 | @param AndData The value to AND with the PCI configuration register.\r | |
190 | @param OrData The value to OR with the result of the AND operation.\r | |
191 | \r | |
192 | @return The value written back to the PCI configuration register.\r | |
193 | \r | |
194 | **/\r | |
195 | UINT8\r | |
196 | EFIAPI\r | |
197 | PciCf8AndThenOr8 (\r | |
198 | IN UINTN Address,\r | |
199 | IN UINT8 AndData,\r | |
200 | IN UINT8 OrData\r | |
201 | );\r | |
202 | \r | |
203 | /**\r | |
204 | Reads a bit field of a PCI configuration register.\r | |
205 | \r | |
206 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
207 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
208 | returned.\r | |
209 | \r | |
210 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
211 | If the register specified by Address >= 0x100, then ASSERT().\r | |
212 | If StartBit is greater than 7, then ASSERT().\r | |
213 | If EndBit is greater than 7, then ASSERT().\r | |
214 | If EndBit is less than StartBit, then ASSERT().\r | |
215 | \r | |
216 | @param Address PCI configuration register to read.\r | |
217 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
218 | Range 0..7.\r | |
219 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
220 | Range 0..7.\r | |
221 | \r | |
222 | @return The value of the bit field read from the PCI configuration register.\r | |
223 | \r | |
224 | **/\r | |
225 | UINT8\r | |
226 | EFIAPI\r | |
227 | PciCf8BitFieldRead8 (\r | |
228 | IN UINTN Address,\r | |
229 | IN UINTN StartBit,\r | |
230 | IN UINTN EndBit\r | |
231 | );\r | |
232 | \r | |
233 | /**\r | |
234 | Writes a bit field to a PCI configuration register.\r | |
235 | \r | |
236 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
237 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
238 | destination PCI configuration register are preserved. The new value of the\r | |
239 | 8-bit register is returned.\r | |
240 | \r | |
241 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
242 | If the register specified by Address >= 0x100, then ASSERT().\r | |
243 | If StartBit is greater than 7, then ASSERT().\r | |
244 | If EndBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 246 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 247 | \r |
248 | @param Address PCI configuration register to write.\r | |
249 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
250 | Range 0..7.\r | |
251 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
252 | Range 0..7.\r | |
253 | @param Value New value of the bit field.\r | |
254 | \r | |
255 | @return The value written back to the PCI configuration register.\r | |
256 | \r | |
257 | **/\r | |
258 | UINT8\r | |
259 | EFIAPI\r | |
260 | PciCf8BitFieldWrite8 (\r | |
261 | IN UINTN Address,\r | |
262 | IN UINTN StartBit,\r | |
263 | IN UINTN EndBit,\r | |
264 | IN UINT8 Value\r | |
265 | );\r | |
266 | \r | |
267 | /**\r | |
268 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
269 | writes the result back to the bit field in the 8-bit port.\r | |
270 | \r | |
271 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 272 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 273 | OrData, and writes the result to the 8-bit PCI configuration register\r |
274 | specified by Address. The value written to the PCI configuration register is\r | |
275 | returned. This function must guarantee that all PCI read and write operations\r | |
276 | are serialized. Extra left bits in OrData are stripped.\r | |
277 | \r | |
278 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
279 | If the register specified by Address >= 0x100, then ASSERT().\r | |
280 | If StartBit is greater than 7, then ASSERT().\r | |
281 | If EndBit is greater than 7, then ASSERT().\r | |
282 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 283 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 284 | \r |
285 | @param Address PCI configuration register to write.\r | |
286 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
287 | Range 0..7.\r | |
288 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
289 | Range 0..7.\r | |
290 | @param OrData The value to OR with the PCI configuration register.\r | |
291 | \r | |
292 | @return The value written back to the PCI configuration register.\r | |
293 | \r | |
294 | **/\r | |
295 | UINT8\r | |
296 | EFIAPI\r | |
297 | PciCf8BitFieldOr8 (\r | |
298 | IN UINTN Address,\r | |
299 | IN UINTN StartBit,\r | |
300 | IN UINTN EndBit,\r | |
301 | IN UINT8 OrData\r | |
302 | );\r | |
303 | \r | |
304 | /**\r | |
305 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
306 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
307 | \r | |
308 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
309 | bitwise AND between the read result and the value specified by AndData, and\r | |
310 | writes the result to the 8-bit PCI configuration register specified by\r | |
311 | Address. The value written to the PCI configuration register is returned.\r | |
312 | This function must guarantee that all PCI read and write operations are\r | |
313 | serialized. Extra left bits in AndData are stripped.\r | |
314 | \r | |
315 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
316 | If the register specified by Address >= 0x100, then ASSERT().\r | |
317 | If StartBit is greater than 7, then ASSERT().\r | |
318 | If EndBit is greater than 7, then ASSERT().\r | |
319 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 320 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 321 | \r |
322 | @param Address PCI configuration register to write.\r | |
323 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
324 | Range 0..7.\r | |
325 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
326 | Range 0..7.\r | |
327 | @param AndData The value to AND with the PCI configuration register.\r | |
328 | \r | |
329 | @return The value written back to the PCI configuration register.\r | |
330 | \r | |
331 | **/\r | |
332 | UINT8\r | |
333 | EFIAPI\r | |
334 | PciCf8BitFieldAnd8 (\r | |
335 | IN UINTN Address,\r | |
336 | IN UINTN StartBit,\r | |
337 | IN UINTN EndBit,\r | |
338 | IN UINT8 AndData\r | |
339 | );\r | |
340 | \r | |
341 | /**\r | |
342 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 343 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 344 | 8-bit port.\r |
345 | \r | |
346 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 347 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 348 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
349 | configuration register specified by Address. The value written to the PCI\r | |
350 | configuration register is returned. This function must guarantee that all PCI\r | |
351 | read and write operations are serialized. Extra left bits in both AndData and\r | |
352 | OrData are stripped.\r | |
353 | \r | |
354 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
355 | If the register specified by Address >= 0x100, then ASSERT().\r | |
356 | If StartBit is greater than 7, then ASSERT().\r | |
357 | If EndBit is greater than 7, then ASSERT().\r | |
358 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
359 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
360 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 361 | \r |
362 | @param Address PCI configuration register to write.\r | |
363 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
364 | Range 0..7.\r | |
365 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
366 | Range 0..7.\r | |
367 | @param AndData The value to AND with the PCI configuration register.\r | |
368 | @param OrData The value to OR with the result of the AND operation.\r | |
369 | \r | |
370 | @return The value written back to the PCI configuration register.\r | |
371 | \r | |
372 | **/\r | |
373 | UINT8\r | |
374 | EFIAPI\r | |
375 | PciCf8BitFieldAndThenOr8 (\r | |
376 | IN UINTN Address,\r | |
377 | IN UINTN StartBit,\r | |
378 | IN UINTN EndBit,\r | |
379 | IN UINT8 AndData,\r | |
380 | IN UINT8 OrData\r | |
381 | );\r | |
382 | \r | |
383 | /**\r | |
384 | Reads a 16-bit PCI configuration register.\r | |
385 | \r | |
386 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
387 | This function must guarantee that all PCI read and write operations are\r | |
388 | serialized.\r | |
389 | \r | |
390 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
391 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
392 | If the register specified by Address >= 0x100, then ASSERT().\r | |
393 | \r | |
394 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
395 | Register.\r | |
396 | \r | |
397 | @return The read value from the PCI configuration register.\r | |
398 | \r | |
399 | **/\r | |
400 | UINT16\r | |
401 | EFIAPI\r | |
402 | PciCf8Read16 (\r | |
403 | IN UINTN Address\r | |
404 | );\r | |
405 | \r | |
406 | /**\r | |
407 | Writes a 16-bit PCI configuration register.\r | |
408 | \r | |
409 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
410 | value specified by Value. Value is returned. This function must guarantee\r | |
411 | that all PCI read and write operations are serialized.\r | |
412 | \r | |
413 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
414 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
415 | If the register specified by Address >= 0x100, then ASSERT().\r | |
416 | \r | |
417 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
418 | Register.\r | |
419 | @param Value The value to write.\r | |
420 | \r | |
421 | @return The value written to the PCI configuration register.\r | |
422 | \r | |
423 | **/\r | |
424 | UINT16\r | |
425 | EFIAPI\r | |
426 | PciCf8Write16 (\r | |
427 | IN UINTN Address,\r | |
94646ec0 | 428 | IN UINT16 Value\r |
fb3df220 | 429 | );\r |
430 | \r | |
431 | /**\r | |
62991af2 | 432 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
fb3df220 | 433 | a 16-bit value.\r |
434 | \r | |
435 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 436 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 437 | OrData, and writes the result to the 16-bit PCI configuration register\r |
438 | specified by Address. The value written to the PCI configuration register is\r | |
439 | returned. This function must guarantee that all PCI read and write operations\r | |
440 | are serialized.\r | |
441 | \r | |
442 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
443 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
444 | If the register specified by Address >= 0x100, then ASSERT().\r | |
445 | \r | |
446 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
447 | Register.\r | |
448 | @param OrData The value to OR with the PCI configuration register.\r | |
449 | \r | |
450 | @return The value written back to the PCI configuration register.\r | |
451 | \r | |
452 | **/\r | |
453 | UINT16\r | |
454 | EFIAPI\r | |
455 | PciCf8Or16 (\r | |
456 | IN UINTN Address,\r | |
457 | IN UINT16 OrData\r | |
458 | );\r | |
459 | \r | |
460 | /**\r | |
461 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
462 | value.\r | |
463 | \r | |
464 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
465 | bitwise AND between the read result and the value specified by AndData, and\r | |
466 | writes the result to the 16-bit PCI configuration register specified by\r | |
467 | Address. The value written to the PCI configuration register is returned.\r | |
468 | This function must guarantee that all PCI read and write operations are\r | |
469 | serialized.\r | |
470 | \r | |
471 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
472 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
473 | If the register specified by Address >= 0x100, then ASSERT().\r | |
474 | \r | |
475 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
476 | Register.\r | |
477 | @param AndData The value to AND with the PCI configuration register.\r | |
478 | \r | |
479 | @return The value written back to the PCI configuration register.\r | |
480 | \r | |
481 | **/\r | |
482 | UINT16\r | |
483 | EFIAPI\r | |
484 | PciCf8And16 (\r | |
485 | IN UINTN Address,\r | |
486 | IN UINT16 AndData\r | |
487 | );\r | |
488 | \r | |
489 | /**\r | |
490 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 491 | value, followed a bitwise OR with another 16-bit value.\r |
fb3df220 | 492 | \r |
493 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
494 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 495 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 496 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
497 | configuration register specified by Address. The value written to the PCI\r | |
498 | configuration register is returned. This function must guarantee that all PCI\r | |
499 | read and write operations are serialized.\r | |
500 | \r | |
501 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
502 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
503 | If the register specified by Address >= 0x100, then ASSERT().\r | |
504 | \r | |
505 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
506 | Register.\r | |
507 | @param AndData The value to AND with the PCI configuration register.\r | |
508 | @param OrData The value to OR with the result of the AND operation.\r | |
509 | \r | |
510 | @return The value written back to the PCI configuration register.\r | |
511 | \r | |
512 | **/\r | |
513 | UINT16\r | |
514 | EFIAPI\r | |
515 | PciCf8AndThenOr16 (\r | |
516 | IN UINTN Address,\r | |
517 | IN UINT16 AndData,\r | |
518 | IN UINT16 OrData\r | |
519 | );\r | |
520 | \r | |
521 | /**\r | |
522 | Reads a bit field of a PCI configuration register.\r | |
523 | \r | |
524 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
525 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
526 | returned.\r | |
527 | \r | |
528 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
529 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
530 | If the register specified by Address >= 0x100, then ASSERT().\r | |
531 | If StartBit is greater than 15, then ASSERT().\r | |
532 | If EndBit is greater than 15, then ASSERT().\r | |
533 | If EndBit is less than StartBit, then ASSERT().\r | |
534 | \r | |
535 | @param Address PCI configuration register to read.\r | |
536 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
537 | Range 0..15.\r | |
538 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
539 | Range 0..15.\r | |
540 | \r | |
541 | @return The value of the bit field read from the PCI configuration register.\r | |
542 | \r | |
543 | **/\r | |
544 | UINT16\r | |
545 | EFIAPI\r | |
546 | PciCf8BitFieldRead16 (\r | |
547 | IN UINTN Address,\r | |
548 | IN UINTN StartBit,\r | |
549 | IN UINTN EndBit\r | |
550 | );\r | |
551 | \r | |
552 | /**\r | |
553 | Writes a bit field to a PCI configuration register.\r | |
554 | \r | |
555 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
556 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
557 | destination PCI configuration register are preserved. The new value of the\r | |
558 | 16-bit register is returned.\r | |
559 | \r | |
560 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
561 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
562 | If the register specified by Address >= 0x100, then ASSERT().\r | |
563 | If StartBit is greater than 15, then ASSERT().\r | |
564 | If EndBit is greater than 15, then ASSERT().\r | |
565 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 566 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 567 | \r |
568 | @param Address PCI configuration register to write.\r | |
569 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
570 | Range 0..15.\r | |
571 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
572 | Range 0..15.\r | |
573 | @param Value New value of the bit field.\r | |
574 | \r | |
575 | @return The value written back to the PCI configuration register.\r | |
576 | \r | |
577 | **/\r | |
578 | UINT16\r | |
579 | EFIAPI\r | |
580 | PciCf8BitFieldWrite16 (\r | |
581 | IN UINTN Address,\r | |
582 | IN UINTN StartBit,\r | |
583 | IN UINTN EndBit,\r | |
584 | IN UINT16 Value\r | |
585 | );\r | |
586 | \r | |
587 | /**\r | |
588 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
589 | writes the result back to the bit field in the 16-bit port.\r | |
590 | \r | |
591 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 592 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 593 | OrData, and writes the result to the 16-bit PCI configuration register\r |
594 | specified by Address. The value written to the PCI configuration register is\r | |
595 | returned. This function must guarantee that all PCI read and write operations\r | |
596 | are serialized. Extra left bits in OrData are stripped.\r | |
597 | \r | |
598 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
599 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
600 | If the register specified by Address >= 0x100, then ASSERT().\r | |
601 | If StartBit is greater than 15, then ASSERT().\r | |
602 | If EndBit is greater than 15, then ASSERT().\r | |
603 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 604 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 605 | \r |
606 | @param Address PCI configuration register to write.\r | |
607 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
608 | Range 0..15.\r | |
609 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
610 | Range 0..15.\r | |
611 | @param OrData The value to OR with the PCI configuration register.\r | |
612 | \r | |
613 | @return The value written back to the PCI configuration register.\r | |
614 | \r | |
615 | **/\r | |
616 | UINT16\r | |
617 | EFIAPI\r | |
618 | PciCf8BitFieldOr16 (\r | |
619 | IN UINTN Address,\r | |
620 | IN UINTN StartBit,\r | |
621 | IN UINTN EndBit,\r | |
622 | IN UINT16 OrData\r | |
623 | );\r | |
624 | \r | |
625 | /**\r | |
626 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
627 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
628 | \r | |
629 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
630 | bitwise AND between the read result and the value specified by AndData, and\r | |
631 | writes the result to the 16-bit PCI configuration register specified by\r | |
632 | Address. The value written to the PCI configuration register is returned.\r | |
633 | This function must guarantee that all PCI read and write operations are\r | |
634 | serialized. Extra left bits in AndData are stripped.\r | |
635 | \r | |
636 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
637 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
638 | If the register specified by Address >= 0x100, then ASSERT().\r | |
639 | If StartBit is greater than 15, then ASSERT().\r | |
640 | If EndBit is greater than 15, then ASSERT().\r | |
641 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 642 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 643 | \r |
644 | @param Address PCI configuration register to write.\r | |
645 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
646 | Range 0..15.\r | |
647 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
648 | Range 0..15.\r | |
649 | @param AndData The value to AND with the PCI configuration register.\r | |
650 | \r | |
651 | @return The value written back to the PCI configuration register.\r | |
652 | \r | |
653 | **/\r | |
654 | UINT16\r | |
655 | EFIAPI\r | |
656 | PciCf8BitFieldAnd16 (\r | |
657 | IN UINTN Address,\r | |
658 | IN UINTN StartBit,\r | |
659 | IN UINTN EndBit,\r | |
660 | IN UINT16 AndData\r | |
661 | );\r | |
662 | \r | |
663 | /**\r | |
664 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 665 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 666 | 16-bit port.\r |
667 | \r | |
668 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 669 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 670 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
671 | configuration register specified by Address. The value written to the PCI\r | |
672 | configuration register is returned. This function must guarantee that all PCI\r | |
673 | read and write operations are serialized. Extra left bits in both AndData and\r | |
674 | OrData are stripped.\r | |
675 | \r | |
676 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
677 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
678 | If the register specified by Address >= 0x100, then ASSERT().\r | |
679 | If StartBit is greater than 15, then ASSERT().\r | |
680 | If EndBit is greater than 15, then ASSERT().\r | |
681 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
682 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
683 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 684 | \r |
685 | @param Address PCI configuration register to write.\r | |
686 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
687 | Range 0..15.\r | |
688 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
689 | Range 0..15.\r | |
690 | @param AndData The value to AND with the PCI configuration register.\r | |
691 | @param OrData The value to OR with the result of the AND operation.\r | |
692 | \r | |
693 | @return The value written back to the PCI configuration register.\r | |
694 | \r | |
695 | **/\r | |
696 | UINT16\r | |
697 | EFIAPI\r | |
698 | PciCf8BitFieldAndThenOr16 (\r | |
699 | IN UINTN Address,\r | |
700 | IN UINTN StartBit,\r | |
701 | IN UINTN EndBit,\r | |
702 | IN UINT16 AndData,\r | |
703 | IN UINT16 OrData\r | |
704 | );\r | |
705 | \r | |
706 | /**\r | |
707 | Reads a 32-bit PCI configuration register.\r | |
708 | \r | |
709 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
710 | This function must guarantee that all PCI read and write operations are\r | |
711 | serialized.\r | |
712 | \r | |
713 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
714 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
715 | If the register specified by Address >= 0x100, then ASSERT().\r | |
716 | \r | |
717 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
718 | Register.\r | |
719 | \r | |
720 | @return The read value from the PCI configuration register.\r | |
721 | \r | |
722 | **/\r | |
723 | UINT32\r | |
724 | EFIAPI\r | |
725 | PciCf8Read32 (\r | |
726 | IN UINTN Address\r | |
727 | );\r | |
728 | \r | |
729 | /**\r | |
730 | Writes a 32-bit PCI configuration register.\r | |
731 | \r | |
732 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
733 | value specified by Value. Value is returned. This function must guarantee\r | |
734 | that all PCI read and write operations are serialized.\r | |
735 | \r | |
736 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
737 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
738 | If the register specified by Address >= 0x100, then ASSERT().\r | |
739 | \r | |
740 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
741 | Register.\r | |
742 | @param Value The value to write.\r | |
743 | \r | |
744 | @return The value written to the PCI configuration register.\r | |
745 | \r | |
746 | **/\r | |
747 | UINT32\r | |
748 | EFIAPI\r | |
749 | PciCf8Write32 (\r | |
750 | IN UINTN Address,\r | |
94646ec0 | 751 | IN UINT32 Value\r |
fb3df220 | 752 | );\r |
753 | \r | |
754 | /**\r | |
62991af2 | 755 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
fb3df220 | 756 | a 32-bit value.\r |
757 | \r | |
758 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 759 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 760 | OrData, and writes the result to the 32-bit PCI configuration register\r |
761 | specified by Address. The value written to the PCI configuration register is\r | |
762 | returned. This function must guarantee that all PCI read and write operations\r | |
763 | are serialized.\r | |
764 | \r | |
765 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
766 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
767 | If the register specified by Address >= 0x100, then ASSERT().\r | |
768 | \r | |
769 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
770 | Register.\r | |
771 | @param OrData The value to OR with the PCI configuration register.\r | |
772 | \r | |
773 | @return The value written back to the PCI configuration register.\r | |
774 | \r | |
775 | **/\r | |
776 | UINT32\r | |
777 | EFIAPI\r | |
778 | PciCf8Or32 (\r | |
779 | IN UINTN Address,\r | |
780 | IN UINT32 OrData\r | |
781 | );\r | |
782 | \r | |
783 | /**\r | |
784 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
785 | value.\r | |
786 | \r | |
787 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
788 | bitwise AND between the read result and the value specified by AndData, and\r | |
789 | writes the result to the 32-bit PCI configuration register specified by\r | |
790 | Address. The value written to the PCI configuration register is returned.\r | |
791 | This function must guarantee that all PCI read and write operations are\r | |
792 | serialized.\r | |
793 | \r | |
794 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
795 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
796 | If the register specified by Address >= 0x100, then ASSERT().\r | |
797 | \r | |
798 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
799 | Register.\r | |
800 | @param AndData The value to AND with the PCI configuration register.\r | |
801 | \r | |
802 | @return The value written back to the PCI configuration register.\r | |
803 | \r | |
804 | **/\r | |
805 | UINT32\r | |
806 | EFIAPI\r | |
807 | PciCf8And32 (\r | |
808 | IN UINTN Address,\r | |
809 | IN UINT32 AndData\r | |
810 | );\r | |
811 | \r | |
812 | /**\r | |
813 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 814 | value, followed a bitwise OR with another 32-bit value.\r |
fb3df220 | 815 | \r |
816 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
817 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 818 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 819 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
820 | configuration register specified by Address. The value written to the PCI\r | |
821 | configuration register is returned. This function must guarantee that all PCI\r | |
822 | read and write operations are serialized.\r | |
823 | \r | |
824 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
825 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
826 | If the register specified by Address >= 0x100, then ASSERT().\r | |
827 | \r | |
828 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
829 | Register.\r | |
830 | @param AndData The value to AND with the PCI configuration register.\r | |
831 | @param OrData The value to OR with the result of the AND operation.\r | |
832 | \r | |
833 | @return The value written back to the PCI configuration register.\r | |
834 | \r | |
835 | **/\r | |
836 | UINT32\r | |
837 | EFIAPI\r | |
838 | PciCf8AndThenOr32 (\r | |
839 | IN UINTN Address,\r | |
840 | IN UINT32 AndData,\r | |
841 | IN UINT32 OrData\r | |
842 | );\r | |
843 | \r | |
844 | /**\r | |
845 | Reads a bit field of a PCI configuration register.\r | |
846 | \r | |
847 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
848 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
849 | returned.\r | |
850 | \r | |
851 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
852 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
853 | If the register specified by Address >= 0x100, then ASSERT().\r | |
854 | If StartBit is greater than 31, then ASSERT().\r | |
855 | If EndBit is greater than 31, then ASSERT().\r | |
856 | If EndBit is less than StartBit, then ASSERT().\r | |
857 | \r | |
858 | @param Address PCI configuration register to read.\r | |
859 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
860 | Range 0..31.\r | |
861 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
862 | Range 0..31.\r | |
863 | \r | |
864 | @return The value of the bit field read from the PCI configuration register.\r | |
865 | \r | |
866 | **/\r | |
867 | UINT32\r | |
868 | EFIAPI\r | |
869 | PciCf8BitFieldRead32 (\r | |
870 | IN UINTN Address,\r | |
871 | IN UINTN StartBit,\r | |
872 | IN UINTN EndBit\r | |
873 | );\r | |
874 | \r | |
875 | /**\r | |
876 | Writes a bit field to a PCI configuration register.\r | |
877 | \r | |
878 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
879 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
880 | destination PCI configuration register are preserved. The new value of the\r | |
881 | 32-bit register is returned.\r | |
882 | \r | |
883 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
884 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
885 | If the register specified by Address >= 0x100, then ASSERT().\r | |
886 | If StartBit is greater than 31, then ASSERT().\r | |
887 | If EndBit is greater than 31, then ASSERT().\r | |
888 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 889 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 890 | \r |
891 | @param Address PCI configuration register to write.\r | |
892 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
893 | Range 0..31.\r | |
894 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
895 | Range 0..31.\r | |
896 | @param Value New value of the bit field.\r | |
897 | \r | |
898 | @return The value written back to the PCI configuration register.\r | |
899 | \r | |
900 | **/\r | |
901 | UINT32\r | |
902 | EFIAPI\r | |
903 | PciCf8BitFieldWrite32 (\r | |
904 | IN UINTN Address,\r | |
905 | IN UINTN StartBit,\r | |
906 | IN UINTN EndBit,\r | |
907 | IN UINT32 Value\r | |
908 | );\r | |
909 | \r | |
910 | /**\r | |
911 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
912 | writes the result back to the bit field in the 32-bit port.\r | |
913 | \r | |
914 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 915 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 916 | OrData, and writes the result to the 32-bit PCI configuration register\r |
917 | specified by Address. The value written to the PCI configuration register is\r | |
918 | returned. This function must guarantee that all PCI read and write operations\r | |
919 | are serialized. Extra left bits in OrData are stripped.\r | |
920 | \r | |
921 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
922 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
923 | If the register specified by Address >= 0x100, then ASSERT().\r | |
924 | If StartBit is greater than 31, then ASSERT().\r | |
925 | If EndBit is greater than 31, then ASSERT().\r | |
926 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 927 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 928 | \r |
929 | @param Address PCI configuration register to write.\r | |
930 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
931 | Range 0..31.\r | |
932 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
933 | Range 0..31.\r | |
934 | @param OrData The value to OR with the PCI configuration register.\r | |
935 | \r | |
936 | @return The value written back to the PCI configuration register.\r | |
937 | \r | |
938 | **/\r | |
939 | UINT32\r | |
940 | EFIAPI\r | |
941 | PciCf8BitFieldOr32 (\r | |
942 | IN UINTN Address,\r | |
943 | IN UINTN StartBit,\r | |
944 | IN UINTN EndBit,\r | |
945 | IN UINT32 OrData\r | |
946 | );\r | |
947 | \r | |
948 | /**\r | |
949 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
950 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
951 | \r | |
952 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
953 | bitwise AND between the read result and the value specified by AndData, and\r | |
954 | writes the result to the 32-bit PCI configuration register specified by\r | |
955 | Address. The value written to the PCI configuration register is returned.\r | |
956 | This function must guarantee that all PCI read and write operations are\r | |
957 | serialized. Extra left bits in AndData are stripped.\r | |
958 | \r | |
959 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
960 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
961 | If the register specified by Address >= 0x100, then ASSERT().\r | |
962 | If StartBit is greater than 31, then ASSERT().\r | |
963 | If EndBit is greater than 31, then ASSERT().\r | |
964 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 965 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 966 | \r |
967 | @param Address PCI configuration register to write.\r | |
968 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
969 | Range 0..31.\r | |
970 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
971 | Range 0..31.\r | |
972 | @param AndData The value to AND with the PCI configuration register.\r | |
973 | \r | |
974 | @return The value written back to the PCI configuration register.\r | |
975 | \r | |
976 | **/\r | |
977 | UINT32\r | |
978 | EFIAPI\r | |
979 | PciCf8BitFieldAnd32 (\r | |
980 | IN UINTN Address,\r | |
981 | IN UINTN StartBit,\r | |
982 | IN UINTN EndBit,\r | |
983 | IN UINT32 AndData\r | |
984 | );\r | |
985 | \r | |
986 | /**\r | |
987 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 988 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 989 | 32-bit port.\r |
990 | \r | |
991 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 992 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 993 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
994 | configuration register specified by Address. The value written to the PCI\r | |
995 | configuration register is returned. This function must guarantee that all PCI\r | |
996 | read and write operations are serialized. Extra left bits in both AndData and\r | |
997 | OrData are stripped.\r | |
998 | \r | |
999 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1000 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1001 | If the register specified by Address >= 0x100, then ASSERT().\r | |
1002 | If StartBit is greater than 31, then ASSERT().\r | |
1003 | If EndBit is greater than 31, then ASSERT().\r | |
1004 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1005 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1006 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 1007 | \r |
1008 | @param Address PCI configuration register to write.\r | |
1009 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1010 | Range 0..31.\r | |
1011 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1012 | Range 0..31.\r | |
1013 | @param AndData The value to AND with the PCI configuration register.\r | |
1014 | @param OrData The value to OR with the result of the AND operation.\r | |
1015 | \r | |
1016 | @return The value written back to the PCI configuration register.\r | |
1017 | \r | |
1018 | **/\r | |
1019 | UINT32\r | |
1020 | EFIAPI\r | |
1021 | PciCf8BitFieldAndThenOr32 (\r | |
1022 | IN UINTN Address,\r | |
1023 | IN UINTN StartBit,\r | |
1024 | IN UINTN EndBit,\r | |
1025 | IN UINT32 AndData,\r | |
1026 | IN UINT32 OrData\r | |
1027 | );\r | |
1028 | \r | |
1029 | /**\r | |
1030 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1031 | \r | |
1032 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1033 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1034 | configuration registers from a single PCI function to be read. Size is\r | |
1035 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1036 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1037 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1038 | end of the range.\r | |
1039 | \r | |
1040 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1041 | If the register specified by StartAddress >= 0x100, then ASSERT().\r | |
1042 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r | |
1043 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1044 | \r | |
1045 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1046 | Function and Register.\r | |
1047 | @param Size Size in bytes of the transfer.\r | |
1048 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1049 | \r | |
9199040c | 1050 | @return Size read from StartAddress.\r |
fb3df220 | 1051 | \r |
1052 | **/\r | |
1053 | UINTN\r | |
1054 | EFIAPI\r | |
1055 | PciCf8ReadBuffer (\r | |
1056 | IN UINTN StartAddress,\r | |
1057 | IN UINTN Size,\r | |
1058 | OUT VOID *Buffer\r | |
1059 | );\r | |
1060 | \r | |
1061 | /**\r | |
1062 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1063 | configuration space.\r | |
1064 | \r | |
1065 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1066 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1067 | configuration registers from a single PCI function to be written. Size is\r | |
1068 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1069 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1070 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1071 | and the end of the range.\r | |
1072 | \r | |
1073 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1074 | If the register specified by StartAddress >= 0x100, then ASSERT().\r | |
1075 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r | |
1076 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1077 | \r | |
1078 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1079 | Function and Register.\r | |
1080 | @param Size Size in bytes of the transfer.\r | |
1081 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1082 | \r | |
9199040c | 1083 | @return Size written to StartAddress.\r |
fb3df220 | 1084 | \r |
1085 | **/\r | |
1086 | UINTN\r | |
1087 | EFIAPI\r | |
1088 | PciCf8WriteBuffer (\r | |
1089 | IN UINTN StartAddress,\r | |
1090 | IN UINTN Size,\r | |
1091 | IN VOID *Buffer\r | |
1092 | );\r | |
1093 | \r | |
1094 | #endif\r |