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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space using the MMIO PCI Express window.\r |
9095d37b LG |
3 | \r |
4 | This library is identical to the PCI Library, except the access method for performing PCI\r | |
1a2f870c | 5 | configuration cycles must be through the 256 MB PCI Express MMIO window whose base address\r |
badcbfb2 | 6 | is defined by PcdPciExpressBaseAddress.\r |
fb3df220 | 7 | \r |
5f354f6a | 8 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
fb3df220 | 10 | \r |
fb3df220 | 11 | **/\r |
12 | \r | |
13 | #ifndef __PCI_EXPRESS_LIB_H__\r | |
14 | #define __PCI_EXPRESS_LIB_H__\r | |
15 | \r | |
5f354f6a RN |
16 | #include <IndustryStandard/PciExpress21.h>\r |
17 | \r | |
fb3df220 | 18 | /**\r |
19 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
20 | address that can be passed to the PCI Library functions.\r | |
21 | \r | |
22 | Computes an address that is compatible with the PCI Library functions. The\r | |
23 | unused upper bits of Bus, Device, Function and Register are stripped prior to\r | |
24 | the generation of the address.\r | |
25 | \r | |
26 | @param Bus PCI Bus number. Range 0..255.\r | |
27 | @param Device PCI Device number. Range 0..31.\r | |
28 | @param Function PCI Function number. Range 0..7.\r | |
29 | @param Register PCI Register number. Range 0..4095.\r | |
30 | \r | |
31 | @return The encode PCI address.\r | |
32 | \r | |
33 | **/\r | |
c9c27019 | 34 | #define PCI_EXPRESS_LIB_ADDRESS(Bus,Device,Function,Offset) PCI_ECAM_ADDRESS ((Bus), (Device), (Function), (Offset))\r |
fb3df220 | 35 | \r |
f926e538 | 36 | /**\r |
9095d37b | 37 | Registers a PCI device so PCI configuration registers may be accessed after\r |
f926e538 | 38 | SetVirtualAddressMap().\r |
9095d37b LG |
39 | \r |
40 | Registers the PCI device specified by Address so all the PCI configuration\r | |
41 | registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r | |
d11195a3 | 42 | is called.\r |
9095d37b | 43 | \r |
f926e538 | 44 | If Address > 0x0FFFFFFF, then ASSERT().\r |
45 | \r | |
46 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
47 | Register.\r | |
9095d37b | 48 | \r |
f926e538 | 49 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
9095d37b | 50 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
f926e538 | 51 | after ExitBootServices().\r |
52 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
53 | at runtime could not be mapped.\r | |
54 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
55 | complete the registration.\r | |
56 | \r | |
57 | **/\r | |
58 | RETURN_STATUS\r | |
59 | EFIAPI\r | |
60 | PciExpressRegisterForRuntimeAccess (\r | |
61 | IN UINTN Address\r | |
62 | );\r | |
63 | \r | |
fb3df220 | 64 | /**\r |
65 | Reads an 8-bit PCI configuration register.\r | |
66 | \r | |
67 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
68 | This function must guarantee that all PCI read and write operations are\r | |
69 | serialized.\r | |
70 | \r | |
71 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
72 | \r | |
73 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
74 | Register.\r | |
75 | \r | |
76 | @return The read value from the PCI configuration register.\r | |
77 | \r | |
78 | **/\r | |
79 | UINT8\r | |
80 | EFIAPI\r | |
81 | PciExpressRead8 (\r | |
82 | IN UINTN Address\r | |
83 | );\r | |
84 | \r | |
85 | /**\r | |
86 | Writes an 8-bit PCI configuration register.\r | |
87 | \r | |
88 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
89 | value specified by Value. Value is returned. This function must guarantee\r | |
90 | that all PCI read and write operations are serialized.\r | |
91 | \r | |
92 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
93 | \r | |
94 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
95 | Register.\r | |
96 | @param Value The value to write.\r | |
97 | \r | |
98 | @return The value written to the PCI configuration register.\r | |
99 | \r | |
100 | **/\r | |
101 | UINT8\r | |
102 | EFIAPI\r | |
103 | PciExpressWrite8 (\r | |
104 | IN UINTN Address,\r | |
94646ec0 | 105 | IN UINT8 Value\r |
fb3df220 | 106 | );\r |
107 | \r | |
108 | /**\r | |
62991af2 | 109 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
fb3df220 | 110 | an 8-bit value.\r |
111 | \r | |
112 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 113 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 114 | OrData, and writes the result to the 8-bit PCI configuration register\r |
115 | specified by Address. The value written to the PCI configuration register is\r | |
116 | returned. This function must guarantee that all PCI read and write operations\r | |
117 | are serialized.\r | |
118 | \r | |
119 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
120 | \r | |
121 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
122 | Register.\r | |
123 | @param OrData The value to OR with the PCI configuration register.\r | |
124 | \r | |
125 | @return The value written back to the PCI configuration register.\r | |
126 | \r | |
127 | **/\r | |
128 | UINT8\r | |
129 | EFIAPI\r | |
130 | PciExpressOr8 (\r | |
131 | IN UINTN Address,\r | |
132 | IN UINT8 OrData\r | |
133 | );\r | |
134 | \r | |
135 | /**\r | |
136 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
137 | value.\r | |
138 | \r | |
139 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
140 | bitwise AND between the read result and the value specified by AndData, and\r | |
141 | writes the result to the 8-bit PCI configuration register specified by\r | |
142 | Address. The value written to the PCI configuration register is returned.\r | |
143 | This function must guarantee that all PCI read and write operations are\r | |
144 | serialized.\r | |
145 | \r | |
146 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
147 | \r | |
148 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
149 | Register.\r | |
150 | @param AndData The value to AND with the PCI configuration register.\r | |
151 | \r | |
152 | @return The value written back to the PCI configuration register.\r | |
153 | \r | |
154 | **/\r | |
155 | UINT8\r | |
156 | EFIAPI\r | |
157 | PciExpressAnd8 (\r | |
158 | IN UINTN Address,\r | |
159 | IN UINT8 AndData\r | |
160 | );\r | |
161 | \r | |
162 | /**\r | |
163 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 164 | value, followed a bitwise OR with another 8-bit value.\r |
fb3df220 | 165 | \r |
166 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
167 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 168 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 169 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
170 | configuration register specified by Address. The value written to the PCI\r | |
171 | configuration register is returned. This function must guarantee that all PCI\r | |
172 | read and write operations are serialized.\r | |
173 | \r | |
174 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
175 | \r | |
176 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
177 | Register.\r | |
178 | @param AndData The value to AND with the PCI configuration register.\r | |
179 | @param OrData The value to OR with the result of the AND operation.\r | |
180 | \r | |
181 | @return The value written back to the PCI configuration register.\r | |
182 | \r | |
183 | **/\r | |
184 | UINT8\r | |
185 | EFIAPI\r | |
186 | PciExpressAndThenOr8 (\r | |
187 | IN UINTN Address,\r | |
188 | IN UINT8 AndData,\r | |
189 | IN UINT8 OrData\r | |
190 | );\r | |
191 | \r | |
192 | /**\r | |
193 | Reads a bit field of a PCI configuration register.\r | |
194 | \r | |
195 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
196 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
197 | returned.\r | |
198 | \r | |
199 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
200 | If StartBit is greater than 7, then ASSERT().\r | |
201 | If EndBit is greater than 7, then ASSERT().\r | |
202 | If EndBit is less than StartBit, then ASSERT().\r | |
203 | \r | |
204 | @param Address PCI configuration register to read.\r | |
205 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
206 | Range 0..7.\r | |
207 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
208 | Range 0..7.\r | |
209 | \r | |
210 | @return The value of the bit field read from the PCI configuration register.\r | |
211 | \r | |
212 | **/\r | |
213 | UINT8\r | |
214 | EFIAPI\r | |
215 | PciExpressBitFieldRead8 (\r | |
216 | IN UINTN Address,\r | |
217 | IN UINTN StartBit,\r | |
218 | IN UINTN EndBit\r | |
219 | );\r | |
220 | \r | |
221 | /**\r | |
222 | Writes a bit field to a PCI configuration register.\r | |
223 | \r | |
224 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
225 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
226 | destination PCI configuration register are preserved. The new value of the\r | |
227 | 8-bit register is returned.\r | |
228 | \r | |
229 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
230 | If StartBit is greater than 7, then ASSERT().\r | |
231 | If EndBit is greater than 7, then ASSERT().\r | |
232 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 233 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 234 | \r |
235 | @param Address PCI configuration register to write.\r | |
236 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
237 | Range 0..7.\r | |
238 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
239 | Range 0..7.\r | |
240 | @param Value New value of the bit field.\r | |
241 | \r | |
242 | @return The value written back to the PCI configuration register.\r | |
243 | \r | |
244 | **/\r | |
245 | UINT8\r | |
246 | EFIAPI\r | |
247 | PciExpressBitFieldWrite8 (\r | |
248 | IN UINTN Address,\r | |
249 | IN UINTN StartBit,\r | |
250 | IN UINTN EndBit,\r | |
251 | IN UINT8 Value\r | |
252 | );\r | |
253 | \r | |
254 | /**\r | |
255 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
256 | writes the result back to the bit field in the 8-bit port.\r | |
257 | \r | |
258 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 259 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 260 | OrData, and writes the result to the 8-bit PCI configuration register\r |
261 | specified by Address. The value written to the PCI configuration register is\r | |
262 | returned. This function must guarantee that all PCI read and write operations\r | |
263 | are serialized. Extra left bits in OrData are stripped.\r | |
264 | \r | |
265 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
266 | If StartBit is greater than 7, then ASSERT().\r | |
267 | If EndBit is greater than 7, then ASSERT().\r | |
268 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 269 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 270 | \r |
271 | @param Address PCI configuration register to write.\r | |
272 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
273 | Range 0..7.\r | |
274 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
275 | Range 0..7.\r | |
276 | @param OrData The value to OR with the PCI configuration register.\r | |
277 | \r | |
278 | @return The value written back to the PCI configuration register.\r | |
279 | \r | |
280 | **/\r | |
281 | UINT8\r | |
282 | EFIAPI\r | |
283 | PciExpressBitFieldOr8 (\r | |
284 | IN UINTN Address,\r | |
285 | IN UINTN StartBit,\r | |
286 | IN UINTN EndBit,\r | |
287 | IN UINT8 OrData\r | |
288 | );\r | |
289 | \r | |
290 | /**\r | |
291 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
292 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
293 | \r | |
294 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
295 | bitwise AND between the read result and the value specified by AndData, and\r | |
296 | writes the result to the 8-bit PCI configuration register specified by\r | |
297 | Address. The value written to the PCI configuration register is returned.\r | |
298 | This function must guarantee that all PCI read and write operations are\r | |
299 | serialized. Extra left bits in AndData are stripped.\r | |
300 | \r | |
301 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
302 | If StartBit is greater than 7, then ASSERT().\r | |
303 | If EndBit is greater than 7, then ASSERT().\r | |
304 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 305 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 306 | \r |
307 | @param Address PCI configuration register to write.\r | |
308 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
309 | Range 0..7.\r | |
310 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
311 | Range 0..7.\r | |
312 | @param AndData The value to AND with the PCI configuration register.\r | |
313 | \r | |
314 | @return The value written back to the PCI configuration register.\r | |
315 | \r | |
316 | **/\r | |
317 | UINT8\r | |
318 | EFIAPI\r | |
319 | PciExpressBitFieldAnd8 (\r | |
320 | IN UINTN Address,\r | |
321 | IN UINTN StartBit,\r | |
322 | IN UINTN EndBit,\r | |
323 | IN UINT8 AndData\r | |
324 | );\r | |
325 | \r | |
326 | /**\r | |
327 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 328 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 329 | 8-bit port.\r |
330 | \r | |
331 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 332 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 333 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
334 | configuration register specified by Address. The value written to the PCI\r | |
335 | configuration register is returned. This function must guarantee that all PCI\r | |
336 | read and write operations are serialized. Extra left bits in both AndData and\r | |
337 | OrData are stripped.\r | |
338 | \r | |
339 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
340 | If StartBit is greater than 7, then ASSERT().\r | |
341 | If EndBit is greater than 7, then ASSERT().\r | |
342 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
343 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
344 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 345 | \r |
346 | @param Address PCI configuration register to write.\r | |
347 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
348 | Range 0..7.\r | |
349 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
350 | Range 0..7.\r | |
351 | @param AndData The value to AND with the PCI configuration register.\r | |
352 | @param OrData The value to OR with the result of the AND operation.\r | |
353 | \r | |
354 | @return The value written back to the PCI configuration register.\r | |
355 | \r | |
356 | **/\r | |
357 | UINT8\r | |
358 | EFIAPI\r | |
359 | PciExpressBitFieldAndThenOr8 (\r | |
360 | IN UINTN Address,\r | |
361 | IN UINTN StartBit,\r | |
362 | IN UINTN EndBit,\r | |
363 | IN UINT8 AndData,\r | |
364 | IN UINT8 OrData\r | |
365 | );\r | |
366 | \r | |
367 | /**\r | |
368 | Reads a 16-bit PCI configuration register.\r | |
369 | \r | |
370 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
371 | This function must guarantee that all PCI read and write operations are\r | |
372 | serialized.\r | |
373 | \r | |
374 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
375 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
376 | \r | |
377 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
378 | Register.\r | |
379 | \r | |
380 | @return The read value from the PCI configuration register.\r | |
381 | \r | |
382 | **/\r | |
383 | UINT16\r | |
384 | EFIAPI\r | |
385 | PciExpressRead16 (\r | |
386 | IN UINTN Address\r | |
387 | );\r | |
388 | \r | |
389 | /**\r | |
390 | Writes a 16-bit PCI configuration register.\r | |
391 | \r | |
392 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
393 | value specified by Value. Value is returned. This function must guarantee\r | |
394 | that all PCI read and write operations are serialized.\r | |
395 | \r | |
396 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
397 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
398 | \r | |
399 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
400 | Register.\r | |
401 | @param Value The value to write.\r | |
402 | \r | |
403 | @return The value written to the PCI configuration register.\r | |
404 | \r | |
405 | **/\r | |
406 | UINT16\r | |
407 | EFIAPI\r | |
408 | PciExpressWrite16 (\r | |
409 | IN UINTN Address,\r | |
94646ec0 | 410 | IN UINT16 Value\r |
fb3df220 | 411 | );\r |
412 | \r | |
413 | /**\r | |
62991af2 | 414 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
fb3df220 | 415 | a 16-bit value.\r |
416 | \r | |
417 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 418 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 419 | OrData, and writes the result to the 16-bit PCI configuration register\r |
420 | specified by Address. The value written to the PCI configuration register is\r | |
421 | returned. This function must guarantee that all PCI read and write operations\r | |
422 | are serialized.\r | |
423 | \r | |
424 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
425 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
426 | \r | |
427 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
428 | Register.\r | |
429 | @param OrData The value to OR with the PCI configuration register.\r | |
430 | \r | |
431 | @return The value written back to the PCI configuration register.\r | |
432 | \r | |
433 | **/\r | |
434 | UINT16\r | |
435 | EFIAPI\r | |
436 | PciExpressOr16 (\r | |
437 | IN UINTN Address,\r | |
438 | IN UINT16 OrData\r | |
439 | );\r | |
440 | \r | |
441 | /**\r | |
442 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
443 | value.\r | |
444 | \r | |
445 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
446 | bitwise AND between the read result and the value specified by AndData, and\r | |
447 | writes the result to the 16-bit PCI configuration register specified by\r | |
448 | Address. The value written to the PCI configuration register is returned.\r | |
449 | This function must guarantee that all PCI read and write operations are\r | |
450 | serialized.\r | |
451 | \r | |
452 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
453 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
454 | \r | |
455 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
456 | Register.\r | |
457 | @param AndData The value to AND with the PCI configuration register.\r | |
458 | \r | |
459 | @return The value written back to the PCI configuration register.\r | |
460 | \r | |
461 | **/\r | |
462 | UINT16\r | |
463 | EFIAPI\r | |
464 | PciExpressAnd16 (\r | |
465 | IN UINTN Address,\r | |
466 | IN UINT16 AndData\r | |
467 | );\r | |
468 | \r | |
469 | /**\r | |
470 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 471 | value, followed a bitwise OR with another 16-bit value.\r |
fb3df220 | 472 | \r |
473 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
474 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 475 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 476 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
477 | configuration register specified by Address. The value written to the PCI\r | |
478 | configuration register is returned. This function must guarantee that all PCI\r | |
479 | read and write operations are serialized.\r | |
480 | \r | |
481 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
482 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
483 | \r | |
484 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
485 | Register.\r | |
486 | @param AndData The value to AND with the PCI configuration register.\r | |
487 | @param OrData The value to OR with the result of the AND operation.\r | |
488 | \r | |
489 | @return The value written back to the PCI configuration register.\r | |
490 | \r | |
491 | **/\r | |
492 | UINT16\r | |
493 | EFIAPI\r | |
494 | PciExpressAndThenOr16 (\r | |
495 | IN UINTN Address,\r | |
496 | IN UINT16 AndData,\r | |
497 | IN UINT16 OrData\r | |
498 | );\r | |
499 | \r | |
500 | /**\r | |
501 | Reads a bit field of a PCI configuration register.\r | |
502 | \r | |
503 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
504 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
505 | returned.\r | |
506 | \r | |
507 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
508 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
509 | If StartBit is greater than 15, then ASSERT().\r | |
510 | If EndBit is greater than 15, then ASSERT().\r | |
511 | If EndBit is less than StartBit, then ASSERT().\r | |
512 | \r | |
513 | @param Address PCI configuration register to read.\r | |
514 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
515 | Range 0..15.\r | |
516 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
517 | Range 0..15.\r | |
518 | \r | |
519 | @return The value of the bit field read from the PCI configuration register.\r | |
520 | \r | |
521 | **/\r | |
522 | UINT16\r | |
523 | EFIAPI\r | |
524 | PciExpressBitFieldRead16 (\r | |
525 | IN UINTN Address,\r | |
526 | IN UINTN StartBit,\r | |
527 | IN UINTN EndBit\r | |
528 | );\r | |
529 | \r | |
530 | /**\r | |
531 | Writes a bit field to a PCI configuration register.\r | |
532 | \r | |
533 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
534 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
535 | destination PCI configuration register are preserved. The new value of the\r | |
536 | 16-bit register is returned.\r | |
537 | \r | |
538 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
539 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
540 | If StartBit is greater than 15, then ASSERT().\r | |
541 | If EndBit is greater than 15, then ASSERT().\r | |
542 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 543 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 544 | \r |
545 | @param Address PCI configuration register to write.\r | |
546 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
547 | Range 0..15.\r | |
548 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
549 | Range 0..15.\r | |
550 | @param Value New value of the bit field.\r | |
551 | \r | |
552 | @return The value written back to the PCI configuration register.\r | |
553 | \r | |
554 | **/\r | |
555 | UINT16\r | |
556 | EFIAPI\r | |
557 | PciExpressBitFieldWrite16 (\r | |
558 | IN UINTN Address,\r | |
559 | IN UINTN StartBit,\r | |
560 | IN UINTN EndBit,\r | |
561 | IN UINT16 Value\r | |
562 | );\r | |
563 | \r | |
564 | /**\r | |
565 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
566 | writes the result back to the bit field in the 16-bit port.\r | |
567 | \r | |
568 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 569 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 570 | OrData, and writes the result to the 16-bit PCI configuration register\r |
571 | specified by Address. The value written to the PCI configuration register is\r | |
572 | returned. This function must guarantee that all PCI read and write operations\r | |
573 | are serialized. Extra left bits in OrData are stripped.\r | |
574 | \r | |
575 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
576 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
577 | If StartBit is greater than 15, then ASSERT().\r | |
578 | If EndBit is greater than 15, then ASSERT().\r | |
579 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 580 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 581 | \r |
582 | @param Address PCI configuration register to write.\r | |
583 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
584 | Range 0..15.\r | |
585 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
586 | Range 0..15.\r | |
587 | @param OrData The value to OR with the PCI configuration register.\r | |
588 | \r | |
589 | @return The value written back to the PCI configuration register.\r | |
590 | \r | |
591 | **/\r | |
592 | UINT16\r | |
593 | EFIAPI\r | |
594 | PciExpressBitFieldOr16 (\r | |
595 | IN UINTN Address,\r | |
596 | IN UINTN StartBit,\r | |
597 | IN UINTN EndBit,\r | |
598 | IN UINT16 OrData\r | |
599 | );\r | |
600 | \r | |
601 | /**\r | |
602 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
603 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
604 | \r | |
605 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
606 | bitwise AND between the read result and the value specified by AndData, and\r | |
607 | writes the result to the 16-bit PCI configuration register specified by\r | |
608 | Address. The value written to the PCI configuration register is returned.\r | |
609 | This function must guarantee that all PCI read and write operations are\r | |
610 | serialized. Extra left bits in AndData are stripped.\r | |
611 | \r | |
612 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
613 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
614 | If StartBit is greater than 15, then ASSERT().\r | |
615 | If EndBit is greater than 15, then ASSERT().\r | |
616 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 617 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 618 | \r |
619 | @param Address PCI configuration register to write.\r | |
620 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
621 | Range 0..15.\r | |
622 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
623 | Range 0..15.\r | |
624 | @param AndData The value to AND with the PCI configuration register.\r | |
625 | \r | |
626 | @return The value written back to the PCI configuration register.\r | |
627 | \r | |
628 | **/\r | |
629 | UINT16\r | |
630 | EFIAPI\r | |
631 | PciExpressBitFieldAnd16 (\r | |
632 | IN UINTN Address,\r | |
633 | IN UINTN StartBit,\r | |
634 | IN UINTN EndBit,\r | |
635 | IN UINT16 AndData\r | |
636 | );\r | |
637 | \r | |
638 | /**\r | |
639 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 640 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 641 | 16-bit port.\r |
642 | \r | |
643 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 644 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 645 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
646 | configuration register specified by Address. The value written to the PCI\r | |
647 | configuration register is returned. This function must guarantee that all PCI\r | |
648 | read and write operations are serialized. Extra left bits in both AndData and\r | |
649 | OrData are stripped.\r | |
650 | \r | |
651 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
652 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
653 | If StartBit is greater than 15, then ASSERT().\r | |
654 | If EndBit is greater than 15, then ASSERT().\r | |
655 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
656 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
657 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 658 | \r |
659 | @param Address PCI configuration register to write.\r | |
660 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
661 | Range 0..15.\r | |
662 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
663 | Range 0..15.\r | |
664 | @param AndData The value to AND with the PCI configuration register.\r | |
665 | @param OrData The value to OR with the result of the AND operation.\r | |
666 | \r | |
667 | @return The value written back to the PCI configuration register.\r | |
668 | \r | |
669 | **/\r | |
670 | UINT16\r | |
671 | EFIAPI\r | |
672 | PciExpressBitFieldAndThenOr16 (\r | |
673 | IN UINTN Address,\r | |
674 | IN UINTN StartBit,\r | |
675 | IN UINTN EndBit,\r | |
676 | IN UINT16 AndData,\r | |
677 | IN UINT16 OrData\r | |
678 | );\r | |
679 | \r | |
680 | /**\r | |
681 | Reads a 32-bit PCI configuration register.\r | |
682 | \r | |
683 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
684 | This function must guarantee that all PCI read and write operations are\r | |
685 | serialized.\r | |
686 | \r | |
687 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
688 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
689 | \r | |
690 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
691 | Register.\r | |
692 | \r | |
693 | @return The read value from the PCI configuration register.\r | |
694 | \r | |
695 | **/\r | |
696 | UINT32\r | |
697 | EFIAPI\r | |
698 | PciExpressRead32 (\r | |
699 | IN UINTN Address\r | |
700 | );\r | |
701 | \r | |
702 | /**\r | |
703 | Writes a 32-bit PCI configuration register.\r | |
704 | \r | |
705 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
706 | value specified by Value. Value is returned. This function must guarantee\r | |
707 | that all PCI read and write operations are serialized.\r | |
708 | \r | |
709 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
710 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
711 | \r | |
712 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
713 | Register.\r | |
714 | @param Value The value to write.\r | |
715 | \r | |
716 | @return The value written to the PCI configuration register.\r | |
717 | \r | |
718 | **/\r | |
719 | UINT32\r | |
720 | EFIAPI\r | |
721 | PciExpressWrite32 (\r | |
722 | IN UINTN Address,\r | |
94646ec0 | 723 | IN UINT32 Value\r |
fb3df220 | 724 | );\r |
725 | \r | |
726 | /**\r | |
62991af2 | 727 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
fb3df220 | 728 | a 32-bit value.\r |
729 | \r | |
730 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 731 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 732 | OrData, and writes the result to the 32-bit PCI configuration register\r |
733 | specified by Address. The value written to the PCI configuration register is\r | |
734 | returned. This function must guarantee that all PCI read and write operations\r | |
735 | are serialized.\r | |
736 | \r | |
737 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
738 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
739 | \r | |
740 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
741 | Register.\r | |
742 | @param OrData The value to OR with the PCI configuration register.\r | |
743 | \r | |
744 | @return The value written back to the PCI configuration register.\r | |
745 | \r | |
746 | **/\r | |
747 | UINT32\r | |
748 | EFIAPI\r | |
749 | PciExpressOr32 (\r | |
750 | IN UINTN Address,\r | |
751 | IN UINT32 OrData\r | |
752 | );\r | |
753 | \r | |
754 | /**\r | |
755 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
756 | value.\r | |
757 | \r | |
758 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
759 | bitwise AND between the read result and the value specified by AndData, and\r | |
760 | writes the result to the 32-bit PCI configuration register specified by\r | |
761 | Address. The value written to the PCI configuration register is returned.\r | |
762 | This function must guarantee that all PCI read and write operations are\r | |
763 | serialized.\r | |
764 | \r | |
765 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
766 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
767 | \r | |
768 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
769 | Register.\r | |
770 | @param AndData The value to AND with the PCI configuration register.\r | |
771 | \r | |
772 | @return The value written back to the PCI configuration register.\r | |
773 | \r | |
774 | **/\r | |
775 | UINT32\r | |
776 | EFIAPI\r | |
777 | PciExpressAnd32 (\r | |
778 | IN UINTN Address,\r | |
779 | IN UINT32 AndData\r | |
780 | );\r | |
781 | \r | |
782 | /**\r | |
783 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 784 | value, followed a bitwise OR with another 32-bit value.\r |
fb3df220 | 785 | \r |
786 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
787 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 788 | performs a bitwise OR between the result of the AND operation and\r |
fb3df220 | 789 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
790 | configuration register specified by Address. The value written to the PCI\r | |
791 | configuration register is returned. This function must guarantee that all PCI\r | |
792 | read and write operations are serialized.\r | |
793 | \r | |
794 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
795 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
796 | \r | |
797 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
798 | Register.\r | |
799 | @param AndData The value to AND with the PCI configuration register.\r | |
800 | @param OrData The value to OR with the result of the AND operation.\r | |
801 | \r | |
802 | @return The value written back to the PCI configuration register.\r | |
803 | \r | |
804 | **/\r | |
805 | UINT32\r | |
806 | EFIAPI\r | |
807 | PciExpressAndThenOr32 (\r | |
808 | IN UINTN Address,\r | |
809 | IN UINT32 AndData,\r | |
810 | IN UINT32 OrData\r | |
811 | );\r | |
812 | \r | |
813 | /**\r | |
814 | Reads a bit field of a PCI configuration register.\r | |
815 | \r | |
816 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
817 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
818 | returned.\r | |
819 | \r | |
820 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
821 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
822 | If StartBit is greater than 31, then ASSERT().\r | |
823 | If EndBit is greater than 31, then ASSERT().\r | |
824 | If EndBit is less than StartBit, then ASSERT().\r | |
825 | \r | |
826 | @param Address PCI configuration register to read.\r | |
827 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
828 | Range 0..31.\r | |
829 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
830 | Range 0..31.\r | |
831 | \r | |
832 | @return The value of the bit field read from the PCI configuration register.\r | |
833 | \r | |
834 | **/\r | |
835 | UINT32\r | |
836 | EFIAPI\r | |
837 | PciExpressBitFieldRead32 (\r | |
838 | IN UINTN Address,\r | |
839 | IN UINTN StartBit,\r | |
840 | IN UINTN EndBit\r | |
841 | );\r | |
842 | \r | |
843 | /**\r | |
844 | Writes a bit field to a PCI configuration register.\r | |
845 | \r | |
846 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
847 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
848 | destination PCI configuration register are preserved. The new value of the\r | |
849 | 32-bit register is returned.\r | |
850 | \r | |
851 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
852 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
853 | If StartBit is greater than 31, then ASSERT().\r | |
854 | If EndBit is greater than 31, then ASSERT().\r | |
855 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 856 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 857 | \r |
858 | @param Address PCI configuration register to write.\r | |
859 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
860 | Range 0..31.\r | |
861 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
862 | Range 0..31.\r | |
863 | @param Value New value of the bit field.\r | |
864 | \r | |
865 | @return The value written back to the PCI configuration register.\r | |
866 | \r | |
867 | **/\r | |
868 | UINT32\r | |
869 | EFIAPI\r | |
870 | PciExpressBitFieldWrite32 (\r | |
871 | IN UINTN Address,\r | |
872 | IN UINTN StartBit,\r | |
873 | IN UINTN EndBit,\r | |
874 | IN UINT32 Value\r | |
875 | );\r | |
876 | \r | |
877 | /**\r | |
878 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
879 | writes the result back to the bit field in the 32-bit port.\r | |
880 | \r | |
881 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 882 | bitwise OR between the read result and the value specified by\r |
fb3df220 | 883 | OrData, and writes the result to the 32-bit PCI configuration register\r |
884 | specified by Address. The value written to the PCI configuration register is\r | |
885 | returned. This function must guarantee that all PCI read and write operations\r | |
886 | are serialized. Extra left bits in OrData are stripped.\r | |
887 | \r | |
888 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
889 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
890 | If StartBit is greater than 31, then ASSERT().\r | |
891 | If EndBit is greater than 31, then ASSERT().\r | |
892 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 893 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 894 | \r |
895 | @param Address PCI configuration register to write.\r | |
896 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
897 | Range 0..31.\r | |
898 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
899 | Range 0..31.\r | |
900 | @param OrData The value to OR with the PCI configuration register.\r | |
901 | \r | |
902 | @return The value written back to the PCI configuration register.\r | |
903 | \r | |
904 | **/\r | |
905 | UINT32\r | |
906 | EFIAPI\r | |
907 | PciExpressBitFieldOr32 (\r | |
908 | IN UINTN Address,\r | |
909 | IN UINTN StartBit,\r | |
910 | IN UINTN EndBit,\r | |
911 | IN UINT32 OrData\r | |
912 | );\r | |
913 | \r | |
914 | /**\r | |
915 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
916 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
917 | \r | |
918 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
919 | bitwise AND between the read result and the value specified by AndData, and\r | |
920 | writes the result to the 32-bit PCI configuration register specified by\r | |
921 | Address. The value written to the PCI configuration register is returned.\r | |
922 | This function must guarantee that all PCI read and write operations are\r | |
923 | serialized. Extra left bits in AndData are stripped.\r | |
924 | \r | |
925 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
926 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
927 | If StartBit is greater than 31, then ASSERT().\r | |
928 | If EndBit is greater than 31, then ASSERT().\r | |
929 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 930 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
fb3df220 | 931 | \r |
932 | @param Address PCI configuration register to write.\r | |
933 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
934 | Range 0..31.\r | |
935 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
936 | Range 0..31.\r | |
937 | @param AndData The value to AND with the PCI configuration register.\r | |
938 | \r | |
939 | @return The value written back to the PCI configuration register.\r | |
940 | \r | |
941 | **/\r | |
942 | UINT32\r | |
943 | EFIAPI\r | |
944 | PciExpressBitFieldAnd32 (\r | |
945 | IN UINTN Address,\r | |
946 | IN UINTN StartBit,\r | |
947 | IN UINTN EndBit,\r | |
948 | IN UINT32 AndData\r | |
949 | );\r | |
950 | \r | |
951 | /**\r | |
952 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 953 | bitwise OR, and writes the result back to the bit field in the\r |
fb3df220 | 954 | 32-bit port.\r |
955 | \r | |
956 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 957 | bitwise AND followed by a bitwise OR between the read result and\r |
fb3df220 | 958 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
959 | configuration register specified by Address. The value written to the PCI\r | |
960 | configuration register is returned. This function must guarantee that all PCI\r | |
961 | read and write operations are serialized. Extra left bits in both AndData and\r | |
962 | OrData are stripped.\r | |
963 | \r | |
964 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
965 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
966 | If StartBit is greater than 31, then ASSERT().\r | |
967 | If EndBit is greater than 31, then ASSERT().\r | |
968 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
969 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
970 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
fb3df220 | 971 | \r |
972 | @param Address PCI configuration register to write.\r | |
973 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
974 | Range 0..31.\r | |
975 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
976 | Range 0..31.\r | |
977 | @param AndData The value to AND with the PCI configuration register.\r | |
978 | @param OrData The value to OR with the result of the AND operation.\r | |
979 | \r | |
980 | @return The value written back to the PCI configuration register.\r | |
981 | \r | |
982 | **/\r | |
983 | UINT32\r | |
984 | EFIAPI\r | |
985 | PciExpressBitFieldAndThenOr32 (\r | |
986 | IN UINTN Address,\r | |
987 | IN UINTN StartBit,\r | |
988 | IN UINTN EndBit,\r | |
989 | IN UINT32 AndData,\r | |
990 | IN UINT32 OrData\r | |
991 | );\r | |
992 | \r | |
993 | /**\r | |
994 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
995 | \r | |
996 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
997 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
998 | configuration registers from a single PCI function to be read. Size is\r | |
999 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1000 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1001 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1002 | end of the range.\r | |
1003 | \r | |
1004 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1005 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1006 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1007 | \r | |
1008 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1009 | Function and Register.\r | |
1010 | @param Size Size in bytes of the transfer.\r | |
1011 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1012 | \r | |
badcbfb2 | 1013 | @return Size read data from StartAddress.\r |
fb3df220 | 1014 | \r |
1015 | **/\r | |
1016 | UINTN\r | |
1017 | EFIAPI\r | |
1018 | PciExpressReadBuffer (\r | |
1019 | IN UINTN StartAddress,\r | |
1020 | IN UINTN Size,\r | |
1021 | OUT VOID *Buffer\r | |
1022 | );\r | |
1023 | \r | |
1024 | /**\r | |
1025 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1026 | configuration space.\r | |
1027 | \r | |
1028 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1029 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1030 | configuration registers from a single PCI function to be written. Size is\r | |
1031 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1032 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1033 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1034 | and the end of the range.\r | |
1035 | \r | |
1036 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1037 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1038 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1039 | \r | |
1040 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1041 | Function and Register.\r | |
1042 | @param Size Size in bytes of the transfer.\r | |
1043 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1044 | \r | |
9199040c | 1045 | @return Size written to StartAddress.\r |
fb3df220 | 1046 | \r |
1047 | **/\r | |
1048 | UINTN\r | |
1049 | EFIAPI\r | |
1050 | PciExpressWriteBuffer (\r | |
1051 | IN UINTN StartAddress,\r | |
1052 | IN UINTN Size,\r | |
1053 | IN VOID *Buffer\r | |
1054 | );\r | |
1055 | \r | |
1056 | #endif\r |