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fb3df220 | 1 | /** @file\r |
50a64e5b | 2 | Provides services to access PCI Configuration Space.\r |
badcbfb2 | 3 | \r |
4 | These functions perform PCI configuration cycles using the default PCI configuration \r | |
5 | access method. This may use I/O ports 0xCF8 and 0xCFC to perform PCI configuration accesses, \r | |
6 | or it may use MMIO registers relative to the PcdPciExpressBaseAddress, or it may use some \r | |
7 | alternate access method. Modules will typically use the PCI Library for its PCI configuration \r | |
8 | accesses. However, if a module requires a mix of PCI access methods, the PCI CF8 Library or \r | |
9 | PCI Express Library may be used in conjunction with the PCI Library. The functionality of \r | |
10 | these three libraries is identical. The PCI CF8 Library and PCI Express Library simply use \r | |
11 | explicit access methods.\r | |
fb3df220 | 12 | \r |
9638ba6d | 13 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
50a64e5b | 14 | All rights reserved. This program and the accompanying materials\r |
15 | are licensed and made available under the terms and conditions of the BSD License\r | |
16 | which accompanies this distribution. The full text of the license may be found at\r | |
17 | http://opensource.org/licenses/bsd-license.php\r | |
fb3df220 | 18 | \r |
50a64e5b | 19 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
20 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
fb3df220 | 21 | \r |
fb3df220 | 22 | **/\r |
23 | \r | |
24 | #ifndef __PCI_LIB_H__\r | |
25 | #define __PCI_LIB_H__\r | |
26 | \r | |
27 | /**\r | |
28 | Macro that converts PCI Bus, PCI Device, PCI Function and PCI Register to an\r | |
29 | address that can be passed to the PCI Library functions.\r | |
30 | \r | |
31 | @param Bus PCI Bus number. Range 0..255.\r | |
32 | @param Device PCI Device number. Range 0..31.\r | |
33 | @param Function PCI Function number. Range 0..7.\r | |
34 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095\r | |
35 | for PCI Express.\r | |
36 | \r | |
37 | @return The encoded PCI address.\r | |
38 | \r | |
39 | **/\r | |
40 | #define PCI_LIB_ADDRESS(Bus,Device,Function,Offset) \\r | |
41 | (((Offset) & 0xfff) | (((Function) & 0x07) << 12) | (((Device) & 0x1f) << 15) | (((Bus) & 0xff) << 20))\r | |
42 | \r | |
f926e538 | 43 | /**\r |
44 | Register a PCI device so PCI configuration registers may be accessed after \r | |
45 | SetVirtualAddressMap().\r | |
46 | \r | |
47 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
48 | \r | |
49 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
50 | Register.\r | |
51 | \r | |
52 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
53 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
54 | after ExitBootServices().\r | |
55 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
56 | at runtime could not be mapped.\r | |
57 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
58 | complete the registration.\r | |
59 | \r | |
60 | **/\r | |
61 | RETURN_STATUS\r | |
62 | EFIAPI\r | |
63 | PciRegisterForRuntimeAccess (\r | |
64 | IN UINTN Address\r | |
65 | );\r | |
66 | \r | |
fb3df220 | 67 | /**\r |
68 | Reads an 8-bit PCI configuration register.\r | |
69 | \r | |
70 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
71 | This function must guarantee that all PCI read and write operations are\r | |
72 | serialized.\r | |
73 | \r | |
74 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
75 | \r | |
76 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
77 | Register.\r | |
78 | \r | |
79 | @return The read value from the PCI configuration register.\r | |
80 | \r | |
81 | **/\r | |
82 | UINT8\r | |
83 | EFIAPI\r | |
84 | PciRead8 (\r | |
85 | IN UINTN Address\r | |
86 | );\r | |
87 | \r | |
88 | /**\r | |
89 | Writes an 8-bit PCI configuration register.\r | |
90 | \r | |
91 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
92 | value specified by Value. Value is returned. This function must guarantee\r | |
93 | that all PCI read and write operations are serialized.\r | |
94 | \r | |
95 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
96 | \r | |
97 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
98 | Register.\r | |
99 | @param Value The value to write.\r | |
100 | \r | |
101 | @return The value written to the PCI configuration register.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT8\r | |
105 | EFIAPI\r | |
106 | PciWrite8 (\r | |
107 | IN UINTN Address,\r | |
94646ec0 | 108 | IN UINT8 Value\r |
fb3df220 | 109 | );\r |
110 | \r | |
111 | /**\r | |
112 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
113 | an 8-bit value.\r | |
114 | \r | |
115 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
116 | bitwise inclusive OR between the read result and the value specified by\r | |
117 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
118 | specified by Address. The value written to the PCI configuration register is\r | |
119 | returned. This function must guarantee that all PCI read and write operations\r | |
120 | are serialized.\r | |
121 | \r | |
122 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
123 | \r | |
124 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
125 | Register.\r | |
126 | @param OrData The value to OR with the PCI configuration register.\r | |
127 | \r | |
128 | @return The value written back to the PCI configuration register.\r | |
129 | \r | |
130 | **/\r | |
131 | UINT8\r | |
132 | EFIAPI\r | |
133 | PciOr8 (\r | |
134 | IN UINTN Address,\r | |
135 | IN UINT8 OrData\r | |
136 | );\r | |
137 | \r | |
138 | /**\r | |
139 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
140 | value.\r | |
141 | \r | |
142 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
143 | bitwise AND between the read result and the value specified by AndData, and\r | |
144 | writes the result to the 8-bit PCI configuration register specified by\r | |
145 | Address. The value written to the PCI configuration register is returned.\r | |
146 | This function must guarantee that all PCI read and write operations are\r | |
147 | serialized.\r | |
148 | \r | |
149 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
150 | \r | |
151 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
152 | Register.\r | |
153 | @param AndData The value to AND with the PCI configuration register.\r | |
154 | \r | |
155 | @return The value written back to the PCI configuration register.\r | |
156 | \r | |
157 | **/\r | |
158 | UINT8\r | |
159 | EFIAPI\r | |
160 | PciAnd8 (\r | |
161 | IN UINTN Address,\r | |
162 | IN UINT8 AndData\r | |
163 | );\r | |
164 | \r | |
165 | /**\r | |
166 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
167 | value, followed a bitwise inclusive OR with another 8-bit value.\r | |
168 | \r | |
169 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
170 | bitwise AND between the read result and the value specified by AndData,\r | |
171 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
172 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
173 | configuration register specified by Address. The value written to the PCI\r | |
174 | configuration register is returned. This function must guarantee that all PCI\r | |
175 | read and write operations are serialized.\r | |
176 | \r | |
177 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
178 | \r | |
179 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
180 | Register.\r | |
181 | @param AndData The value to AND with the PCI configuration register.\r | |
182 | @param OrData The value to OR with the result of the AND operation.\r | |
183 | \r | |
184 | @return The value written back to the PCI configuration register.\r | |
185 | \r | |
186 | **/\r | |
187 | UINT8\r | |
188 | EFIAPI\r | |
189 | PciAndThenOr8 (\r | |
190 | IN UINTN Address,\r | |
191 | IN UINT8 AndData,\r | |
192 | IN UINT8 OrData\r | |
193 | );\r | |
194 | \r | |
195 | /**\r | |
196 | Reads a bit field of a PCI configuration register.\r | |
197 | \r | |
198 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
199 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
200 | returned.\r | |
201 | \r | |
202 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
203 | If StartBit is greater than 7, then ASSERT().\r | |
204 | If EndBit is greater than 7, then ASSERT().\r | |
205 | If EndBit is less than StartBit, then ASSERT().\r | |
206 | \r | |
207 | @param Address PCI configuration register to read.\r | |
208 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
209 | Range 0..7.\r | |
210 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
211 | Range 0..7.\r | |
212 | \r | |
213 | @return The value of the bit field read from the PCI configuration register.\r | |
214 | \r | |
215 | **/\r | |
216 | UINT8\r | |
217 | EFIAPI\r | |
218 | PciBitFieldRead8 (\r | |
219 | IN UINTN Address,\r | |
220 | IN UINTN StartBit,\r | |
221 | IN UINTN EndBit\r | |
222 | );\r | |
223 | \r | |
224 | /**\r | |
225 | Writes a bit field to a PCI configuration register.\r | |
226 | \r | |
227 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
228 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
229 | destination PCI configuration register are preserved. The new value of the\r | |
230 | 8-bit register is returned.\r | |
231 | \r | |
232 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
233 | If StartBit is greater than 7, then ASSERT().\r | |
234 | If EndBit is greater than 7, then ASSERT().\r | |
235 | If EndBit is less than StartBit, then ASSERT().\r | |
236 | \r | |
237 | @param Address PCI configuration register to write.\r | |
238 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
239 | Range 0..7.\r | |
240 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
241 | Range 0..7.\r | |
242 | @param Value New value of the bit field.\r | |
243 | \r | |
244 | @return The value written back to the PCI configuration register.\r | |
245 | \r | |
246 | **/\r | |
247 | UINT8\r | |
248 | EFIAPI\r | |
249 | PciBitFieldWrite8 (\r | |
250 | IN UINTN Address,\r | |
251 | IN UINTN StartBit,\r | |
252 | IN UINTN EndBit,\r | |
253 | IN UINT8 Value\r | |
254 | );\r | |
255 | \r | |
256 | /**\r | |
257 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
258 | writes the result back to the bit field in the 8-bit port.\r | |
259 | \r | |
260 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
261 | bitwise inclusive OR between the read result and the value specified by\r | |
262 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
263 | specified by Address. The value written to the PCI configuration register is\r | |
264 | returned. This function must guarantee that all PCI read and write operations\r | |
265 | are serialized. Extra left bits in OrData are stripped.\r | |
266 | \r | |
267 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
268 | If StartBit is greater than 7, then ASSERT().\r | |
269 | If EndBit is greater than 7, then ASSERT().\r | |
270 | If EndBit is less than StartBit, then ASSERT().\r | |
271 | \r | |
272 | @param Address PCI configuration register to write.\r | |
273 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
274 | Range 0..7.\r | |
275 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
276 | Range 0..7.\r | |
277 | @param OrData The value to OR with the PCI configuration register.\r | |
278 | \r | |
279 | @return The value written back to the PCI configuration register.\r | |
280 | \r | |
281 | **/\r | |
282 | UINT8\r | |
283 | EFIAPI\r | |
284 | PciBitFieldOr8 (\r | |
285 | IN UINTN Address,\r | |
286 | IN UINTN StartBit,\r | |
287 | IN UINTN EndBit,\r | |
288 | IN UINT8 OrData\r | |
289 | );\r | |
290 | \r | |
291 | /**\r | |
292 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
293 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
294 | \r | |
295 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
296 | bitwise AND between the read result and the value specified by AndData, and\r | |
297 | writes the result to the 8-bit PCI configuration register specified by\r | |
298 | Address. The value written to the PCI configuration register is returned.\r | |
299 | This function must guarantee that all PCI read and write operations are\r | |
300 | serialized. Extra left bits in AndData are stripped.\r | |
301 | \r | |
302 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
303 | If StartBit is greater than 7, then ASSERT().\r | |
304 | If EndBit is greater than 7, then ASSERT().\r | |
305 | If EndBit is less than StartBit, then ASSERT().\r | |
306 | \r | |
307 | @param Address PCI configuration register to write.\r | |
308 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
309 | Range 0..7.\r | |
310 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
311 | Range 0..7.\r | |
312 | @param AndData The value to AND with the PCI configuration register.\r | |
313 | \r | |
314 | @return The value written back to the PCI configuration register.\r | |
315 | \r | |
316 | **/\r | |
317 | UINT8\r | |
318 | EFIAPI\r | |
319 | PciBitFieldAnd8 (\r | |
320 | IN UINTN Address,\r | |
321 | IN UINTN StartBit,\r | |
322 | IN UINTN EndBit,\r | |
323 | IN UINT8 AndData\r | |
324 | );\r | |
325 | \r | |
326 | /**\r | |
327 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
328 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
329 | 8-bit port.\r | |
330 | \r | |
331 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
332 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
333 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
334 | configuration register specified by Address. The value written to the PCI\r | |
335 | configuration register is returned. This function must guarantee that all PCI\r | |
336 | read and write operations are serialized. Extra left bits in both AndData and\r | |
337 | OrData are stripped.\r | |
338 | \r | |
339 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
340 | If StartBit is greater than 7, then ASSERT().\r | |
341 | If EndBit is greater than 7, then ASSERT().\r | |
342 | If EndBit is less than StartBit, then ASSERT().\r | |
343 | \r | |
344 | @param Address PCI configuration register to write.\r | |
345 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
346 | Range 0..7.\r | |
347 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
348 | Range 0..7.\r | |
349 | @param AndData The value to AND with the PCI configuration register.\r | |
350 | @param OrData The value to OR with the result of the AND operation.\r | |
351 | \r | |
352 | @return The value written back to the PCI configuration register.\r | |
353 | \r | |
354 | **/\r | |
355 | UINT8\r | |
356 | EFIAPI\r | |
357 | PciBitFieldAndThenOr8 (\r | |
358 | IN UINTN Address,\r | |
359 | IN UINTN StartBit,\r | |
360 | IN UINTN EndBit,\r | |
361 | IN UINT8 AndData,\r | |
362 | IN UINT8 OrData\r | |
363 | );\r | |
364 | \r | |
365 | /**\r | |
366 | Reads a 16-bit PCI configuration register.\r | |
367 | \r | |
368 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
369 | This function must guarantee that all PCI read and write operations are\r | |
370 | serialized.\r | |
371 | \r | |
372 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
373 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
374 | \r | |
375 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
376 | Register.\r | |
377 | \r | |
378 | @return The read value from the PCI configuration register.\r | |
379 | \r | |
380 | **/\r | |
381 | UINT16\r | |
382 | EFIAPI\r | |
383 | PciRead16 (\r | |
384 | IN UINTN Address\r | |
385 | );\r | |
386 | \r | |
387 | /**\r | |
388 | Writes a 16-bit PCI configuration register.\r | |
389 | \r | |
390 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
391 | value specified by Value. Value is returned. This function must guarantee\r | |
392 | that all PCI read and write operations are serialized.\r | |
393 | \r | |
394 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
395 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
396 | \r | |
397 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
398 | Register.\r | |
399 | @param Value The value to write.\r | |
400 | \r | |
401 | @return The value written to the PCI configuration register.\r | |
402 | \r | |
403 | **/\r | |
404 | UINT16\r | |
405 | EFIAPI\r | |
406 | PciWrite16 (\r | |
407 | IN UINTN Address,\r | |
94646ec0 | 408 | IN UINT16 Value\r |
fb3df220 | 409 | );\r |
410 | \r | |
411 | /**\r | |
412 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
413 | a 16-bit value.\r | |
414 | \r | |
415 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
416 | bitwise inclusive OR between the read result and the value specified by\r | |
417 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
418 | specified by Address. The value written to the PCI configuration register is\r | |
419 | returned. This function must guarantee that all PCI read and write operations\r | |
420 | are serialized.\r | |
421 | \r | |
422 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
423 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
424 | \r | |
425 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
426 | Register.\r | |
427 | @param OrData The value to OR with the PCI configuration register.\r | |
428 | \r | |
429 | @return The value written back to the PCI configuration register.\r | |
430 | \r | |
431 | **/\r | |
432 | UINT16\r | |
433 | EFIAPI\r | |
434 | PciOr16 (\r | |
435 | IN UINTN Address,\r | |
436 | IN UINT16 OrData\r | |
437 | );\r | |
438 | \r | |
439 | /**\r | |
440 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
441 | value.\r | |
442 | \r | |
443 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
444 | bitwise AND between the read result and the value specified by AndData, and\r | |
445 | writes the result to the 16-bit PCI configuration register specified by\r | |
446 | Address. The value written to the PCI configuration register is returned.\r | |
447 | This function must guarantee that all PCI read and write operations are\r | |
448 | serialized.\r | |
449 | \r | |
450 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
451 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
452 | \r | |
453 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
454 | Register.\r | |
455 | @param AndData The value to AND with the PCI configuration register.\r | |
456 | \r | |
457 | @return The value written back to the PCI configuration register.\r | |
458 | \r | |
459 | **/\r | |
460 | UINT16\r | |
461 | EFIAPI\r | |
462 | PciAnd16 (\r | |
463 | IN UINTN Address,\r | |
464 | IN UINT16 AndData\r | |
465 | );\r | |
466 | \r | |
467 | /**\r | |
468 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
469 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
470 | \r | |
471 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
472 | bitwise AND between the read result and the value specified by AndData,\r | |
473 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
474 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
475 | configuration register specified by Address. The value written to the PCI\r | |
476 | configuration register is returned. This function must guarantee that all PCI\r | |
477 | read and write operations are serialized.\r | |
478 | \r | |
479 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
480 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
481 | \r | |
482 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
483 | Register.\r | |
484 | @param AndData The value to AND with the PCI configuration register.\r | |
485 | @param OrData The value to OR with the result of the AND operation.\r | |
486 | \r | |
487 | @return The value written back to the PCI configuration register.\r | |
488 | \r | |
489 | **/\r | |
490 | UINT16\r | |
491 | EFIAPI\r | |
492 | PciAndThenOr16 (\r | |
493 | IN UINTN Address,\r | |
494 | IN UINT16 AndData,\r | |
495 | IN UINT16 OrData\r | |
496 | );\r | |
497 | \r | |
498 | /**\r | |
499 | Reads a bit field of a PCI configuration register.\r | |
500 | \r | |
501 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
502 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
503 | returned.\r | |
504 | \r | |
505 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
506 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
507 | If StartBit is greater than 15, then ASSERT().\r | |
508 | If EndBit is greater than 15, then ASSERT().\r | |
509 | If EndBit is less than StartBit, then ASSERT().\r | |
510 | \r | |
511 | @param Address PCI configuration register to read.\r | |
512 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
513 | Range 0..15.\r | |
514 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
515 | Range 0..15.\r | |
516 | \r | |
517 | @return The value of the bit field read from the PCI configuration register.\r | |
518 | \r | |
519 | **/\r | |
520 | UINT16\r | |
521 | EFIAPI\r | |
522 | PciBitFieldRead16 (\r | |
523 | IN UINTN Address,\r | |
524 | IN UINTN StartBit,\r | |
525 | IN UINTN EndBit\r | |
526 | );\r | |
527 | \r | |
528 | /**\r | |
529 | Writes a bit field to a PCI configuration register.\r | |
530 | \r | |
531 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
532 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
533 | destination PCI configuration register are preserved. The new value of the\r | |
534 | 16-bit register is returned.\r | |
535 | \r | |
536 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
537 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
538 | If StartBit is greater than 15, then ASSERT().\r | |
539 | If EndBit is greater than 15, then ASSERT().\r | |
540 | If EndBit is less than StartBit, then ASSERT().\r | |
541 | \r | |
542 | @param Address PCI configuration register to write.\r | |
543 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
544 | Range 0..15.\r | |
545 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
546 | Range 0..15.\r | |
547 | @param Value New value of the bit field.\r | |
548 | \r | |
549 | @return The value written back to the PCI configuration register.\r | |
550 | \r | |
551 | **/\r | |
552 | UINT16\r | |
553 | EFIAPI\r | |
554 | PciBitFieldWrite16 (\r | |
555 | IN UINTN Address,\r | |
556 | IN UINTN StartBit,\r | |
557 | IN UINTN EndBit,\r | |
558 | IN UINT16 Value\r | |
559 | );\r | |
560 | \r | |
561 | /**\r | |
562 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
563 | writes the result back to the bit field in the 16-bit port.\r | |
564 | \r | |
565 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
566 | bitwise inclusive OR between the read result and the value specified by\r | |
567 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
568 | specified by Address. The value written to the PCI configuration register is\r | |
569 | returned. This function must guarantee that all PCI read and write operations\r | |
570 | are serialized. Extra left bits in OrData are stripped.\r | |
571 | \r | |
572 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
573 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
574 | If StartBit is greater than 15, then ASSERT().\r | |
575 | If EndBit is greater than 15, then ASSERT().\r | |
576 | If EndBit is less than StartBit, then ASSERT().\r | |
577 | \r | |
578 | @param Address PCI configuration register to write.\r | |
579 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
580 | Range 0..15.\r | |
581 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
582 | Range 0..15.\r | |
583 | @param OrData The value to OR with the PCI configuration register.\r | |
584 | \r | |
585 | @return The value written back to the PCI configuration register.\r | |
586 | \r | |
587 | **/\r | |
588 | UINT16\r | |
589 | EFIAPI\r | |
590 | PciBitFieldOr16 (\r | |
591 | IN UINTN Address,\r | |
592 | IN UINTN StartBit,\r | |
593 | IN UINTN EndBit,\r | |
594 | IN UINT16 OrData\r | |
595 | );\r | |
596 | \r | |
597 | /**\r | |
598 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
599 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
600 | \r | |
601 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
602 | bitwise AND between the read result and the value specified by AndData, and\r | |
603 | writes the result to the 16-bit PCI configuration register specified by\r | |
604 | Address. The value written to the PCI configuration register is returned.\r | |
605 | This function must guarantee that all PCI read and write operations are\r | |
606 | serialized. Extra left bits in AndData are stripped.\r | |
607 | \r | |
608 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
609 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
610 | If StartBit is greater than 15, then ASSERT().\r | |
611 | If EndBit is greater than 15, then ASSERT().\r | |
612 | If EndBit is less than StartBit, then ASSERT().\r | |
613 | \r | |
614 | @param Address PCI configuration register to write.\r | |
615 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
616 | Range 0..15.\r | |
617 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
618 | Range 0..15.\r | |
619 | @param AndData The value to AND with the PCI configuration register.\r | |
620 | \r | |
621 | @return The value written back to the PCI configuration register.\r | |
622 | \r | |
623 | **/\r | |
624 | UINT16\r | |
625 | EFIAPI\r | |
626 | PciBitFieldAnd16 (\r | |
627 | IN UINTN Address,\r | |
628 | IN UINTN StartBit,\r | |
629 | IN UINTN EndBit,\r | |
630 | IN UINT16 AndData\r | |
631 | );\r | |
632 | \r | |
633 | /**\r | |
634 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
635 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
636 | 16-bit port.\r | |
637 | \r | |
638 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
639 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
640 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
641 | configuration register specified by Address. The value written to the PCI\r | |
642 | configuration register is returned. This function must guarantee that all PCI\r | |
643 | read and write operations are serialized. Extra left bits in both AndData and\r | |
644 | OrData are stripped.\r | |
645 | \r | |
646 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
647 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
648 | If StartBit is greater than 15, then ASSERT().\r | |
649 | If EndBit is greater than 15, then ASSERT().\r | |
650 | If EndBit is less than StartBit, then ASSERT().\r | |
651 | \r | |
652 | @param Address PCI configuration register to write.\r | |
653 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
654 | Range 0..15.\r | |
655 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
656 | Range 0..15.\r | |
657 | @param AndData The value to AND with the PCI configuration register.\r | |
658 | @param OrData The value to OR with the result of the AND operation.\r | |
659 | \r | |
660 | @return The value written back to the PCI configuration register.\r | |
661 | \r | |
662 | **/\r | |
663 | UINT16\r | |
664 | EFIAPI\r | |
665 | PciBitFieldAndThenOr16 (\r | |
666 | IN UINTN Address,\r | |
667 | IN UINTN StartBit,\r | |
668 | IN UINTN EndBit,\r | |
669 | IN UINT16 AndData,\r | |
670 | IN UINT16 OrData\r | |
671 | );\r | |
672 | \r | |
673 | /**\r | |
674 | Reads a 32-bit PCI configuration register.\r | |
675 | \r | |
676 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
677 | This function must guarantee that all PCI read and write operations are\r | |
678 | serialized.\r | |
679 | \r | |
680 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
681 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
682 | \r | |
683 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
684 | Register.\r | |
685 | \r | |
686 | @return The read value from the PCI configuration register.\r | |
687 | \r | |
688 | **/\r | |
689 | UINT32\r | |
690 | EFIAPI\r | |
691 | PciRead32 (\r | |
692 | IN UINTN Address\r | |
693 | );\r | |
694 | \r | |
695 | /**\r | |
696 | Writes a 32-bit PCI configuration register.\r | |
697 | \r | |
698 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
699 | value specified by Value. Value is returned. This function must guarantee\r | |
700 | that all PCI read and write operations are serialized.\r | |
701 | \r | |
702 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
703 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
704 | \r | |
705 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
706 | Register.\r | |
707 | @param Value The value to write.\r | |
708 | \r | |
709 | @return The value written to the PCI configuration register.\r | |
710 | \r | |
711 | **/\r | |
712 | UINT32\r | |
713 | EFIAPI\r | |
714 | PciWrite32 (\r | |
715 | IN UINTN Address,\r | |
94646ec0 | 716 | IN UINT32 Value\r |
fb3df220 | 717 | );\r |
718 | \r | |
719 | /**\r | |
720 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
721 | a 32-bit value.\r | |
722 | \r | |
723 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
724 | bitwise inclusive OR between the read result and the value specified by\r | |
725 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
726 | specified by Address. The value written to the PCI configuration register is\r | |
727 | returned. This function must guarantee that all PCI read and write operations\r | |
728 | are serialized.\r | |
729 | \r | |
730 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
731 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
732 | \r | |
733 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
734 | Register.\r | |
735 | @param OrData The value to OR with the PCI configuration register.\r | |
736 | \r | |
737 | @return The value written back to the PCI configuration register.\r | |
738 | \r | |
739 | **/\r | |
740 | UINT32\r | |
741 | EFIAPI\r | |
742 | PciOr32 (\r | |
743 | IN UINTN Address,\r | |
744 | IN UINT32 OrData\r | |
745 | );\r | |
746 | \r | |
747 | /**\r | |
748 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
749 | value.\r | |
750 | \r | |
751 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
752 | bitwise AND between the read result and the value specified by AndData, and\r | |
753 | writes the result to the 32-bit PCI configuration register specified by\r | |
754 | Address. The value written to the PCI configuration register is returned.\r | |
755 | This function must guarantee that all PCI read and write operations are\r | |
756 | serialized.\r | |
757 | \r | |
758 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
759 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
760 | \r | |
761 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
762 | Register.\r | |
763 | @param AndData The value to AND with the PCI configuration register.\r | |
764 | \r | |
765 | @return The value written back to the PCI configuration register.\r | |
766 | \r | |
767 | **/\r | |
768 | UINT32\r | |
769 | EFIAPI\r | |
770 | PciAnd32 (\r | |
771 | IN UINTN Address,\r | |
772 | IN UINT32 AndData\r | |
773 | );\r | |
774 | \r | |
775 | /**\r | |
776 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
777 | value, followed a bitwise inclusive OR with another 32-bit value.\r | |
778 | \r | |
779 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
780 | bitwise AND between the read result and the value specified by AndData,\r | |
781 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
782 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
783 | configuration register specified by Address. The value written to the PCI\r | |
784 | configuration register is returned. This function must guarantee that all PCI\r | |
785 | read and write operations are serialized.\r | |
786 | \r | |
787 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
788 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
789 | \r | |
790 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
791 | Register.\r | |
792 | @param AndData The value to AND with the PCI configuration register.\r | |
793 | @param OrData The value to OR with the result of the AND operation.\r | |
794 | \r | |
795 | @return The value written back to the PCI configuration register.\r | |
796 | \r | |
797 | **/\r | |
798 | UINT32\r | |
799 | EFIAPI\r | |
800 | PciAndThenOr32 (\r | |
801 | IN UINTN Address,\r | |
802 | IN UINT32 AndData,\r | |
803 | IN UINT32 OrData\r | |
804 | );\r | |
805 | \r | |
806 | /**\r | |
807 | Reads a bit field of a PCI configuration register.\r | |
808 | \r | |
809 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
810 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
811 | returned.\r | |
812 | \r | |
813 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
814 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
815 | If StartBit is greater than 31, then ASSERT().\r | |
816 | If EndBit is greater than 31, then ASSERT().\r | |
817 | If EndBit is less than StartBit, then ASSERT().\r | |
818 | \r | |
819 | @param Address PCI configuration register to read.\r | |
820 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
821 | Range 0..31.\r | |
822 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
823 | Range 0..31.\r | |
824 | \r | |
825 | @return The value of the bit field read from the PCI configuration register.\r | |
826 | \r | |
827 | **/\r | |
828 | UINT32\r | |
829 | EFIAPI\r | |
830 | PciBitFieldRead32 (\r | |
831 | IN UINTN Address,\r | |
832 | IN UINTN StartBit,\r | |
833 | IN UINTN EndBit\r | |
834 | );\r | |
835 | \r | |
836 | /**\r | |
837 | Writes a bit field to a PCI configuration register.\r | |
838 | \r | |
839 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
840 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
841 | destination PCI configuration register are preserved. The new value of the\r | |
842 | 32-bit register is returned.\r | |
843 | \r | |
844 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
845 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
846 | If StartBit is greater than 31, then ASSERT().\r | |
847 | If EndBit is greater than 31, then ASSERT().\r | |
848 | If EndBit is less than StartBit, then ASSERT().\r | |
849 | \r | |
850 | @param Address PCI configuration register to write.\r | |
851 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
852 | Range 0..31.\r | |
853 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
854 | Range 0..31.\r | |
855 | @param Value New value of the bit field.\r | |
856 | \r | |
857 | @return The value written back to the PCI configuration register.\r | |
858 | \r | |
859 | **/\r | |
860 | UINT32\r | |
861 | EFIAPI\r | |
862 | PciBitFieldWrite32 (\r | |
863 | IN UINTN Address,\r | |
864 | IN UINTN StartBit,\r | |
865 | IN UINTN EndBit,\r | |
866 | IN UINT32 Value\r | |
867 | );\r | |
868 | \r | |
869 | /**\r | |
870 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
871 | writes the result back to the bit field in the 32-bit port.\r | |
872 | \r | |
873 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
874 | bitwise inclusive OR between the read result and the value specified by\r | |
875 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
876 | specified by Address. The value written to the PCI configuration register is\r | |
877 | returned. This function must guarantee that all PCI read and write operations\r | |
878 | are serialized. Extra left bits in OrData are stripped.\r | |
879 | \r | |
880 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
881 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
882 | If StartBit is greater than 31, then ASSERT().\r | |
883 | If EndBit is greater than 31, then ASSERT().\r | |
884 | If EndBit is less than StartBit, then ASSERT().\r | |
885 | \r | |
886 | @param Address PCI configuration register to write.\r | |
887 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
888 | Range 0..31.\r | |
889 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
890 | Range 0..31.\r | |
891 | @param OrData The value to OR with the PCI configuration register.\r | |
892 | \r | |
893 | @return The value written back to the PCI configuration register.\r | |
894 | \r | |
895 | **/\r | |
896 | UINT32\r | |
897 | EFIAPI\r | |
898 | PciBitFieldOr32 (\r | |
899 | IN UINTN Address,\r | |
900 | IN UINTN StartBit,\r | |
901 | IN UINTN EndBit,\r | |
902 | IN UINT32 OrData\r | |
903 | );\r | |
904 | \r | |
905 | /**\r | |
906 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
907 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
908 | \r | |
909 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
910 | bitwise AND between the read result and the value specified by AndData, and\r | |
911 | writes the result to the 32-bit PCI configuration register specified by\r | |
912 | Address. The value written to the PCI configuration register is returned.\r | |
913 | This function must guarantee that all PCI read and write operations are\r | |
914 | serialized. Extra left bits in AndData are stripped.\r | |
915 | \r | |
916 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
917 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
918 | If StartBit is greater than 31, then ASSERT().\r | |
919 | If EndBit is greater than 31, then ASSERT().\r | |
920 | If EndBit is less than StartBit, then ASSERT().\r | |
921 | \r | |
922 | @param Address PCI configuration register to write.\r | |
923 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
924 | Range 0..31.\r | |
925 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
926 | Range 0..31.\r | |
927 | @param AndData The value to AND with the PCI configuration register.\r | |
928 | \r | |
929 | @return The value written back to the PCI configuration register.\r | |
930 | \r | |
931 | **/\r | |
932 | UINT32\r | |
933 | EFIAPI\r | |
934 | PciBitFieldAnd32 (\r | |
935 | IN UINTN Address,\r | |
936 | IN UINTN StartBit,\r | |
937 | IN UINTN EndBit,\r | |
938 | IN UINT32 AndData\r | |
939 | );\r | |
940 | \r | |
941 | /**\r | |
942 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
943 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
944 | 32-bit port.\r | |
945 | \r | |
946 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
947 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
948 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
949 | configuration register specified by Address. The value written to the PCI\r | |
950 | configuration register is returned. This function must guarantee that all PCI\r | |
951 | read and write operations are serialized. Extra left bits in both AndData and\r | |
952 | OrData are stripped.\r | |
953 | \r | |
954 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
955 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
956 | If StartBit is greater than 31, then ASSERT().\r | |
957 | If EndBit is greater than 31, then ASSERT().\r | |
958 | If EndBit is less than StartBit, then ASSERT().\r | |
959 | \r | |
960 | @param Address PCI configuration register to write.\r | |
961 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
962 | Range 0..31.\r | |
963 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
964 | Range 0..31.\r | |
965 | @param AndData The value to AND with the PCI configuration register.\r | |
966 | @param OrData The value to OR with the result of the AND operation.\r | |
967 | \r | |
968 | @return The value written back to the PCI configuration register.\r | |
969 | \r | |
970 | **/\r | |
971 | UINT32\r | |
972 | EFIAPI\r | |
973 | PciBitFieldAndThenOr32 (\r | |
974 | IN UINTN Address,\r | |
975 | IN UINTN StartBit,\r | |
976 | IN UINTN EndBit,\r | |
977 | IN UINT32 AndData,\r | |
978 | IN UINT32 OrData\r | |
979 | );\r | |
980 | \r | |
981 | /**\r | |
982 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
983 | \r | |
984 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
985 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
986 | configuration registers from a single PCI function to be read. Size is\r | |
987 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
988 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
989 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
990 | end of the range.\r | |
991 | \r | |
992 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
993 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
994 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
995 | \r | |
996 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
997 | Function and Register.\r | |
998 | @param Size Size in bytes of the transfer.\r | |
999 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1000 | \r | |
1001 | @return Size\r | |
1002 | \r | |
1003 | **/\r | |
1004 | UINTN\r | |
1005 | EFIAPI\r | |
1006 | PciReadBuffer (\r | |
1007 | IN UINTN StartAddress,\r | |
1008 | IN UINTN Size,\r | |
1009 | OUT VOID *Buffer\r | |
1010 | );\r | |
1011 | \r | |
1012 | /**\r | |
1013 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1014 | configuration space.\r | |
1015 | \r | |
1016 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1017 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1018 | configuration registers from a single PCI function to be written. Size is\r | |
1019 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1020 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1021 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1022 | and the end of the range.\r | |
1023 | \r | |
1024 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1025 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1026 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1027 | \r | |
1028 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1029 | Function and Register.\r | |
1030 | @param Size Size in bytes of the transfer.\r | |
1031 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1032 | \r | |
9199040c | 1033 | @return Size written to StartAddress.\r |
fb3df220 | 1034 | \r |
1035 | **/\r | |
1036 | UINTN\r | |
1037 | EFIAPI\r | |
1038 | PciWriteBuffer (\r | |
1039 | IN UINTN StartAddress,\r | |
1040 | IN UINTN Size,\r | |
1041 | IN VOID *Buffer\r | |
1042 | );\r | |
1043 | \r | |
1044 | #endif\r |