]>
Commit | Line | Data |
---|---|---|
a2285a89 RN |
1 | /** @file\r |
2 | The multiple segments PCI configuration Library Services that carry out\r | |
3 | PCI configuration and enable the PCI operations to be replayed during an\r | |
4 | S3 resume. This library class maps directly on top of the PciSegmentLib class.\r | |
5 | \r | |
6 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
a2285a89 RN |
8 | \r |
9 | **/\r | |
10 | \r | |
11 | #ifndef __S3_PCI_SEGMENT_LIB__\r | |
12 | #define __S3_PCI_SEGMENT_LIB__\r | |
13 | \r | |
14 | \r | |
15 | /**\r | |
16 | Macro that converts PCI Segment, PCI Bus, PCI Device, PCI Function,\r | |
17 | and PCI Register to an address that can be passed to the S3 PCI Segment Library functions.\r | |
18 | \r | |
19 | Computes an address that is compatible with the PCI Segment Library functions.\r | |
20 | The unused upper bits of Segment, Bus, Device, Function,\r | |
21 | and Register are stripped prior to the generation of the address.\r | |
22 | \r | |
23 | @param Segment PCI Segment number. Range 0..65535.\r | |
24 | @param Bus PCI Bus number. Range 0..255.\r | |
25 | @param Device PCI Device number. Range 0..31.\r | |
26 | @param Function PCI Function number. Range 0..7.\r | |
27 | @param Register PCI Register number. Range 0..255 for PCI. Range 0..4095 for PCI Express.\r | |
28 | \r | |
29 | @return The address that is compatible with the PCI Segment Library functions.\r | |
30 | \r | |
31 | **/\r | |
32 | #define S3_PCI_SEGMENT_LIB_ADDRESS(Segment,Bus,Device,Function,Register) \\r | |
33 | ((Segment != 0) ? \\r | |
34 | ( ((Register) & 0xfff) | \\r | |
35 | (((Function) & 0x07) << 12) | \\r | |
36 | (((Device) & 0x1f) << 15) | \\r | |
37 | (((Bus) & 0xff) << 20) | \\r | |
38 | (LShiftU64 ((Segment) & 0xffff, 32)) \\r | |
39 | ) : \\r | |
40 | ( ((Register) & 0xfff) | \\r | |
41 | (((Function) & 0x07) << 12) | \\r | |
42 | (((Device) & 0x1f) << 15) | \\r | |
43 | (((Bus) & 0xff) << 20) \\r | |
44 | ) \\r | |
45 | )\r | |
46 | \r | |
47 | /**\r | |
48 | Reads an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
49 | be replayed on S3 resume.\r | |
50 | \r | |
51 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
52 | This function must guarantee that all PCI read and write operations are serialized.\r | |
53 | \r | |
54 | If any reserved bits in Address are set, then ASSERT().\r | |
55 | \r | |
56 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
57 | \r | |
58 | @return The 8-bit PCI configuration register specified by Address.\r | |
59 | \r | |
60 | **/\r | |
61 | UINT8\r | |
62 | EFIAPI\r | |
63 | S3PciSegmentRead8 (\r | |
64 | IN UINT64 Address\r | |
65 | );\r | |
66 | \r | |
67 | /**\r | |
68 | Writes an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
69 | be replayed on S3 resume.\r | |
70 | \r | |
71 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
72 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
73 | \r | |
74 | If any reserved bits in Address are set, then ASSERT().\r | |
75 | \r | |
76 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
77 | @param Value The value to write.\r | |
78 | \r | |
79 | @return The value written to the PCI configuration register.\r | |
80 | \r | |
81 | **/\r | |
82 | UINT8\r | |
83 | EFIAPI\r | |
84 | S3PciSegmentWrite8 (\r | |
85 | IN UINT64 Address,\r | |
86 | IN UINT8 Value\r | |
87 | );\r | |
88 | \r | |
89 | /**\r | |
90 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves\r | |
91 | the value in the S3 script to be replayed on S3 resume.\r | |
92 | \r | |
93 | Reads the 8-bit PCI configuration register specified by Address,\r | |
94 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
95 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
96 | The value written to the PCI configuration register is returned.\r | |
97 | This function must guarantee that all PCI read and write operations are serialized.\r | |
98 | \r | |
99 | If any reserved bits in Address are set, then ASSERT().\r | |
100 | \r | |
101 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
102 | @param OrData The value to OR with the PCI configuration register.\r | |
103 | \r | |
104 | @return The value written to the PCI configuration register.\r | |
105 | \r | |
106 | **/\r | |
107 | UINT8\r | |
108 | EFIAPI\r | |
109 | S3PciSegmentOr8 (\r | |
110 | IN UINT64 Address,\r | |
111 | IN UINT8 OrData\r | |
112 | );\r | |
113 | \r | |
114 | /**\r | |
115 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and\r | |
116 | saves the value in the S3 script to be replayed on S3 resume.\r | |
117 | \r | |
118 | Reads the 8-bit PCI configuration register specified by Address,\r | |
119 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
120 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
121 | The value written to the PCI configuration register is returned.\r | |
122 | This function must guarantee that all PCI read and write operations are serialized.\r | |
123 | If any reserved bits in Address are set, then ASSERT().\r | |
124 | \r | |
125 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
126 | @param AndData The value to AND with the PCI configuration register.\r | |
127 | \r | |
128 | @return The value written to the PCI configuration register.\r | |
129 | \r | |
130 | **/\r | |
131 | UINT8\r | |
132 | EFIAPI\r | |
133 | S3PciSegmentAnd8 (\r | |
134 | IN UINT64 Address,\r | |
135 | IN UINT8 AndData\r | |
136 | );\r | |
137 | \r | |
138 | /**\r | |
139 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
140 | followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to\r | |
141 | be replayed on S3 resume.\r | |
142 | \r | |
143 | Reads the 8-bit PCI configuration register specified by Address,\r | |
144 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
145 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
146 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
147 | The value written to the PCI configuration register is returned.\r | |
148 | This function must guarantee that all PCI read and write operations are serialized.\r | |
149 | \r | |
150 | If any reserved bits in Address are set, then ASSERT().\r | |
151 | \r | |
152 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
153 | @param AndData The value to AND with the PCI configuration register.\r | |
154 | @param OrData The value to OR with the PCI configuration register.\r | |
155 | \r | |
156 | @return The value written to the PCI configuration register.\r | |
157 | \r | |
158 | **/\r | |
159 | UINT8\r | |
160 | EFIAPI\r | |
161 | S3PciSegmentAndThenOr8 (\r | |
162 | IN UINT64 Address,\r | |
163 | IN UINT8 AndData,\r | |
164 | IN UINT8 OrData\r | |
165 | );\r | |
166 | \r | |
167 | /**\r | |
168 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
169 | S3 script to be replayed on S3 resume.\r | |
170 | \r | |
171 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
172 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
173 | returned.\r | |
174 | \r | |
175 | If any reserved bits in Address are set, then ASSERT().\r | |
176 | If StartBit is greater than 7, then ASSERT().\r | |
177 | If EndBit is greater than 7, then ASSERT().\r | |
178 | If EndBit is less than StartBit, then ASSERT().\r | |
179 | \r | |
180 | @param Address PCI configuration register to read.\r | |
181 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
182 | Range 0..7.\r | |
183 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
184 | Range 0..7.\r | |
185 | \r | |
186 | @return The value of the bit field read from the PCI configuration register.\r | |
187 | \r | |
188 | **/\r | |
189 | UINT8\r | |
190 | EFIAPI\r | |
191 | S3PciSegmentBitFieldRead8 (\r | |
192 | IN UINT64 Address,\r | |
193 | IN UINTN StartBit,\r | |
194 | IN UINTN EndBit\r | |
195 | );\r | |
196 | \r | |
197 | /**\r | |
198 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
199 | the S3 script to be replayed on S3 resume.\r | |
200 | \r | |
201 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
202 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
203 | destination PCI configuration register are preserved. The new value of the\r | |
204 | 8-bit register is returned.\r | |
205 | \r | |
206 | If any reserved bits in Address are set, then ASSERT().\r | |
207 | If StartBit is greater than 7, then ASSERT().\r | |
208 | If EndBit is greater than 7, then ASSERT().\r | |
209 | If EndBit is less than StartBit, then ASSERT().\r | |
210 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
211 | \r | |
212 | @param Address PCI configuration register to write.\r | |
213 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
214 | Range 0..7.\r | |
215 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
216 | Range 0..7.\r | |
217 | @param Value New value of the bit field.\r | |
218 | \r | |
219 | @return The value written back to the PCI configuration register.\r | |
220 | \r | |
221 | **/\r | |
222 | UINT8\r | |
223 | EFIAPI\r | |
224 | S3PciSegmentBitFieldWrite8 (\r | |
225 | IN UINT64 Address,\r | |
226 | IN UINTN StartBit,\r | |
227 | IN UINTN EndBit,\r | |
228 | IN UINT8 Value\r | |
229 | );\r | |
230 | \r | |
231 | /**\r | |
232 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes\r | |
233 | the result back to the bit field in the 8-bit port, and saves the value in the\r | |
234 | S3 script to be replayed on S3 resume.\r | |
235 | \r | |
236 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
237 | bitwise OR between the read result and the value specified by\r | |
238 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
239 | specified by Address. The value written to the PCI configuration register is\r | |
240 | returned. This function must guarantee that all PCI read and write operations\r | |
241 | are serialized. Extra left bits in OrData are stripped.\r | |
242 | \r | |
243 | If any reserved bits in Address are set, then ASSERT().\r | |
244 | If StartBit is greater than 7, then ASSERT().\r | |
245 | If EndBit is greater than 7, then ASSERT().\r | |
246 | If EndBit is less than StartBit, then ASSERT().\r | |
247 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
248 | \r | |
249 | @param Address PCI configuration register to write.\r | |
250 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
251 | Range 0..7.\r | |
252 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
253 | Range 0..7.\r | |
254 | @param OrData The value to OR with the PCI configuration register.\r | |
255 | \r | |
256 | @return The value written back to the PCI configuration register.\r | |
257 | \r | |
258 | **/\r | |
259 | UINT8\r | |
260 | EFIAPI\r | |
261 | S3PciSegmentBitFieldOr8 (\r | |
262 | IN UINT64 Address,\r | |
263 | IN UINTN StartBit,\r | |
264 | IN UINTN EndBit,\r | |
265 | IN UINT8 OrData\r | |
266 | );\r | |
267 | \r | |
268 | /**\r | |
269 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
270 | AND, writes the result back to the bit field in the 8-bit register, and\r | |
271 | saves the value in the S3 script to be replayed on S3 resume.\r | |
272 | \r | |
273 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
274 | bitwise AND between the read result and the value specified by AndData, and\r | |
275 | writes the result to the 8-bit PCI configuration register specified by\r | |
276 | Address. The value written to the PCI configuration register is returned.\r | |
277 | This function must guarantee that all PCI read and write operations are\r | |
278 | serialized. Extra left bits in AndData are stripped.\r | |
279 | \r | |
280 | If any reserved bits in Address are set, then ASSERT().\r | |
281 | If StartBit is greater than 7, then ASSERT().\r | |
282 | If EndBit is greater than 7, then ASSERT().\r | |
283 | If EndBit is less than StartBit, then ASSERT().\r | |
284 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
285 | \r | |
286 | @param Address PCI configuration register to write.\r | |
287 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
288 | Range 0..7.\r | |
289 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
290 | Range 0..7.\r | |
291 | @param AndData The value to AND with the PCI configuration register.\r | |
292 | \r | |
293 | @return The value written back to the PCI configuration register.\r | |
294 | \r | |
295 | **/\r | |
296 | UINT8\r | |
297 | EFIAPI\r | |
298 | S3PciSegmentBitFieldAnd8 (\r | |
299 | IN UINT64 Address,\r | |
300 | IN UINTN StartBit,\r | |
301 | IN UINTN EndBit,\r | |
302 | IN UINT8 AndData\r | |
303 | );\r | |
304 | \r | |
305 | /**\r | |
306 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
307 | bitwise OR, writes the result back to the bit field in the 8-bit port,\r | |
308 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
309 | \r | |
310 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
311 | bitwise AND followed by a bitwise OR between the read result and\r | |
312 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
313 | configuration register specified by Address. The value written to the PCI\r | |
314 | configuration register is returned. This function must guarantee that all PCI\r | |
315 | read and write operations are serialized. Extra left bits in both AndData and\r | |
316 | OrData are stripped.\r | |
317 | \r | |
318 | If any reserved bits in Address are set, then ASSERT().\r | |
319 | If StartBit is greater than 7, then ASSERT().\r | |
320 | If EndBit is greater than 7, then ASSERT().\r | |
321 | If EndBit is less than StartBit, then ASSERT().\r | |
322 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
323 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
324 | \r | |
325 | @param Address PCI configuration register to write.\r | |
326 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
327 | Range 0..7.\r | |
328 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
329 | Range 0..7.\r | |
330 | @param AndData The value to AND with the PCI configuration register.\r | |
331 | @param OrData The value to OR with the result of the AND operation.\r | |
332 | \r | |
333 | @return The value written back to the PCI configuration register.\r | |
334 | \r | |
335 | **/\r | |
336 | UINT8\r | |
337 | EFIAPI\r | |
338 | S3PciSegmentBitFieldAndThenOr8 (\r | |
339 | IN UINT64 Address,\r | |
340 | IN UINTN StartBit,\r | |
341 | IN UINTN EndBit,\r | |
342 | IN UINT8 AndData,\r | |
343 | IN UINT8 OrData\r | |
344 | );\r | |
345 | \r | |
346 | /**\r | |
347 | Reads a 16-bit PCI configuration register, and saves the value in the S3 script\r | |
348 | to be replayed on S3 resume.\r | |
349 | \r | |
350 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
351 | This function must guarantee that all PCI read and write operations are serialized.\r | |
352 | \r | |
353 | If any reserved bits in Address are set, then ASSERT().\r | |
354 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
355 | \r | |
356 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
357 | \r | |
358 | @return The 16-bit PCI configuration register specified by Address.\r | |
359 | \r | |
360 | **/\r | |
361 | UINT16\r | |
362 | EFIAPI\r | |
363 | S3PciSegmentRead16 (\r | |
364 | IN UINT64 Address\r | |
365 | );\r | |
366 | \r | |
367 | /**\r | |
368 | Writes a 16-bit PCI configuration register, and saves the value in the S3 script to\r | |
369 | be replayed on S3 resume.\r | |
370 | \r | |
371 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
372 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
373 | \r | |
374 | If any reserved bits in Address are set, then ASSERT().\r | |
375 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
376 | \r | |
377 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
378 | @param Value The value to write.\r | |
379 | \r | |
380 | @return The parameter of Value.\r | |
381 | \r | |
382 | **/\r | |
383 | UINT16\r | |
384 | EFIAPI\r | |
385 | S3PciSegmentWrite16 (\r | |
386 | IN UINT64 Address,\r | |
387 | IN UINT16 Value\r | |
388 | );\r | |
389 | \r | |
390 | /**\r | |
391 | Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit\r | |
392 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
393 | \r | |
394 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
395 | bitwise OR between the read result and the value specified by OrData, and\r | |
396 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
397 | The value written to the PCI configuration register is returned. This function\r | |
398 | must guarantee that all PCI read and write operations are serialized.\r | |
399 | \r | |
400 | If any reserved bits in Address are set, then ASSERT().\r | |
401 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
402 | \r | |
403 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
404 | Register.\r | |
405 | @param OrData The value to OR with the PCI configuration register.\r | |
406 | \r | |
407 | @return The value written back to the PCI configuration register.\r | |
408 | \r | |
409 | **/\r | |
410 | UINT16\r | |
411 | EFIAPI\r | |
412 | S3PciSegmentOr16 (\r | |
413 | IN UINT64 Address,\r | |
414 | IN UINT16 OrData\r | |
415 | );\r | |
416 | \r | |
417 | /**\r | |
418 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and\r | |
419 | saves the value in the S3 script to be replayed on S3 resume.\r | |
420 | \r | |
421 | Reads the 16-bit PCI configuration register specified by Address,\r | |
422 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
423 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
424 | The value written to the PCI configuration register is returned.\r | |
425 | This function must guarantee that all PCI read and write operations are serialized.\r | |
426 | \r | |
427 | If any reserved bits in Address are set, then ASSERT().\r | |
428 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
429 | \r | |
430 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
431 | @param AndData The value to AND with the PCI configuration register.\r | |
432 | \r | |
433 | @return The value written to the PCI configuration register.\r | |
434 | \r | |
435 | **/\r | |
436 | UINT16\r | |
437 | EFIAPI\r | |
438 | S3PciSegmentAnd16 (\r | |
439 | IN UINT64 Address,\r | |
440 | IN UINT16 AndData\r | |
441 | );\r | |
442 | \r | |
443 | /**\r | |
444 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
445 | followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to\r | |
446 | be replayed on S3 resume.\r | |
447 | \r | |
448 | Reads the 16-bit PCI configuration register specified by Address,\r | |
449 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
450 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
451 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
452 | The value written to the PCI configuration register is returned.\r | |
453 | This function must guarantee that all PCI read and write operations are serialized.\r | |
454 | \r | |
455 | If any reserved bits in Address are set, then ASSERT().\r | |
456 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
457 | \r | |
458 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
459 | @param AndData The value to AND with the PCI configuration register.\r | |
460 | @param OrData The value to OR with the PCI configuration register.\r | |
461 | \r | |
462 | @return The value written to the PCI configuration register.\r | |
463 | \r | |
464 | **/\r | |
465 | UINT16\r | |
466 | EFIAPI\r | |
467 | S3PciSegmentAndThenOr16 (\r | |
468 | IN UINT64 Address,\r | |
469 | IN UINT16 AndData,\r | |
470 | IN UINT16 OrData\r | |
471 | );\r | |
472 | \r | |
473 | /**\r | |
474 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
475 | S3 script to be replayed on S3 resume.\r | |
476 | \r | |
477 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
478 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
479 | returned.\r | |
480 | \r | |
481 | If any reserved bits in Address are set, then ASSERT().\r | |
482 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
483 | If StartBit is greater than 15, then ASSERT().\r | |
484 | If EndBit is greater than 15, then ASSERT().\r | |
485 | If EndBit is less than StartBit, then ASSERT().\r | |
486 | \r | |
487 | @param Address PCI configuration register to read.\r | |
488 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
489 | Range 0..15.\r | |
490 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
491 | Range 0..15.\r | |
492 | \r | |
493 | @return The value of the bit field read from the PCI configuration register.\r | |
494 | \r | |
495 | **/\r | |
496 | UINT16\r | |
497 | EFIAPI\r | |
498 | S3PciSegmentBitFieldRead16 (\r | |
499 | IN UINT64 Address,\r | |
500 | IN UINTN StartBit,\r | |
501 | IN UINTN EndBit\r | |
502 | );\r | |
503 | \r | |
504 | /**\r | |
505 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
506 | the S3 script to be replayed on S3 resume.\r | |
507 | \r | |
508 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
509 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
510 | destination PCI configuration register are preserved. The new value of the\r | |
511 | 16-bit register is returned.\r | |
512 | \r | |
513 | If any reserved bits in Address are set, then ASSERT().\r | |
514 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
515 | If StartBit is greater than 15, then ASSERT().\r | |
516 | If EndBit is greater than 15, then ASSERT().\r | |
517 | If EndBit is less than StartBit, then ASSERT().\r | |
518 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
519 | \r | |
520 | @param Address PCI configuration register to write.\r | |
521 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
522 | Range 0..15.\r | |
523 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
524 | Range 0..15.\r | |
525 | @param Value New value of the bit field.\r | |
526 | \r | |
527 | @return The value written back to the PCI configuration register.\r | |
528 | \r | |
529 | **/\r | |
530 | UINT16\r | |
531 | EFIAPI\r | |
532 | S3PciSegmentBitFieldWrite16 (\r | |
533 | IN UINT64 Address,\r | |
534 | IN UINTN StartBit,\r | |
535 | IN UINTN EndBit,\r | |
536 | IN UINT16 Value\r | |
537 | );\r | |
538 | \r | |
539 | /**\r | |
540 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
541 | the result back to the bit field in the 16-bit port, and saves the value in the\r | |
542 | S3 script to be replayed on S3 resume.\r | |
543 | \r | |
544 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
545 | bitwise OR between the read result and the value specified by\r | |
546 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
547 | specified by Address. The value written to the PCI configuration register is\r | |
548 | returned. This function must guarantee that all PCI read and write operations\r | |
549 | are serialized. Extra left bits in OrData are stripped.\r | |
550 | \r | |
551 | If any reserved bits in Address are set, then ASSERT().\r | |
552 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
553 | If StartBit is greater than 15, then ASSERT().\r | |
554 | If EndBit is greater than 15, then ASSERT().\r | |
555 | If EndBit is less than StartBit, then ASSERT().\r | |
556 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
557 | \r | |
558 | @param Address PCI configuration register to write.\r | |
559 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
560 | Range 0..15.\r | |
561 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
562 | Range 0..15.\r | |
563 | @param OrData The value to OR with the PCI configuration register.\r | |
564 | \r | |
565 | @return The value written back to the PCI configuration register.\r | |
566 | \r | |
567 | **/\r | |
568 | UINT16\r | |
569 | EFIAPI\r | |
570 | S3PciSegmentBitFieldOr16 (\r | |
571 | IN UINT64 Address,\r | |
572 | IN UINTN StartBit,\r | |
573 | IN UINTN EndBit,\r | |
574 | IN UINT16 OrData\r | |
575 | );\r | |
576 | \r | |
577 | /**\r | |
578 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
579 | AND, writes the result back to the bit field in the 16-bit register, and\r | |
580 | saves the value in the S3 script to be replayed on S3 resume.\r | |
581 | \r | |
582 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
583 | bitwise AND between the read result and the value specified by AndData, and\r | |
584 | writes the result to the 16-bit PCI configuration register specified by\r | |
585 | Address. The value written to the PCI configuration register is returned.\r | |
586 | This function must guarantee that all PCI read and write operations are\r | |
587 | serialized. Extra left bits in AndData are stripped.\r | |
588 | \r | |
589 | If any reserved bits in Address are set, then ASSERT().\r | |
590 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
591 | If StartBit is greater than 15, then ASSERT().\r | |
592 | If EndBit is greater than 15, then ASSERT().\r | |
593 | If EndBit is less than StartBit, then ASSERT().\r | |
594 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
595 | \r | |
596 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
597 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
598 | Range 0..15.\r | |
599 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
600 | Range 0..15.\r | |
601 | @param AndData The value to AND with the PCI configuration register.\r | |
602 | \r | |
603 | @return The value written back to the PCI configuration register.\r | |
604 | \r | |
605 | **/\r | |
606 | UINT16\r | |
607 | EFIAPI\r | |
608 | S3PciSegmentBitFieldAnd16 (\r | |
609 | IN UINT64 Address,\r | |
610 | IN UINTN StartBit,\r | |
611 | IN UINTN EndBit,\r | |
612 | IN UINT16 AndData\r | |
613 | );\r | |
614 | \r | |
615 | /**\r | |
616 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
617 | bitwise OR, writes the result back to the bit field in the 16-bit port,\r | |
618 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
619 | \r | |
620 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
621 | bitwise AND followed by a bitwise OR between the read result and\r | |
622 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
623 | configuration register specified by Address. The value written to the PCI\r | |
624 | configuration register is returned. This function must guarantee that all PCI\r | |
625 | read and write operations are serialized. Extra left bits in both AndData and\r | |
626 | OrData are stripped.\r | |
627 | \r | |
628 | If any reserved bits in Address are set, then ASSERT().\r | |
629 | If StartBit is greater than 15, then ASSERT().\r | |
630 | If EndBit is greater than 15, then ASSERT().\r | |
631 | If EndBit is less than StartBit, then ASSERT().\r | |
632 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
633 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
634 | \r | |
635 | @param Address PCI configuration register to write.\r | |
636 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
637 | Range 0..15.\r | |
638 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
639 | Range 0..15.\r | |
640 | @param AndData The value to AND with the PCI configuration register.\r | |
641 | @param OrData The value to OR with the result of the AND operation.\r | |
642 | \r | |
643 | @return The value written back to the PCI configuration register.\r | |
644 | \r | |
645 | **/\r | |
646 | UINT16\r | |
647 | EFIAPI\r | |
648 | S3PciSegmentBitFieldAndThenOr16 (\r | |
649 | IN UINT64 Address,\r | |
650 | IN UINTN StartBit,\r | |
651 | IN UINTN EndBit,\r | |
652 | IN UINT16 AndData,\r | |
653 | IN UINT16 OrData\r | |
654 | );\r | |
655 | \r | |
656 | /**\r | |
657 | Reads a 32-bit PCI configuration register, and saves the value in the S3 script\r | |
658 | to be replayed on S3 resume.\r | |
659 | \r | |
660 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
661 | This function must guarantee that all PCI read and write operations are serialized.\r | |
662 | \r | |
663 | If any reserved bits in Address are set, then ASSERT().\r | |
664 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
665 | \r | |
666 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
667 | \r | |
668 | @return The 32-bit PCI configuration register specified by Address.\r | |
669 | \r | |
670 | **/\r | |
671 | UINT32\r | |
672 | EFIAPI\r | |
673 | S3PciSegmentRead32 (\r | |
674 | IN UINT64 Address\r | |
675 | );\r | |
676 | \r | |
677 | /**\r | |
678 | Writes a 32-bit PCI configuration register, and saves the value in the S3 script to\r | |
679 | be replayed on S3 resume.\r | |
680 | \r | |
681 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
682 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
683 | \r | |
684 | If any reserved bits in Address are set, then ASSERT().\r | |
685 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
686 | \r | |
687 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
688 | @param Value The value to write.\r | |
689 | \r | |
690 | @return The parameter of Value.\r | |
691 | \r | |
692 | **/\r | |
693 | UINT32\r | |
694 | EFIAPI\r | |
695 | S3PciSegmentWrite32 (\r | |
696 | IN UINT64 Address,\r | |
697 | IN UINT32 Value\r | |
698 | );\r | |
699 | \r | |
700 | /**\r | |
701 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit\r | |
702 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
703 | \r | |
704 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
705 | bitwise OR between the read result and the value specified by OrData, and\r | |
706 | writes the result to the 32-bit PCI configuration register specified by Address.\r | |
707 | The value written to the PCI configuration register is returned. This function\r | |
708 | must guarantee that all PCI read and write operations are serialized.\r | |
709 | \r | |
710 | If any reserved bits in Address are set, then ASSERT().\r | |
711 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
712 | \r | |
713 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and\r | |
714 | Register.\r | |
715 | @param OrData The value to OR with the PCI configuration register.\r | |
716 | \r | |
717 | @return The value written back to the PCI configuration register.\r | |
718 | \r | |
719 | **/\r | |
720 | UINT32\r | |
721 | EFIAPI\r | |
722 | S3PciSegmentOr32 (\r | |
723 | IN UINT64 Address,\r | |
724 | IN UINT32 OrData\r | |
725 | );\r | |
726 | \r | |
727 | /**\r | |
728 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and\r | |
729 | saves the value in the S3 script to be replayed on S3 resume.\r | |
730 | \r | |
731 | Reads the 32-bit PCI configuration register specified by Address,\r | |
732 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
733 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
734 | The value written to the PCI configuration register is returned.\r | |
735 | This function must guarantee that all PCI read and write operations are serialized.\r | |
736 | \r | |
737 | If any reserved bits in Address are set, then ASSERT().\r | |
738 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
739 | \r | |
740 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
741 | @param AndData The value to AND with the PCI configuration register.\r | |
742 | \r | |
743 | @return The value written to the PCI configuration register.\r | |
744 | \r | |
745 | **/\r | |
746 | UINT32\r | |
747 | EFIAPI\r | |
748 | S3PciSegmentAnd32 (\r | |
749 | IN UINT64 Address,\r | |
750 | IN UINT32 AndData\r | |
751 | );\r | |
752 | \r | |
753 | /**\r | |
754 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
755 | followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to\r | |
756 | be replayed on S3 resume.\r | |
757 | \r | |
758 | Reads the 32-bit PCI configuration register specified by Address,\r | |
759 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
760 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
761 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
762 | The value written to the PCI configuration register is returned.\r | |
763 | This function must guarantee that all PCI read and write operations are serialized.\r | |
764 | \r | |
765 | If any reserved bits in Address are set, then ASSERT().\r | |
766 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
767 | \r | |
768 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
769 | @param AndData The value to AND with the PCI configuration register.\r | |
770 | @param OrData The value to OR with the PCI configuration register.\r | |
771 | \r | |
772 | @return The value written to the PCI configuration register.\r | |
773 | \r | |
774 | **/\r | |
775 | UINT32\r | |
776 | EFIAPI\r | |
777 | S3PciSegmentAndThenOr32 (\r | |
778 | IN UINT64 Address,\r | |
779 | IN UINT32 AndData,\r | |
780 | IN UINT32 OrData\r | |
781 | );\r | |
782 | \r | |
783 | /**\r | |
784 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
785 | S3 script to be replayed on S3 resume.\r | |
786 | \r | |
787 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
788 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
789 | returned.\r | |
790 | \r | |
791 | If any reserved bits in Address are set, then ASSERT().\r | |
792 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
793 | If StartBit is greater than 31, then ASSERT().\r | |
794 | If EndBit is greater than 31, then ASSERT().\r | |
795 | If EndBit is less than StartBit, then ASSERT().\r | |
796 | \r | |
797 | @param Address PCI configuration register to read.\r | |
798 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
799 | Range 0..31.\r | |
800 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
801 | Range 0..31.\r | |
802 | \r | |
803 | @return The value of the bit field read from the PCI configuration register.\r | |
804 | \r | |
805 | **/\r | |
806 | UINT32\r | |
807 | EFIAPI\r | |
808 | S3PciSegmentBitFieldRead32 (\r | |
809 | IN UINT64 Address,\r | |
810 | IN UINTN StartBit,\r | |
811 | IN UINTN EndBit\r | |
812 | );\r | |
813 | \r | |
814 | /**\r | |
815 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
816 | the S3 script to be replayed on S3 resume.\r | |
817 | \r | |
818 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
819 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
820 | destination PCI configuration register are preserved. The new value of the\r | |
821 | 32-bit register is returned.\r | |
822 | \r | |
823 | If any reserved bits in Address are set, then ASSERT().\r | |
824 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
825 | If StartBit is greater than 31, then ASSERT().\r | |
826 | If EndBit is greater than 31, then ASSERT().\r | |
827 | If EndBit is less than StartBit, then ASSERT().\r | |
828 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
829 | \r | |
830 | @param Address PCI configuration register to write.\r | |
831 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
832 | Range 0..31.\r | |
833 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
834 | Range 0..31.\r | |
835 | @param Value New value of the bit field.\r | |
836 | \r | |
837 | @return The value written back to the PCI configuration register.\r | |
838 | \r | |
839 | **/\r | |
840 | UINT32\r | |
841 | EFIAPI\r | |
842 | S3PciSegmentBitFieldWrite32 (\r | |
843 | IN UINT64 Address,\r | |
844 | IN UINTN StartBit,\r | |
845 | IN UINTN EndBit,\r | |
846 | IN UINT32 Value\r | |
847 | );\r | |
848 | \r | |
849 | /**\r | |
850 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes\r | |
851 | the result back to the bit field in the 32-bit port, and saves the value in the\r | |
852 | S3 script to be replayed on S3 resume.\r | |
853 | \r | |
854 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
855 | bitwise OR between the read result and the value specified by\r | |
856 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
857 | specified by Address. The value written to the PCI configuration register is\r | |
858 | returned. This function must guarantee that all PCI read and write operations\r | |
859 | are serialized. Extra left bits in OrData are stripped.\r | |
860 | \r | |
861 | If any reserved bits in Address are set, then ASSERT().\r | |
862 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
863 | If StartBit is greater than 31, then ASSERT().\r | |
864 | If EndBit is greater than 31, then ASSERT().\r | |
865 | If EndBit is less than StartBit, then ASSERT().\r | |
866 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
867 | \r | |
868 | @param Address PCI configuration register to write.\r | |
869 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
870 | Range 0..31.\r | |
871 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
872 | Range 0..31.\r | |
873 | @param OrData The value to OR with the PCI configuration register.\r | |
874 | \r | |
875 | @return The value written back to the PCI configuration register.\r | |
876 | \r | |
877 | **/\r | |
878 | UINT32\r | |
879 | EFIAPI\r | |
880 | S3PciSegmentBitFieldOr32 (\r | |
881 | IN UINT64 Address,\r | |
882 | IN UINTN StartBit,\r | |
883 | IN UINTN EndBit,\r | |
884 | IN UINT32 OrData\r | |
885 | );\r | |
886 | \r | |
887 | /**\r | |
888 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
889 | AND, and writes the result back to the bit field in the 32-bit register, and\r | |
890 | saves the value in the S3 script to be replayed on S3 resume.\r | |
891 | \r | |
892 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
893 | bitwise AND between the read result and the value specified by AndData, and\r | |
894 | writes the result to the 32-bit PCI configuration register specified by\r | |
895 | Address. The value written to the PCI configuration register is returned.\r | |
896 | This function must guarantee that all PCI read and write operations are\r | |
897 | serialized. Extra left bits in AndData are stripped.\r | |
898 | \r | |
899 | If any reserved bits in Address are set, then ASSERT().\r | |
900 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
901 | If StartBit is greater than 31, then ASSERT().\r | |
902 | If EndBit is greater than 31, then ASSERT().\r | |
903 | If EndBit is less than StartBit, then ASSERT().\r | |
904 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
905 | \r | |
906 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
907 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
908 | Range 0..31.\r | |
909 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
910 | Range 0..31.\r | |
911 | @param AndData The value to AND with the PCI configuration register.\r | |
912 | \r | |
913 | @return The value written back to the PCI configuration register.\r | |
914 | \r | |
915 | **/\r | |
916 | UINT32\r | |
917 | EFIAPI\r | |
918 | S3PciSegmentBitFieldAnd32 (\r | |
919 | IN UINT64 Address,\r | |
920 | IN UINTN StartBit,\r | |
921 | IN UINTN EndBit,\r | |
922 | IN UINT32 AndData\r | |
923 | );\r | |
924 | \r | |
925 | /**\r | |
926 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
927 | bitwise OR, writes the result back to the bit field in the 32-bit port,\r | |
928 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
929 | \r | |
930 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
931 | bitwise AND followed by a bitwise OR between the read result and\r | |
932 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
933 | configuration register specified by Address. The value written to the PCI\r | |
934 | configuration register is returned. This function must guarantee that all PCI\r | |
935 | read and write operations are serialized. Extra left bits in both AndData and\r | |
936 | OrData are stripped.\r | |
937 | \r | |
938 | If any reserved bits in Address are set, then ASSERT().\r | |
939 | If StartBit is greater than 31, then ASSERT().\r | |
940 | If EndBit is greater than 31, then ASSERT().\r | |
941 | If EndBit is less than StartBit, then ASSERT().\r | |
942 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
943 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
944 | \r | |
945 | @param Address PCI configuration register to write.\r | |
946 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
947 | Range 0..31.\r | |
948 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
949 | Range 0..31.\r | |
950 | @param AndData The value to AND with the PCI configuration register.\r | |
951 | @param OrData The value to OR with the result of the AND operation.\r | |
952 | \r | |
953 | @return The value written back to the PCI configuration register.\r | |
954 | \r | |
955 | **/\r | |
956 | UINT32\r | |
957 | EFIAPI\r | |
958 | S3PciSegmentBitFieldAndThenOr32 (\r | |
959 | IN UINT64 Address,\r | |
960 | IN UINTN StartBit,\r | |
961 | IN UINTN EndBit,\r | |
962 | IN UINT32 AndData,\r | |
963 | IN UINT32 OrData\r | |
964 | );\r | |
965 | \r | |
966 | /**\r | |
967 | Reads a range of PCI configuration registers into a caller supplied buffer,\r | |
968 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
969 | \r | |
970 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
971 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
972 | configuration registers from a single PCI function to be read. Size is\r | |
973 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
974 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
975 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
976 | end of the range.\r | |
977 | \r | |
978 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
979 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
980 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
981 | \r | |
982 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
983 | Function and Register.\r | |
984 | @param Size Size in bytes of the transfer.\r | |
985 | @param Buffer Pointer to a buffer receiving the data read.\r | |
986 | \r | |
987 | @return Size\r | |
988 | \r | |
989 | **/\r | |
990 | UINTN\r | |
991 | EFIAPI\r | |
992 | S3PciSegmentReadBuffer (\r | |
993 | IN UINT64 StartAddress,\r | |
994 | IN UINTN Size,\r | |
995 | OUT VOID *Buffer\r | |
996 | );\r | |
997 | \r | |
998 | /**\r | |
999 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1000 | configuration space, and saves the value in the S3 script to be replayed on S3\r | |
1001 | resume.\r | |
1002 | \r | |
1003 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1004 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1005 | configuration registers from a single PCI function to be written. Size is\r | |
1006 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1007 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1008 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1009 | and the end of the range.\r | |
1010 | \r | |
1011 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1012 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1013 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1014 | \r | |
1015 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1016 | Function and Register.\r | |
1017 | @param Size Size in bytes of the transfer.\r | |
1018 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1019 | \r | |
1020 | @return The parameter of Size.\r | |
1021 | \r | |
1022 | **/\r | |
1023 | UINTN\r | |
1024 | EFIAPI\r | |
1025 | S3PciSegmentWriteBuffer (\r | |
1026 | IN UINT64 StartAddress,\r | |
1027 | IN UINTN Size,\r | |
1028 | IN VOID *Buffer\r | |
1029 | );\r | |
1030 | \r | |
1031 | #endif\r |