MdePkg/BaseLib: BaseLib for RISCV64 architecture

Add RISC-V RV64 BaseLib functions.

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=2672

Signed-off-by: Abner Chang <abner.chang@hpe.com>
Co-authored-by: Gilbert Chen <gilbert.chen@hpe.com>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
Reviewed-by: Zhiguang Liu <zhiguang.liu@intel.com>
Cc: Michael D Kinney <michael.d.kinney@intel.com>
Cc: Liming Gao <liming.gao@intel.com>
Cc: Leif Lindholm <leif.lindholm@linaro.org>
Cc: Gilbert Chen <gilbert.chen@hpe.com>

diff --git a/MdePkg/Include/Library/BaseLib.h b/MdePkg/Include/Library/BaseLib.h
index d066f1be2495e261c9f7340221fad4fd7541885b..b0bbe8cef83430015499cfd7c216228b30fd2a42 100644 (file)
--- a/MdePkg/Include/Library/BaseLib.h
+++ b/MdePkg/Include/Library/BaseLib.h
@@ -5,6 +5,8 @@
 Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
 Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 Copyright (c) Microsoft Corporation.<BR>\r
+Portions Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
 SPDX-License-Identifier: BSD-2-Clause-Patent\r
 \r
 **/\r
@@ -125,6 +127,30 @@ typedef struct {
 \r
 #endif  // defined (MDE_CPU_AARCH64)\r
 \r
+#if defined (MDE_CPU_RISCV64)\r
+///\r
+/// The RISC-V architecture context buffer used by SetJump() and LongJump().\r
+///\r
+typedef struct {\r
+  UINT64                            RA;\r
+  UINT64                            S0;\r
+  UINT64                            S1;\r
+  UINT64                            S2;\r
+  UINT64                            S3;\r
+  UINT64                            S4;\r
+  UINT64                            S5;\r
+  UINT64                            S6;\r
+  UINT64                            S7;\r
+  UINT64                            S8;\r
+  UINT64                            S9;\r
+  UINT64                            S10;\r
+  UINT64                            S11;\r
+  UINT64                            SP;\r
+} BASE_LIBRARY_JUMP_BUFFER;\r
+\r
+#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8\r
+\r
+#endif // defined (MDE_CPU_RISCV64)\r
 \r
 //\r
 // String Services\r

diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf
index 3586beb0ab5c53646f2edcd05d751d33526d1ebc..a57ae2da31f3f6ae54ef2da31751e785a793e119 100644 (file)
--- a/MdePkg/Library/BaseLib/BaseLib.inf
+++ b/MdePkg/Library/BaseLib/BaseLib.inf
@@ -4,6 +4,7 @@
 #  Copyright (c) 2007 - 2019, Intel Corporation. All rights reserved.<BR>\r
 #  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
 #  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
+#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
 #\r
 #  SPDX-License-Identifier: BSD-2-Clause-Patent\r
 #\r
@@ -20,7 +21,7 @@
   LIBRARY_CLASS                  = BaseLib\r
 \r
 #\r
-#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64\r
+#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64 RISCV64\r
 #\r
 \r
 [Sources]\r
@@ -381,6 +382,21 @@
   AArch64/CpuBreakpoint.asm         | MSFT\r
   AArch64/SpeculationBarrier.asm    | MSFT\r
 \r
+[Sources.RISCV64]\r
+  Math64.c\r
+  Unaligned.c\r
+  RiscV64/InternalSwitchStack.c\r
+  RiscV64/CpuBreakpoint.c\r
+  RiscV64/GetInterruptState.c\r
+  RiscV64/DisableInterrupts.c\r
+  RiscV64/EnableInterrupts.c\r
+  RiscV64/CpuPause.c\r
+  RiscV64/RiscVSetJumpLongJump.S    | GCC\r
+  RiscV64/RiscVCpuBreakpoint.S      | GCC\r
+  RiscV64/RiscVCpuPause.S           | GCC\r
+  RiscV64/RiscVInterrupt.S          | GCC\r
+  RiscV64/FlushCache.S              | GCC\r
+\r
 [Packages]\r
   MdePkg/MdePkg.dec\r
 \r

diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
new file mode 100644 (file)
index 0000000..88d0877
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuBreakpoint.c
@@ -0,0 +1,27 @@
+/** @file\r
+  CPU breakpoint for RISC-V\r
+\r
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+extern VOID RiscVCpuBreakpoint (VOID);\r
+\r
+/**\r
+  Generates a breakpoint on the CPU.\r
+\r
+  Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
+  that code can resume normal execution after the breakpoint.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuBreakpoint (\r
+  VOID\r
+  )\r
+{\r
+  RiscVCpuBreakpoint ();\r
+}\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/CpuPause.c b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
new file mode 100644 (file)
index 0000000..9931bad
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/CpuPause.c
@@ -0,0 +1,29 @@
+/** @file\r
+  CPU pause for RISC-V\r
+\r
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+extern VOID RiscVCpuPause (VOID);\r
+\r
+\r
+/**\r
+  Requests CPU to pause for a short period of time.\r
+\r
+  Requests CPU to pause for a short period of time. Typically used in MP\r
+  systems to prevent memory starvation while waiting for a spin lock.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+CpuPause (\r
+  VOID\r
+  )\r
+{\r
+  RiscVCpuPause ();\r
+}\r
+\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
new file mode 100644 (file)
index 0000000..867086c
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/DisableInterrupts.c
@@ -0,0 +1,24 @@
+/** @file\r
+  CPU disable interrupt function for RISC-V\r
+\r
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+#include "BaseLibInternals.h"\r
+\r
+extern VOID RiscVDisableSupervisorModeInterrupts (VOID);\r
+\r
+/**\r
+  Disables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+DisableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  RiscVDisableSupervisorModeInterrupts ();\r
+}\r
+\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
new file mode 100644 (file)
index 0000000..22ef730
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/EnableInterrupts.c
@@ -0,0 +1,25 @@
+/** @file\r
+  CPU enable interrupt function for RISC-V\r
+\r
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+extern VOID RiscVEnableSupervisorModeInterrupt (VOID);\r
+\r
+/**\r
+  Enables CPU interrupts.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+EnableInterrupts (\r
+  VOID\r
+  )\r
+{\r
+  RiscVEnableSupervisorModeInterrupt ();\r
+}\r
+\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/FlushCache.S b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
new file mode 100644 (file)
index 0000000..7c10fdd
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/FlushCache.S
@@ -0,0 +1,21 @@
+//------------------------------------------------------------------------------\r
+//\r
+// RISC-V cache operation.\r
+//\r
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+.align 3\r
+ASM_GLOBAL ASM_PFX(RiscVInvalidateInstCacheAsm)\r
+ASM_GLOBAL ASM_PFX(RiscVInvalidateDataCacheAsm)\r
+\r
+ASM_PFX(RiscVInvalidateInstCacheAsm):\r
+    fence.i\r
+    ret\r
+\r
+ASM_PFX(RiscVInvalidateDataCacheAsm):\r
+    fence\r
+    ret\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
new file mode 100644 (file)
index 0000000..292f1ec
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/GetInterruptState.c
@@ -0,0 +1,35 @@
+/** @file\r
+  CPU get interrupt state function for RISC-V\r
+\r
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+extern UINT32 RiscVGetSupervisorModeInterrupts (VOID);\r
+\r
+/**\r
+  Retrieves the current CPU interrupt state.\r
+\r
+  Returns TRUE is interrupts are currently enabled. Otherwise\r
+  returns FALSE.\r
+\r
+  @retval TRUE  CPU interrupts are enabled.\r
+  @retval FALSE CPU interrupts are disabled.\r
+\r
+**/\r
+BOOLEAN\r
+EFIAPI\r
+GetInterruptState (\r
+  VOID\r
+  )\r
+{\r
+  unsigned long RetValue;\r
+\r
+  RetValue = RiscVGetSupervisorModeInterrupts ();\r
+  return RetValue? TRUE: FALSE;\r
+}\r
+\r
+\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
new file mode 100644 (file)
index 0000000..0bb2921
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/InternalSwitchStack.c
@@ -0,0 +1,55 @@
+/** @file\r
+  Switch stack function for RISC-V\r
+\r
+  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+\r
+  SPDX-License-Identifier: BSD-2-Clause-Patent\r
+**/\r
+\r
+#include "BaseLibInternals.h"\r
+\r
+/**\r
+  Transfers control to a function starting with a new stack.\r
+\r
+  Transfers control to the function specified by EntryPoint using the\r
+  new stack specified by NewStack and passing in the parameters specified\r
+  by Context1 and Context2.  Context1 and Context2 are optional and may\r
+  be NULL.  The function EntryPoint must never return.\r
+  Marker will be ignored on IA-32, x64, and EBC.\r
+  IPF CPUs expect one additional parameter of type VOID * that specifies\r
+  the new backing store pointer.\r
+\r
+  If EntryPoint is NULL, then ASSERT().\r
+  If NewStack is NULL, then ASSERT().\r
+\r
+  @param  EntryPoint  A pointer to function to call with the new stack.\r
+  @param  Context1    A pointer to the context to pass into the EntryPoint\r
+                      function.\r
+  @param  Context2    A pointer to the context to pass into the EntryPoint\r
+                      function.\r
+  @param  NewStack    A pointer to the new stack to use for the EntryPoint\r
+                      function.\r
+  @param  Marker      VA_LIST marker for the variable argument list.\r
+\r
+**/\r
+VOID\r
+EFIAPI\r
+InternalSwitchStack (\r
+  IN      SWITCH_STACK_ENTRY_POINT  EntryPoint,\r
+  IN      VOID                      *Context1,   OPTIONAL\r
+  IN      VOID                      *Context2,   OPTIONAL\r
+  IN      VOID                      *NewStack,\r
+  IN      VA_LIST                   Marker\r
+  )\r
+{\r
+  BASE_LIBRARY_JUMP_BUFFER  JumpBuffer;\r
+\r
+  DEBUG ((DEBUG_INFO, "RISC-V InternalSwitchStack Entry:%x Context1:%x Context2:%x NewStack%x\n", \\r
+          EntryPoint, Context1, Context2, NewStack));\r
+  JumpBuffer.RA = (UINTN)EntryPoint;\r
+  JumpBuffer.SP = (UINTN)NewStack - sizeof (VOID *);\r
+  JumpBuffer.S0 = (UINT64)(UINTN)Context1;\r
+  JumpBuffer.S1 = (UINT64)(UINTN)Context2;\r
+  LongJump (&JumpBuffer, (UINTN)-1);\r
+  ASSERT(FALSE);\r
+}\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
new file mode 100644 (file)
index 0000000..ccf91df
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuBreakpoint.S
@@ -0,0 +1,14 @@
+//------------------------------------------------------------------------------\r
+//\r
+// CpuBreakpoint for RISC-V\r
+//\r
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(RiscVCpuBreakpoint)\r
+ASM_PFX(RiscVCpuBreakpoint):\r
+  ebreak\r
+  ret\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
new file mode 100644 (file)
index 0000000..6660c2f
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVCpuPause.S
@@ -0,0 +1,14 @@
+//------------------------------------------------------------------------------\r
+//\r
+// CpuPause for RISC-V\r
+//\r
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(RiscVCpuPause)\r
+ASM_PFX(RiscVCpuPause):\r
+  nop\r
+  ret\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
new file mode 100644 (file)
index 0000000..766fcfb
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVInterrupt.S
@@ -0,0 +1,32 @@
+//------------------------------------------------------------------------------\r
+//\r
+// RISC-V Supervisor Mode interrupt enable/disable\r
+//\r
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+//------------------------------------------------------------------------------\r
+\r
+ASM_GLOBAL ASM_PFX(RiscVDisableSupervisorModeInterrupts)\r
+ASM_GLOBAL ASM_PFX(RiscVEnableSupervisorModeInterrupt)\r
+ASM_GLOBAL ASM_PFX(RiscVGetSupervisorModeInterrupts)\r
+\r
+# define  MSTATUS_SIE    0x00000002\r
+# define  CSR_SSTATUS    0x100\r
+\r
+ASM_PFX(RiscVDisableSupervisorModeInterrupts):\r
+  li   a1, MSTATUS_SIE\r
+  csrc CSR_SSTATUS, a1\r
+  ret\r
+\r
+ASM_PFX(RiscVEnableSupervisorModeInterrupt):\r
+  li   a1, MSTATUS_SIE\r
+  csrs CSR_SSTATUS, a1\r
+  ret\r
+\r
+ASM_PFX(RiscVGetSupervisorModeInterrupts):\r
+  csrr a0, CSR_SSTATUS\r
+  andi a0, a0, MSTATUS_SIE\r
+  ret\r
+\r

diff --git a/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
new file mode 100644 (file)
index 0000000..34486ea
--- /dev/null
+++ b/MdePkg/Library/BaseLib/RiscV64/RiscVSetJumpLongJump.S
@@ -0,0 +1,55 @@
+//------------------------------------------------------------------------------\r
+//\r
+// Set/Long jump for RISC-V\r
+//\r
+// Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
+//\r
+// SPDX-License-Identifier: BSD-2-Clause-Patent\r
+//\r
+//------------------------------------------------------------------------------\r
+# define REG_S  sd\r
+# define REG_L  ld\r
+# define SZREG  8\r
+.align 3\r
+    .globl  SetJump\r
+\r
+SetJump:\r
+    REG_S ra,  0*SZREG(a0)\r
+    REG_S s0,  1*SZREG(a0)\r
+    REG_S s1,  2*SZREG(a0)\r
+    REG_S s2,  3*SZREG(a0)\r
+    REG_S s3,  4*SZREG(a0)\r
+    REG_S s4,  5*SZREG(a0)\r
+    REG_S s5,  6*SZREG(a0)\r
+    REG_S s6,  7*SZREG(a0)\r
+    REG_S s7,  8*SZREG(a0)\r
+    REG_S s8,  9*SZREG(a0)\r
+    REG_S s9,  10*SZREG(a0)\r
+    REG_S s10, 11*SZREG(a0)\r
+    REG_S s11, 12*SZREG(a0)\r
+    REG_S sp,  13*SZREG(a0)\r
+    li    a0,  0\r
+    ret\r
+\r
+    .globl  InternalLongJump\r
+InternalLongJump:\r
+    REG_L ra,  0*SZREG(a0)\r
+    REG_L s0,  1*SZREG(a0)\r
+    REG_L s1,  2*SZREG(a0)\r
+    REG_L s2,  3*SZREG(a0)\r
+    REG_L s3,  4*SZREG(a0)\r
+    REG_L s4,  5*SZREG(a0)\r
+    REG_L s5,  6*SZREG(a0)\r
+    REG_L s6,  7*SZREG(a0)\r
+    REG_L s7,  8*SZREG(a0)\r
+    REG_L s8,  9*SZREG(a0)\r
+    REG_L s9,  10*SZREG(a0)\r
+    REG_L s10, 11*SZREG(a0)\r
+    REG_L s11, 12*SZREG(a0)\r
+    REG_L sp,  13*SZREG(a0)\r
+\r
+    add   a0, s0, 0\r
+    add   a1, s1, 0\r
+    add   a2, s2, 0\r
+    add   a3, s3, 0\r
+    ret\r