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4006b0b5 EL |
1 | /** @file\r |
2 | This PPI manipulates the I2C host controller to perform transactions as a master \r | |
3 | on the I2C bus using the current state of any switches or multiplexers in the I2C bus.\r | |
4 | \r | |
5 | Copyright (c) 2013, Intel Corporation. All rights reserved.<BR>\r | |
6 | This program and the accompanying materials \r | |
7 | are licensed and made available under the terms and conditions of the BSD License \r | |
8 | which accompanies this distribution. The full text of the license may be found at \r | |
9 | http://opensource.org/licenses/bsd-license.php \r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
13 | \r | |
14 | @par Revision Reference:\r | |
15 | This PPI is introduced in PI Version 1.3.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | #ifndef __I2C_MASTER_PPI_H__\r | |
20 | #define __I2C_MASTER_PPI_H__\r | |
21 | \r | |
22 | #include <Pi/PiI2c.h>\r | |
23 | \r | |
24 | #define EFI_PEI_I2C_MASTER_PPI_GUID \\r | |
25 | { 0xb3bfab9b, 0x9f9c, 0x4e8b, { 0xad, 0x37, 0x7f, 0x8c, 0x51, 0xfc, 0x62, 0x80 }}\r | |
26 | \r | |
27 | typedef struct _EFI_PEI_I2C_MASTER_PPI EFI_PEI_I2C_MASTER_PPI;\r | |
28 | \r | |
29 | /**\r | |
30 | Set the frequency for the I2C clock line.\r | |
31 | \r | |
32 | @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.\r | |
33 | @param BusClockHertz Pointer to the requested I2C bus clock frequency in Hertz.\r | |
34 | Upon return this value contains the actual frequency \r | |
35 | in use by the I2C controller.\r | |
36 | \r | |
37 | @retval EFI_SUCCESS The bus frequency was set successfully.\r | |
38 | @retval EFI_INVALID_PARAMETER BusClockHertz is NULL\r | |
39 | @retval EFI_UNSUPPORTED The controller does not support this frequency.\r | |
40 | \r | |
41 | **/\r | |
42 | typedef\r | |
43 | EFI_STATUS\r | |
44 | (EFIAPI *EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY) (\r | |
45 | IN EFI_PEI_I2C_MASTER_PPI *This,\r | |
46 | IN UINTN *BusClockHertz\r | |
47 | );\r | |
48 | \r | |
49 | /**\r | |
50 | Reset the I2C controller and configure it for use.\r | |
51 | \r | |
52 | @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.\r | |
53 | \r | |
54 | @retval EFI_SUCCESS The reset completed successfully.\r | |
55 | @retval EFI_DEVICE_ERROR The reset operation failed.\r | |
56 | \r | |
57 | **/\r | |
58 | typedef\r | |
59 | EFI_STATUS\r | |
60 | (EFIAPI *EFI_PEI_I2C_MASTER_PPI_RESET) (\r | |
61 | IN CONST EFI_PEI_I2C_MASTER_PPI *This\r | |
62 | );\r | |
63 | \r | |
64 | /**\r | |
65 | Start an I2C transaction on the host controller.\r | |
66 | \r | |
67 | @param This Pointer to an EFI_PEI_I2C_MASTER_PPI structure.\r | |
68 | @param SlaveAddress Address of the device on the I2C bus.\r | |
69 | Set the I2C_ADDRESSING_10_BIT when using 10-bit addresses, \r | |
70 | clear this bit for 7-bit addressing.\r | |
71 | Bits 0-6 are used for 7-bit I2C slave addresses and \r | |
72 | bits 0-9 are used for 10-bit I2C slave addresses.\r | |
73 | @param RequestPacket Pointer to an EFI_I2C_REQUEST_PACKET structure describing the I2C transaction.\r | |
74 | \r | |
75 | @retval EFI_SUCCESS The transaction completed successfully.\r | |
76 | @retval EFI_BAD_BUFFER_SIZE The RequestPacket->LengthInBytes value is too large.\r | |
77 | @retval EFI_DEVICE_ERROR There was an I2C error (NACK) during the transaction.\r | |
78 | @retval EFI_INVALID_PARAMETER RequestPacket is NULL\r | |
79 | @retval EFI_NO_RESPONSE The I2C device is not responding to the slave address.\r | |
80 | EFI_DEVICE_ERROR will be returned if the controller cannot distinguish when the NACK occurred.\r | |
81 | @retval EFI_NOT_FOUND Reserved bit set in the SlaveAddress parameter\r | |
82 | @retval EFI_OUT_OF_RESOURCES Insufficient memory for I2C transaction\r | |
83 | @retval EFI_UNSUPPORTED The controller does not support the requested transaction.\r | |
84 | \r | |
85 | **/\r | |
86 | typedef\r | |
87 | EFI_STATUS\r | |
88 | (EFIAPI *EFI_PEI_I2C_MASTER_PPI_START_REQUEST) (\r | |
89 | IN CONST EFI_PEI_I2C_MASTER_PPI *This,\r | |
90 | IN UINTN SlaveAddress,\r | |
91 | IN EFI_I2C_REQUEST_PACKET *RequestPacket\r | |
92 | );\r | |
93 | \r | |
94 | ///\r | |
95 | /// This PPI manipulates the I2C host controller to perform transactions as a master on the I2C bus\r | |
96 | /// using the current state of any switches or multiplexers in the I2C bus.\r | |
97 | ///\r | |
98 | struct _EFI_PEI_I2C_MASTER_PPI {\r | |
99 | EFI_PEI_I2C_MASTER_PPI_SET_BUS_FREQUENCY SetBusFrequency;\r | |
100 | EFI_PEI_I2C_MASTER_PPI_RESET Reset;\r | |
101 | EFI_PEI_I2C_MASTER_PPI_START_REQUEST StartRequest;\r | |
102 | CONST EFI_I2C_CONTROLLER_CAPABILITIES *I2cControllerCapabilities;\r | |
103 | EFI_GUID Identifier;\r | |
104 | };\r | |
105 | \r | |
106 | extern EFI_GUID gEfiPeiI2cMasterPpiGuid;\r | |
107 | \r | |
108 | #endif\r |