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5879b875 | 1 | /** @file\r |
2 | This file declares PciCfg PPI used to access PCI configuration space in PEI\r | |
3 | \r | |
4 | Copyright (c) 2006 - 2007, Intel Corporation \r | |
5 | All rights reserved. This program and the accompanying materials \r | |
6 | are licensed and made available under the terms and conditions of the BSD License \r | |
7 | which accompanies this distribution. The full text of the license may be found at \r | |
8 | http://opensource.org/licenses/bsd-license.php \r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, \r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. \r | |
12 | \r | |
5879b875 | 13 | @par Revision Reference:\r |
14 | This PPI is defined in PI\r | |
15 | Version 1.00.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | #ifndef __PEI_PCI_CFG2_H__\r | |
20 | #define __PEI_PCI_CFG2_H__\r | |
21 | \r | |
22 | \r | |
23 | #define EFI_PEI_PCI_CFG2_PPI_GUID \\r | |
24 | { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r | |
25 | \r | |
26 | \r | |
27 | typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;\r | |
28 | \r | |
29 | #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r | |
30 | (((bus) << 24) | \\r | |
31 | ((dev) << 16) | \\r | |
32 | ((func) << 8) | \\r | |
33 | ((reg) < 256 ? (reg) : ((UINT64) (reg) << 32)));\r | |
34 | \r | |
35 | //\r | |
36 | // EFI_PEI_PCI_CFG_PPI_WIDTH\r | |
37 | //\r | |
38 | typedef enum {\r | |
39 | EfiPeiPciCfgWidthUint8 = 0,\r | |
40 | EfiPeiPciCfgWidthUint16 = 1,\r | |
41 | EfiPeiPciCfgWidthUint32 = 2,\r | |
42 | EfiPeiPciCfgWidthUint64 = 3,\r | |
43 | EfiPeiPciCfgWidthMaximum\r | |
44 | } EFI_PEI_PCI_CFG_PPI_WIDTH;\r | |
45 | \r | |
46 | //\r | |
47 | // EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS\r | |
48 | //\r | |
49 | typedef struct {\r | |
50 | UINT8 Register;\r | |
51 | UINT8 Function;\r | |
52 | UINT8 Device;\r | |
53 | UINT8 Bus;\r | |
54 | UINT32 ExtendedRegister;\r | |
55 | } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r | |
56 | \r | |
57 | /**\r | |
58 | Reads from or write to a given location in the PCI configuration space.\r | |
59 | \r | |
60 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r | |
61 | \r | |
62 | @param This Pointer to local data for the interface.\r | |
63 | \r | |
64 | @param Width The width of the access. Enumerated in bytes. \r | |
65 | See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r | |
66 | \r | |
67 | @param Address The physical address of the access. The format of \r | |
68 | the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r | |
69 | \r | |
70 | @param Buffer A pointer to the buffer of data..\r | |
71 | \r | |
72 | \r | |
73 | @retval EFI_SUCCESS The function completed successfully.\r | |
74 | \r | |
75 | @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r | |
76 | \r | |
77 | @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r | |
78 | time.\r | |
79 | \r | |
80 | **/\r | |
81 | typedef\r | |
82 | EFI_STATUS\r | |
83 | (EFIAPI *EFI_PEI_PCI_CFG_PPI_IO) (\r | |
00edb218 A |
84 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
85 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r | |
86 | IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
87 | IN CONST UINT64 Address,\r | |
5879b875 | 88 | IN OUT VOID *Buffer\r |
89 | );\r | |
90 | \r | |
91 | \r | |
92 | /**\r | |
93 | PCI read-modify-write operation.\r | |
94 | \r | |
95 | @param PeiServices An indirect pointer to the PEI Services Table \r | |
96 | published by the PEI Foundation.\r | |
97 | \r | |
98 | @param This Pointer to local data for the interface.\r | |
99 | \r | |
100 | @param Width The width of the access. Enumerated in bytes. Type\r | |
101 | EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r | |
102 | \r | |
103 | @param Address The physical address of the access.\r | |
104 | \r | |
105 | @param SetBits Points to value to bitwise-OR with the read configuration value. \r | |
106 | \r | |
107 | The size of the value is determined by Width.\r | |
108 | \r | |
109 | @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value. \r | |
110 | The size of the value is determined by Width.\r | |
111 | \r | |
112 | \r | |
113 | @retval EFI_SUCCESS The function completed successfully.\r | |
114 | \r | |
115 | @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r | |
116 | \r | |
117 | @retval EFI_DEVICE_NOT_READY The device is not capable of supporting \r | |
118 | the operation at this time.\r | |
119 | \r | |
120 | **/\r | |
121 | typedef\r | |
122 | EFI_STATUS\r | |
123 | (EFIAPI *EFI_PEI_PCI_CFG_PPI_RW) (\r | |
124 | IN CONST EFI_PEI_SERVICES **PeiServices,\r | |
125 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r | |
126 | IN CONST EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
127 | IN CONST UINT64 Address,\r | |
128 | IN CONST VOID *SetBits,\r | |
129 | IN CONST VOID *ClearBits\r | |
130 | );\r | |
131 | \r | |
132 | /**\r | |
133 | @par Ppi Description:\r | |
134 | The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI \r | |
135 | controllers behind a PCI root bridge controller.\r | |
136 | \r | |
137 | @param Read PCI read services. See the Read() function description.\r | |
138 | \r | |
139 | @param Write PCI write services. See the Write() function description.\r | |
140 | \r | |
141 | @param Modify PCI read-modify-write services. See the Modify() function description.\r | |
142 | \r | |
143 | @param Segment The PCI bus segment which the specified functions will access.\r | |
144 | \r | |
145 | **/\r | |
146 | struct _EFI_PEI_PCI_CFG2_PPI {\r | |
147 | EFI_PEI_PCI_CFG_PPI_IO Read;\r | |
148 | EFI_PEI_PCI_CFG_PPI_IO Write;\r | |
149 | EFI_PEI_PCI_CFG_PPI_RW Modify;\r | |
150 | UINT16 Segment;\r | |
151 | };\r | |
152 | \r | |
153 | \r | |
154 | extern EFI_GUID gEfiPciCfg2PpiGuid;\r | |
155 | \r | |
156 | #endif\r |