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5879b875 | 1 | /** @file\r |
d7132512 | 2 | This file declares PciCfg2 PPI.\r |
5879b875 | 3 | \r |
d7132512 LG |
4 | This ppi Provides platform or chipset-specific access to \r |
5 | the PCI configuration space for a specific PCI segment.\r | |
6 | \r | |
7 | Copyright (c) 2006 - 2008, Intel Corporation\r | |
845effb3 | 8 | All rights reserved. This program and the accompanying materials\r |
9 | are licensed and made available under the terms and conditions of the BSD License\r | |
10 | which accompanies this distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
5879b875 | 12 | \r |
845effb3 | 13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
14 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
5879b875 | 15 | \r |
5879b875 | 16 | @par Revision Reference:\r |
0047820e | 17 | This PPI is introduced in PI Version 1.0.\r |
5879b875 | 18 | \r |
19 | **/\r | |
20 | \r | |
21 | #ifndef __PEI_PCI_CFG2_H__\r | |
22 | #define __PEI_PCI_CFG2_H__\r | |
23 | \r | |
0c7f62f8 | 24 | #include <Pi/PiPeiCis.h>\r |
5879b875 | 25 | \r |
26 | #define EFI_PEI_PCI_CFG2_PPI_GUID \\r | |
27 | { 0x57a449a, 0x1fdc, 0x4c06, { 0xbf, 0xc9, 0xf5, 0x3f, 0x6a, 0x99, 0xbb, 0x92 } }\r | |
28 | \r | |
29 | \r | |
30 | typedef struct _EFI_PEI_PCI_CFG2_PPI EFI_PEI_PCI_CFG2_PPI;\r | |
31 | \r | |
32 | #define EFI_PEI_PCI_CFG_ADDRESS(bus,dev,func,reg) \\r | |
33 | (((bus) << 24) | \\r | |
34 | ((dev) << 16) | \\r | |
35 | ((func) << 8) | \\r | |
8b13229b | 36 | ((reg) < 256 ? (reg) : ((UINT64)(reg) << 32)));\r |
5879b875 | 37 | \r |
06889842 | 38 | ///\r |
39 | /// EFI_PEI_PCI_CFG_PPI_WIDTH\r | |
40 | ///\r | |
5879b875 | 41 | typedef enum {\r |
97c4afff | 42 | ///\r |
43 | /// 8-bit access\r | |
44 | ///\r | |
5879b875 | 45 | EfiPeiPciCfgWidthUint8 = 0,\r |
97c4afff | 46 | ///\r |
47 | /// 16-bit access\r | |
48 | ///\r | |
5879b875 | 49 | EfiPeiPciCfgWidthUint16 = 1,\r |
97c4afff | 50 | ///\r |
51 | /// 32-bit access\r | |
52 | ///\r | |
5879b875 | 53 | EfiPeiPciCfgWidthUint32 = 2,\r |
97c4afff | 54 | ///\r |
55 | /// 64-bit access\r | |
56 | ///\r | |
5879b875 | 57 | EfiPeiPciCfgWidthUint64 = 3,\r |
58 | EfiPeiPciCfgWidthMaximum\r | |
59 | } EFI_PEI_PCI_CFG_PPI_WIDTH;\r | |
60 | \r | |
06889842 | 61 | ///\r |
62 | /// EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS\r | |
63 | ///\r | |
5879b875 | 64 | typedef struct {\r |
11227adb | 65 | ///\r |
66 | /// 8-bit register offset within the PCI configuration space for a given device's function\r | |
67 | /// space.\r | |
68 | ///\r | |
5879b875 | 69 | UINT8 Register;\r |
11227adb | 70 | ///\r |
71 | /// Only the 3 least-significant bits are used to encode one of 8 possible functions within a\r | |
72 | /// given device.\r | |
73 | ///\r | |
5879b875 | 74 | UINT8 Function;\r |
11227adb | 75 | ///\r |
76 | /// Only the 5 least-significant bits are used to encode one of 32 possible devices.\r | |
77 | ///\r | |
5879b875 | 78 | UINT8 Device;\r |
11227adb | 79 | ///\r |
80 | /// 8-bit value to encode between 0 and 255 buses.\r | |
81 | ///\r | |
5879b875 | 82 | UINT8 Bus;\r |
11227adb | 83 | ///\r |
84 | /// Register number in PCI configuration space. If this field is zero, then Register is used\r | |
85 | /// for the register number. If this field is non-zero, then Register is ignored and this field\r | |
86 | /// is used for the register number.\r | |
87 | ///\r | |
5879b875 | 88 | UINT32 ExtendedRegister;\r |
89 | } EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS;\r | |
90 | \r | |
91 | /**\r | |
92 | Reads from or write to a given location in the PCI configuration space.\r | |
93 | \r | |
94 | @param PeiServices An indirect pointer to the PEI Services Table published by the PEI Foundation.\r | |
95 | \r | |
96 | @param This Pointer to local data for the interface.\r | |
97 | \r | |
845effb3 | 98 | @param Width The width of the access. Enumerated in bytes.\r |
5879b875 | 99 | See EFI_PEI_PCI_CFG_PPI_WIDTH above.\r |
100 | \r | |
845effb3 | 101 | @param Address The physical address of the access. The format of\r |
5879b875 | 102 | the address is described by EFI_PEI_PCI_CFG_PPI_PCI_ADDRESS.\r |
103 | \r | |
104 | @param Buffer A pointer to the buffer of data..\r | |
105 | \r | |
106 | \r | |
107 | @retval EFI_SUCCESS The function completed successfully.\r | |
108 | \r | |
109 | @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r | |
110 | \r | |
111 | @retval EFI_DEVICE_NOT_READY The device is not capable of supporting the operation at this\r | |
112 | time.\r | |
113 | \r | |
114 | **/\r | |
115 | typedef\r | |
116 | EFI_STATUS\r | |
8b13229b | 117 | (EFIAPI *EFI_PEI_PCI_CFG2_PPI_IO)(\r |
00edb218 A |
118 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
119 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r | |
ef4fa1a4 | 120 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r |
121 | IN UINT64 Address,\r | |
5879b875 | 122 | IN OUT VOID *Buffer\r |
123 | );\r | |
124 | \r | |
125 | \r | |
126 | /**\r | |
d7132512 LG |
127 | Performs a read-modify-write operation on the contents \r |
128 | from a given location in the PCI configuration space.\r | |
5879b875 | 129 | \r |
845effb3 | 130 | @param PeiServices An indirect pointer to the PEI Services Table\r |
5879b875 | 131 | published by the PEI Foundation.\r |
132 | \r | |
133 | @param This Pointer to local data for the interface.\r | |
134 | \r | |
135 | @param Width The width of the access. Enumerated in bytes. Type\r | |
136 | EFI_PEI_PCI_CFG_PPI_WIDTH is defined in Read().\r | |
137 | \r | |
138 | @param Address The physical address of the access.\r | |
139 | \r | |
845effb3 | 140 | @param SetBits Points to value to bitwise-OR with the read configuration value.\r |
5879b875 | 141 | \r |
142 | The size of the value is determined by Width.\r | |
143 | \r | |
845effb3 | 144 | @param ClearBits Points to the value to negate and bitwise-AND with the read configuration value.\r |
5879b875 | 145 | The size of the value is determined by Width.\r |
146 | \r | |
147 | \r | |
148 | @retval EFI_SUCCESS The function completed successfully.\r | |
149 | \r | |
150 | @retval EFI_DEVICE_ERROR There was a problem with the transaction.\r | |
151 | \r | |
845effb3 | 152 | @retval EFI_DEVICE_NOT_READY The device is not capable of supporting\r |
5879b875 | 153 | the operation at this time.\r |
154 | \r | |
155 | **/\r | |
156 | typedef\r | |
157 | EFI_STATUS\r | |
8b13229b | 158 | (EFIAPI *EFI_PEI_PCI_CFG2_PPI_RW)(\r |
5879b875 | 159 | IN CONST EFI_PEI_SERVICES **PeiServices,\r |
160 | IN CONST EFI_PEI_PCI_CFG2_PPI *This,\r | |
ef4fa1a4 | 161 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r |
162 | IN UINT64 Address,\r | |
11227adb | 163 | IN VOID *SetBits,\r |
164 | IN VOID *ClearBits\r | |
5879b875 | 165 | );\r |
166 | \r | |
44717a39 | 167 | ///\r |
168 | /// The EFI_PEI_PCI_CFG_PPI interfaces are used to abstract accesses to PCI\r | |
169 | /// controllers behind a PCI root bridge controller.\r | |
170 | ///\r | |
5879b875 | 171 | struct _EFI_PEI_PCI_CFG2_PPI {\r |
845effb3 | 172 | EFI_PEI_PCI_CFG2_PPI_IO Read;\r |
173 | EFI_PEI_PCI_CFG2_PPI_IO Write;\r | |
174 | EFI_PEI_PCI_CFG2_PPI_RW Modify;\r | |
44717a39 | 175 | ///\r |
176 | /// The PCI bus segment which the specified functions will access.\r | |
177 | ///\r | |
5879b875 | 178 | UINT16 Segment;\r |
179 | };\r | |
180 | \r | |
181 | \r | |
182 | extern EFI_GUID gEfiPciCfg2PpiGuid;\r | |
183 | \r | |
184 | #endif\r |