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1 | /** @file\r |
2 | This file defines the Legacy SPI Controller Protocol.\r | |
3 | \r | |
4 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
db04b706 MH |
6 | \r |
7 | @par Revision Reference:\r | |
8 | This Protocol was introduced in UEFI PI Specification 1.6.\r | |
9 | \r | |
10 | **/\r | |
11 | \r | |
12 | #ifndef __LEGACY_SPI_CONTROLLER_PROTOCOL_H__\r | |
13 | #define __LEGACY_SPI_CONTROLLER_PROTOCOL_H__\r | |
14 | \r | |
15 | ///\r | |
16 | /// Note: The UEFI PI 1.6 specification uses the character 'l' in the GUID\r | |
17 | /// definition. This definition assumes it was supposed to be '1'.\r | |
18 | ///\r | |
19 | /// Global ID for the Legacy SPI Controller Protocol\r | |
20 | ///\r | |
21 | #define EFI_LEGACY_SPI_CONTROLLER_GUID \\r | |
22 | { 0x39136fc7, 0x1a11, 0x49de, \\r | |
23 | { 0xbf, 0x35, 0x0e, 0x78, 0xdd, 0xb5, 0x24, 0xfc }}\r | |
24 | \r | |
25 | typedef\r | |
2f88bd3a | 26 | struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r |
db04b706 MH |
27 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL;\r |
28 | \r | |
29 | /**\r | |
30 | Set the erase block opcode.\r | |
31 | \r | |
32 | This routine must be called at or below TPL_NOTIFY.\r | |
33 | The menu table contains SPI transaction opcodes which are accessible after\r | |
34 | the legacy SPI flash controller's configuration is locked. The board layer\r | |
35 | specifies the erase block size for the SPI NOR flash part. The SPI NOR flash\r | |
36 | peripheral driver selects the erase block opcode which matches the erase\r | |
37 | block size and uses this API to load the opcode into the opcode menu table.\r | |
38 | \r | |
39 | @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r | |
40 | structure.\r | |
41 | @param[in] EraseBlockOpcode Erase block opcode to be placed into the opcode\r | |
42 | menu table.\r | |
43 | \r | |
44 | @retval EFI_SUCCESS The opcode menu table was updated\r | |
45 | @retval EFI_ACCESS_ERROR The SPI controller is locked\r | |
46 | \r | |
47 | **/\r | |
48 | typedef EFI_STATUS\r | |
2f88bd3a | 49 | (EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE)(\r |
db04b706 MH |
50 | IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r |
51 | IN UINT8 EraseBlockOpcode\r | |
52 | );\r | |
53 | \r | |
54 | /**\r | |
55 | Set the write status prefix opcode.\r | |
56 | \r | |
57 | This routine must be called at or below TPL_NOTIFY.\r | |
58 | The prefix table contains SPI transaction write prefix opcodes which are\r | |
59 | accessible after the legacy SPI flash controller's configuration is locked.\r | |
60 | The board layer specifies the write status prefix opcode for the SPI NOR\r | |
61 | flash part. The SPI NOR flash peripheral driver uses this API to load the\r | |
62 | opcode into the prefix table.\r | |
63 | \r | |
64 | @param[in] This Pointer to an\r | |
65 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.\r | |
66 | @param[in] WriteStatusPrefix Prefix opcode for the write status command.\r | |
67 | \r | |
68 | @retval EFI_SUCCESS The prefix table was updated\r | |
69 | @retval EFI_ACCESS_ERROR The SPI controller is locked\r | |
70 | \r | |
71 | **/\r | |
72 | typedef\r | |
73 | EFI_STATUS\r | |
2f88bd3a | 74 | (EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX)(\r |
db04b706 MH |
75 | IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r |
76 | IN UINT8 WriteStatusPrefix\r | |
77 | );\r | |
78 | \r | |
79 | /**\r | |
80 | Set the BIOS base address.\r | |
81 | \r | |
82 | This routine must be called at or below TPL_NOTIFY.\r | |
83 | The BIOS base address works with the protect range registers to protect\r | |
84 | portions of the SPI NOR flash from erase and write operat ions. The BIOS\r | |
85 | calls this API prior to passing control to the OS loader.\r | |
86 | \r | |
87 | @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r | |
88 | structure.\r | |
89 | @param[in] BiosBaseAddress The BIOS base address.\r | |
90 | \r | |
91 | @retval EFI_SUCCESS The BIOS base address was properly set\r | |
92 | @retval EFI_ACCESS_ERROR The SPI controller is locked\r | |
93 | @retval EFI_INVALID_PARAMETER The BIOS base address is greater than\r | |
94 | This->Maxi.mumOffset\r | |
95 | @retval EFI_UNSUPPORTED The BIOS base address was already set\r | |
96 | \r | |
97 | **/\r | |
98 | typedef EFI_STATUS\r | |
2f88bd3a | 99 | (EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS)(\r |
db04b706 MH |
100 | IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r |
101 | IN UINT32 BiosBaseAddress\r | |
102 | );\r | |
103 | \r | |
104 | /**\r | |
105 | Clear the SPI protect range registers.\r | |
106 | \r | |
107 | This routine must be called at or below TPL_NOTIFY.\r | |
108 | The BIOS uses this routine to set an initial condition on the SPI protect\r | |
109 | range registers.\r | |
110 | \r | |
111 | @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.\r | |
112 | \r | |
113 | @retval EFI_SUCCESS The registers were successfully cleared\r | |
114 | @retval EFI_ACCESS_ERROR The SPI controller is locked\r | |
115 | \r | |
116 | **/\r | |
117 | typedef\r | |
118 | EFI_STATUS\r | |
2f88bd3a | 119 | (EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT)(\r |
db04b706 MH |
120 | IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This\r |
121 | );\r | |
122 | \r | |
123 | /**\r | |
124 | Determine if the SPI range is protected.\r | |
125 | \r | |
126 | This routine must be called at or below TPL_NOTIFY.\r | |
127 | The BIOS uses this routine to verify a range in the SPI is protected.\r | |
128 | \r | |
129 | @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r | |
130 | structure.\r | |
131 | @param[in] BiosAddress Address within a 4 KiB block to start protecting.\r | |
132 | @param[in] BytesToProtect The number of 4 KiB blocks to protect.\r | |
133 | \r | |
134 | @retval TRUE The range is protected\r | |
135 | @retval FALSE The range is not protected\r | |
136 | \r | |
137 | **/\r | |
138 | typedef\r | |
139 | BOOLEAN\r | |
2f88bd3a | 140 | (EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED)(\r |
db04b706 MH |
141 | IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r |
142 | IN UINT32 BiosAddress,\r | |
143 | IN UINT32 BlocksToProtect\r | |
144 | );\r | |
145 | \r | |
146 | /**\r | |
147 | Set the next protect range register.\r | |
148 | \r | |
149 | This routine must be called at or below TPL_NOTIFY.\r | |
150 | The BIOS sets the protect range register to prevent write and erase\r | |
151 | operations to a portion of the SPI NOR flash device.\r | |
152 | \r | |
153 | @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL\r | |
154 | structure.\r | |
155 | @param[in] BiosAddress Address within a 4 KiB block to start protecting.\r | |
156 | @param[in] BlocksToProtect The number of 4 KiB blocks to protect.\r | |
157 | \r | |
158 | @retval EFI_SUCCESS The register was successfully updated\r | |
159 | @retval EFI_ACCESS_ERROR The SPI controller is locked\r | |
160 | @retval EFI_INVALID_PARAMETER BiosAddress < This->BiosBaseAddress, or\r | |
161 | BlocksToProtect * 4 KiB\r | |
162 | > This->MaximumRangeBytes, or\r | |
163 | BiosAddress - This->BiosBaseAddress\r | |
164 | + (BlocksToProtect * 4 KiB)\r | |
165 | > This->MaximumRangeBytes\r | |
166 | @retval EFI_OUT_OF_RESOURCES No protect range register available\r | |
167 | @retval EFI_UNSUPPORTED Call This->SetBaseAddress because the BIOS base\r | |
168 | address is not set\r | |
169 | \r | |
170 | **/\r | |
171 | typedef\r | |
172 | EFI_STATUS\r | |
2f88bd3a | 173 | (EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE)(\r |
db04b706 MH |
174 | IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This,\r |
175 | IN UINT32 BiosAddress,\r | |
176 | IN UINT32 BlocksToProtect\r | |
177 | );\r | |
178 | \r | |
179 | /**\r | |
180 | Lock the SPI controller configuration.\r | |
181 | \r | |
182 | This routine must be called at or below TPL_NOTIFY.\r | |
183 | This routine locks the SPI controller's configuration so that the software\r | |
184 | is no longer able to update:\r | |
185 | * Prefix table\r | |
186 | * Opcode menu\r | |
187 | * Opcode type table\r | |
188 | * BIOS base address\r | |
189 | * Protect range registers\r | |
190 | \r | |
191 | @param[in] This Pointer to an EFI_LEGACY_SPI_CONTROLLER_PROTOCOL structure.\r | |
192 | \r | |
193 | @retval EFI_SUCCESS The SPI controller was successfully locked\r | |
194 | @retval EFI_ALREADY_STARTED The SPI controller was already locked\r | |
195 | \r | |
196 | **/\r | |
197 | typedef EFI_STATUS\r | |
2f88bd3a | 198 | (EFIAPI *EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER)(\r |
db04b706 MH |
199 | IN CONST EFI_LEGACY_SPI_CONTROLLER_PROTOCOL *This\r |
200 | );\r | |
201 | \r | |
202 | ///\r | |
203 | /// Support the extra features of the legacy SPI flash controller.\r | |
204 | ///\r | |
205 | struct _EFI_LEGACY_SPI_CONTROLLER_PROTOCOL {\r | |
206 | ///\r | |
207 | /// Maximum offset from the BIOS base address that is able to be protected.\r | |
208 | ///\r | |
2f88bd3a | 209 | UINT32 MaximumOffset;\r |
db04b706 MH |
210 | \r |
211 | ///\r | |
212 | /// Maximum number of bytes that can be protected by one range register.\r | |
213 | ///\r | |
2f88bd3a | 214 | UINT32 MaximumRangeBytes;\r |
db04b706 MH |
215 | \r |
216 | ///\r | |
217 | /// The number of registers available for protecting the BIOS.\r | |
218 | ///\r | |
2f88bd3a | 219 | UINT32 RangeRegisterCount;\r |
db04b706 MH |
220 | \r |
221 | ///\r | |
222 | /// Set the erase block opcode.\r | |
223 | ///\r | |
2f88bd3a | 224 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_ERASE_BLOCK_OPCODE EraseBlockOpcode;\r |
db04b706 MH |
225 | \r |
226 | ///\r | |
227 | /// Set the write status prefix opcode.\r | |
228 | ///\r | |
2f88bd3a | 229 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_WRITE_STATUS_PREFIX WriteStatusPrefix;\r |
db04b706 MH |
230 | \r |
231 | ///\r | |
232 | /// Set the BIOS base address.\r | |
233 | ///\r | |
2f88bd3a | 234 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_BIOS_BASE_ADDRESS BiosBaseAddress;\r |
db04b706 MH |
235 | \r |
236 | ///\r | |
237 | /// Clear the SPI protect range registers.\r | |
238 | ///\r | |
2f88bd3a | 239 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_CLEAR_SPI_PROTECT ClearSpiProtect;\r |
db04b706 MH |
240 | \r |
241 | ///\r | |
242 | /// Determine if the SPI range is protected.\r | |
243 | ///\r | |
2f88bd3a | 244 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_IS_RANGE_PROTECTED IsRangeProtected;\r |
db04b706 MH |
245 | \r |
246 | ///\r | |
247 | /// Set the next protect range register.\r | |
248 | ///\r | |
2f88bd3a | 249 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_PROTECT_NEXT_RANGE ProtectNextRange;\r |
db04b706 MH |
250 | \r |
251 | ///\r | |
252 | /// Lock the SPI controller configuration.\r | |
253 | ///\r | |
2f88bd3a | 254 | EFI_LEGACY_SPI_CONTROLLER_PROTOCOL_LOCK_CONTROLLER LockController;\r |
db04b706 MH |
255 | };\r |
256 | \r | |
2f88bd3a | 257 | extern EFI_GUID gEfiLegacySpiControllerProtocolGuid;\r |
db04b706 MH |
258 | \r |
259 | #endif // __LEGACY_SPI_CONTROLLER_PROTOCOL_H__\r |