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07c6a47e ED |
1 | /** @file\r |
2 | EFI MM CPU Protocol as defined in the PI 1.5 specification.\r | |
3 | \r | |
4 | This protocol allows MM drivers to access architecture-standard registers from any of the CPU\r | |
5 | save state areas. In some cases, difference processors provide the same information in the save state,\r | |
6 | but not in the same format. These so-called pseudo-registers provide this information in a standard\r | |
7 | format.\r | |
8 | \r | |
9 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
9344f092 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
07c6a47e ED |
11 | \r |
12 | **/\r | |
13 | \r | |
14 | #ifndef _MM_CPU_H_\r | |
15 | #define _MM_CPU_H_\r | |
16 | \r | |
17 | #define EFI_MM_CPU_PROTOCOL_GUID \\r | |
18 | { \\r | |
19 | 0xeb346b97, 0x975f, 0x4a9f, { 0x8b, 0x22, 0xf8, 0xe9, 0x2b, 0xb3, 0xd5, 0x69 } \\r | |
20 | }\r | |
21 | \r | |
22 | ///\r | |
23 | /// Save State register index\r | |
24 | ///\r | |
25 | typedef enum {\r | |
26 | ///\r | |
27 | /// x86/X64 standard registers\r | |
28 | ///\r | |
2f88bd3a MK |
29 | EFI_MM_SAVE_STATE_REGISTER_GDTBASE = 4,\r |
30 | EFI_MM_SAVE_STATE_REGISTER_IDTBASE = 5,\r | |
31 | EFI_MM_SAVE_STATE_REGISTER_LDTBASE = 6,\r | |
32 | EFI_MM_SAVE_STATE_REGISTER_GDTLIMIT = 7,\r | |
33 | EFI_MM_SAVE_STATE_REGISTER_IDTLIMIT = 8,\r | |
34 | EFI_MM_SAVE_STATE_REGISTER_LDTLIMIT = 9,\r | |
35 | EFI_MM_SAVE_STATE_REGISTER_LDTINFO = 10,\r | |
36 | EFI_MM_SAVE_STATE_REGISTER_ES = 20,\r | |
37 | EFI_MM_SAVE_STATE_REGISTER_CS = 21,\r | |
38 | EFI_MM_SAVE_STATE_REGISTER_SS = 22,\r | |
39 | EFI_MM_SAVE_STATE_REGISTER_DS = 23,\r | |
40 | EFI_MM_SAVE_STATE_REGISTER_FS = 24,\r | |
41 | EFI_MM_SAVE_STATE_REGISTER_GS = 25,\r | |
42 | EFI_MM_SAVE_STATE_REGISTER_LDTR_SEL = 26,\r | |
43 | EFI_MM_SAVE_STATE_REGISTER_TR_SEL = 27,\r | |
44 | EFI_MM_SAVE_STATE_REGISTER_DR7 = 28,\r | |
45 | EFI_MM_SAVE_STATE_REGISTER_DR6 = 29,\r | |
46 | EFI_MM_SAVE_STATE_REGISTER_R8 = 30,\r | |
47 | EFI_MM_SAVE_STATE_REGISTER_R9 = 31,\r | |
48 | EFI_MM_SAVE_STATE_REGISTER_R10 = 32,\r | |
49 | EFI_MM_SAVE_STATE_REGISTER_R11 = 33,\r | |
50 | EFI_MM_SAVE_STATE_REGISTER_R12 = 34,\r | |
51 | EFI_MM_SAVE_STATE_REGISTER_R13 = 35,\r | |
52 | EFI_MM_SAVE_STATE_REGISTER_R14 = 36,\r | |
53 | EFI_MM_SAVE_STATE_REGISTER_R15 = 37,\r | |
54 | EFI_MM_SAVE_STATE_REGISTER_RAX = 38,\r | |
55 | EFI_MM_SAVE_STATE_REGISTER_RBX = 39,\r | |
56 | EFI_MM_SAVE_STATE_REGISTER_RCX = 40,\r | |
57 | EFI_MM_SAVE_STATE_REGISTER_RDX = 41,\r | |
58 | EFI_MM_SAVE_STATE_REGISTER_RSP = 42,\r | |
59 | EFI_MM_SAVE_STATE_REGISTER_RBP = 43,\r | |
60 | EFI_MM_SAVE_STATE_REGISTER_RSI = 44,\r | |
61 | EFI_MM_SAVE_STATE_REGISTER_RDI = 45,\r | |
62 | EFI_MM_SAVE_STATE_REGISTER_RIP = 46,\r | |
63 | EFI_MM_SAVE_STATE_REGISTER_RFLAGS = 51,\r | |
64 | EFI_MM_SAVE_STATE_REGISTER_CR0 = 52,\r | |
65 | EFI_MM_SAVE_STATE_REGISTER_CR3 = 53,\r | |
66 | EFI_MM_SAVE_STATE_REGISTER_CR4 = 54,\r | |
67 | EFI_MM_SAVE_STATE_REGISTER_FCW = 256,\r | |
68 | EFI_MM_SAVE_STATE_REGISTER_FSW = 257,\r | |
69 | EFI_MM_SAVE_STATE_REGISTER_FTW = 258,\r | |
70 | EFI_MM_SAVE_STATE_REGISTER_OPCODE = 259,\r | |
71 | EFI_MM_SAVE_STATE_REGISTER_FP_EIP = 260,\r | |
72 | EFI_MM_SAVE_STATE_REGISTER_FP_CS = 261,\r | |
73 | EFI_MM_SAVE_STATE_REGISTER_DATAOFFSET = 262,\r | |
74 | EFI_MM_SAVE_STATE_REGISTER_FP_DS = 263,\r | |
75 | EFI_MM_SAVE_STATE_REGISTER_MM0 = 264,\r | |
76 | EFI_MM_SAVE_STATE_REGISTER_MM1 = 265,\r | |
77 | EFI_MM_SAVE_STATE_REGISTER_MM2 = 266,\r | |
78 | EFI_MM_SAVE_STATE_REGISTER_MM3 = 267,\r | |
79 | EFI_MM_SAVE_STATE_REGISTER_MM4 = 268,\r | |
80 | EFI_MM_SAVE_STATE_REGISTER_MM5 = 269,\r | |
81 | EFI_MM_SAVE_STATE_REGISTER_MM6 = 270,\r | |
82 | EFI_MM_SAVE_STATE_REGISTER_MM7 = 271,\r | |
83 | EFI_MM_SAVE_STATE_REGISTER_XMM0 = 272,\r | |
84 | EFI_MM_SAVE_STATE_REGISTER_XMM1 = 273,\r | |
85 | EFI_MM_SAVE_STATE_REGISTER_XMM2 = 274,\r | |
86 | EFI_MM_SAVE_STATE_REGISTER_XMM3 = 275,\r | |
87 | EFI_MM_SAVE_STATE_REGISTER_XMM4 = 276,\r | |
88 | EFI_MM_SAVE_STATE_REGISTER_XMM5 = 277,\r | |
89 | EFI_MM_SAVE_STATE_REGISTER_XMM6 = 278,\r | |
90 | EFI_MM_SAVE_STATE_REGISTER_XMM7 = 279,\r | |
91 | EFI_MM_SAVE_STATE_REGISTER_XMM8 = 280,\r | |
92 | EFI_MM_SAVE_STATE_REGISTER_XMM9 = 281,\r | |
93 | EFI_MM_SAVE_STATE_REGISTER_XMM10 = 282,\r | |
94 | EFI_MM_SAVE_STATE_REGISTER_XMM11 = 283,\r | |
95 | EFI_MM_SAVE_STATE_REGISTER_XMM12 = 284,\r | |
96 | EFI_MM_SAVE_STATE_REGISTER_XMM13 = 285,\r | |
97 | EFI_MM_SAVE_STATE_REGISTER_XMM14 = 286,\r | |
98 | EFI_MM_SAVE_STATE_REGISTER_XMM15 = 287,\r | |
07c6a47e ED |
99 | ///\r |
100 | /// Pseudo-Registers\r | |
101 | ///\r | |
2f88bd3a MK |
102 | EFI_MM_SAVE_STATE_REGISTER_IO = 512,\r |
103 | EFI_MM_SAVE_STATE_REGISTER_LMA = 513,\r | |
104 | EFI_MM_SAVE_STATE_REGISTER_PROCESSOR_ID = 514\r | |
07c6a47e ED |
105 | } EFI_MM_SAVE_STATE_REGISTER;\r |
106 | \r | |
107 | ///\r | |
108 | /// The EFI_MM_SAVE_STATE_REGISTER_LMA pseudo-register values\r | |
109 | /// If the processor acts in 32-bit mode at the time the MMI occurred, the pseudo register value\r | |
110 | /// EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT is returned in Buffer. Otherwise,\r | |
111 | /// EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT is returned in Buffer.\r | |
112 | ///\r | |
113 | #define EFI_MM_SAVE_STATE_REGISTER_LMA_32BIT 32\r | |
114 | #define EFI_MM_SAVE_STATE_REGISTER_LMA_64BIT 64\r | |
115 | \r | |
116 | ///\r | |
117 | /// Size width of I/O instruction\r | |
118 | ///\r | |
119 | typedef enum {\r | |
2f88bd3a MK |
120 | EFI_MM_SAVE_STATE_IO_WIDTH_UINT8 = 0,\r |
121 | EFI_MM_SAVE_STATE_IO_WIDTH_UINT16 = 1,\r | |
122 | EFI_MM_SAVE_STATE_IO_WIDTH_UINT32 = 2,\r | |
123 | EFI_MM_SAVE_STATE_IO_WIDTH_UINT64 = 3\r | |
07c6a47e ED |
124 | } EFI_MM_SAVE_STATE_IO_WIDTH;\r |
125 | \r | |
126 | ///\r | |
127 | /// Types of I/O instruction\r | |
128 | ///\r | |
129 | typedef enum {\r | |
2f88bd3a MK |
130 | EFI_MM_SAVE_STATE_IO_TYPE_INPUT = 1,\r |
131 | EFI_MM_SAVE_STATE_IO_TYPE_OUTPUT = 2,\r | |
132 | EFI_MM_SAVE_STATE_IO_TYPE_STRING = 4,\r | |
133 | EFI_MM_SAVE_STATE_IO_TYPE_REP_PREFIX = 8\r | |
07c6a47e ED |
134 | } EFI_MM_SAVE_STATE_IO_TYPE;\r |
135 | \r | |
136 | ///\r | |
137 | /// Structure of the data which is returned when ReadSaveState() is called with\r | |
138 | /// EFI_MM_SAVE_STATE_REGISTER_IO. If there was no I/O then ReadSaveState() will\r | |
139 | /// return EFI_NOT_FOUND.\r | |
140 | ///\r | |
141 | /// This structure describes the I/O operation which was in process when the MMI was generated.\r | |
142 | ///\r | |
143 | typedef struct _EFI_MM_SAVE_STATE_IO_INFO {\r | |
144 | ///\r | |
145 | /// For input instruction (IN, INS), this is data read before the MMI occurred. For output\r | |
146 | /// instructions (OUT, OUTS) this is data that was written before the MMI occurred. The\r | |
147 | /// width of the data is specified by IoWidth.\r | |
148 | ///\r | |
149 | UINT64 IoData;\r | |
150 | ///\r | |
151 | /// The I/O port that was being accessed when the MMI was triggered.\r | |
152 | ///\r | |
153 | UINT16 IoPort;\r | |
154 | ///\r | |
155 | /// Defines the size width (UINT8, UINT16, UINT32, UINT64) for IoData.\r | |
156 | ///\r | |
157 | EFI_MM_SAVE_STATE_IO_WIDTH IoWidth;\r | |
158 | ///\r | |
159 | /// Defines type of I/O instruction.\r | |
160 | ///\r | |
161 | EFI_MM_SAVE_STATE_IO_TYPE IoType;\r | |
162 | } EFI_MM_SAVE_STATE_IO_INFO;\r | |
163 | \r | |
2f88bd3a | 164 | typedef struct _EFI_MM_CPU_PROTOCOL EFI_MM_CPU_PROTOCOL;\r |
07c6a47e ED |
165 | \r |
166 | /**\r | |
167 | Read data from the CPU save state.\r | |
168 | \r | |
169 | This function is used to read the specified number of bytes of the specified register from the CPU\r | |
170 | save state of the specified CPU and place the value into the buffer. If the CPU does not support the\r | |
171 | specified register Register, then EFI_NOT_FOUND should be returned. If the CPU does not\r | |
172 | support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r | |
173 | \r | |
174 | @param[in] This The EFI_MM_CPU_PROTOCOL instance.\r | |
175 | @param[in] Width The number of bytes to read from the CPU save state.\r | |
176 | @param[in] Register Specifies the CPU register to read form the save state.\r | |
177 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
178 | @param[out] Buffer Upon return, this holds the CPU register value read from the save state.\r | |
179 | \r | |
180 | @retval EFI_SUCCESS The register was read from Save State.\r | |
181 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
182 | @retval EFI_INVALID_PARAMETER Input parameters are not valid, for example, Processor No or register width\r | |
183 | is not correct.This or Buffer is NULL.\r | |
184 | **/\r | |
185 | typedef\r | |
186 | EFI_STATUS\r | |
187 | (EFIAPI *EFI_MM_READ_SAVE_STATE)(\r | |
188 | IN CONST EFI_MM_CPU_PROTOCOL *This,\r | |
189 | IN UINTN Width,\r | |
190 | IN EFI_MM_SAVE_STATE_REGISTER Register,\r | |
191 | IN UINTN CpuIndex,\r | |
192 | OUT VOID *Buffer\r | |
193 | );\r | |
194 | \r | |
07c6a47e ED |
195 | /**\r |
196 | Write data to the CPU save state.\r | |
197 | \r | |
198 | This function is used to write the specified number of bytes of the specified register to the CPU save\r | |
199 | state of the specified CPU and place the value into the buffer. If the CPU does not support the\r | |
200 | specified register Register, then EFI_UNSUPPORTED should be returned. If the CPU does not\r | |
201 | support the specified register width Width, then EFI_INVALID_PARAMETER is returned.\r | |
202 | \r | |
203 | @param[in] This The EFI_MM_CPU_PROTOCOL instance.\r | |
204 | @param[in] Width The number of bytes to write to the CPU save state.\r | |
205 | @param[in] Register Specifies the CPU register to write to the save state.\r | |
206 | @param[in] CpuIndex Specifies the zero-based index of the CPU save state.\r | |
207 | @param[in] Buffer Upon entry, this holds the new CPU register value.\r | |
208 | \r | |
209 | @retval EFI_SUCCESS The register was written to Save State.\r | |
210 | @retval EFI_NOT_FOUND The register is not defined for the Save State of Processor.\r | |
211 | @retval EFI_INVALID_PARAMETER Input parameters are not valid. For example:\r | |
212 | ProcessorIndex or Width is not correct.\r | |
213 | **/\r | |
214 | typedef\r | |
215 | EFI_STATUS\r | |
216 | (EFIAPI *EFI_MM_WRITE_SAVE_STATE)(\r | |
217 | IN CONST EFI_MM_CPU_PROTOCOL *This,\r | |
218 | IN UINTN Width,\r | |
219 | IN EFI_MM_SAVE_STATE_REGISTER Register,\r | |
220 | IN UINTN CpuIndex,\r | |
221 | IN CONST VOID *Buffer\r | |
222 | );\r | |
223 | \r | |
224 | ///\r | |
225 | /// EFI MM CPU Protocol provides access to CPU-related information while in MM.\r | |
226 | ///\r | |
227 | /// This protocol allows MM drivers to access architecture-standard registers from any of the CPU\r | |
228 | /// save state areas. In some cases, difference processors provide the same information in the save state,\r | |
229 | /// but not in the same format. These so-called pseudo-registers provide this information in a standard\r | |
230 | /// format.\r | |
231 | ///\r | |
232 | struct _EFI_MM_CPU_PROTOCOL {\r | |
2f88bd3a MK |
233 | EFI_MM_READ_SAVE_STATE ReadSaveState;\r |
234 | EFI_MM_WRITE_SAVE_STATE WriteSaveState;\r | |
07c6a47e ED |
235 | };\r |
236 | \r | |
2f88bd3a | 237 | extern EFI_GUID gEfiMmCpuProtocolGuid;\r |
07c6a47e ED |
238 | \r |
239 | #endif\r |