]>
Commit | Line | Data |
---|---|---|
6bfbb5f0 | 1 | ## @file\r |
34b0820e | 2 | # Base Library implementation.\r |
85ea851e | 3 | #\r |
bb817c56 HT |
4 | # Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>\r |
5 | # Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
807e2604 | 6 | # Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r |
e1f414b6 | 7 | #\r |
bb817c56 | 8 | # This program and the accompanying materials\r |
e1f414b6 | 9 | # are licensed and made available under the terms and conditions of the BSD License\r |
10 | # which accompanies this distribution. The full text of the license may be found at\r | |
127010dd | 11 | # http://opensource.org/licenses/bsd-license.php.\r |
e1f414b6 | 12 | # THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
13 | # WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | #\r | |
15 | #\r | |
6bfbb5f0 | 16 | ##\r |
e1f414b6 | 17 | \r |
e1f414b6 | 18 | [Defines]\r |
19 | INF_VERSION = 0x00010005\r | |
20 | BASE_NAME = BaseLib\r | |
21 | FILE_GUID = 27d67720-ea68-48ae-93da-a3a074c90e30\r | |
22 | MODULE_TYPE = BASE\r | |
23 | VERSION_STRING = 1.0\r | |
24 | LIBRARY_CLASS = BaseLib \r | |
e1f414b6 | 25 | \r |
e1f414b6 | 26 | #\r |
807e2604 | 27 | # VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64\r |
e1f414b6 | 28 | #\r |
29 | \r | |
6bfbb5f0 | 30 | [Sources]\r |
e1f414b6 | 31 | CheckSum.c\r |
32 | SwitchStack.c\r | |
33 | SwapBytes64.c\r | |
34 | SwapBytes32.c\r | |
35 | SwapBytes16.c\r | |
36 | LongJump.c\r | |
37 | SetJump.c\r | |
38 | RShiftU64.c\r | |
39 | RRotU64.c\r | |
40 | RRotU32.c\r | |
41 | MultU64x64.c\r | |
42 | MultU64x32.c\r | |
43 | MultS64x64.c\r | |
44 | ModU64x32.c\r | |
45 | LShiftU64.c\r | |
46 | LRotU64.c\r | |
47 | LRotU32.c\r | |
48 | LowBitSet64.c\r | |
49 | LowBitSet32.c\r | |
50 | HighBitSet64.c\r | |
51 | HighBitSet32.c\r | |
52 | GetPowerOfTwo64.c\r | |
53 | GetPowerOfTwo32.c\r | |
54 | DivU64x64Remainder.c\r | |
55 | DivU64x32Remainder.c\r | |
56 | DivU64x32.c\r | |
57 | DivS64x64Remainder.c\r | |
58 | ARShiftU64.c\r | |
59 | BitField.c\r | |
60 | CpuDeadLoop.c\r | |
61 | Cpu.c\r | |
62 | LinkedList.c\r | |
63 | String.c\r | |
64 | BaseLibInternals.h\r | |
e1f414b6 | 65 | \r |
66 | [Sources.Ia32]\r | |
6b4fe92a | 67 | Ia32/Wbinvd.c | MSFT \r |
68 | Ia32/WriteMm7.c | MSFT \r | |
69 | Ia32/WriteMm6.c | MSFT \r | |
70 | Ia32/WriteMm5.c | MSFT \r | |
71 | Ia32/WriteMm4.c | MSFT \r | |
72 | Ia32/WriteMm3.c | MSFT \r | |
73 | Ia32/WriteMm2.c | MSFT \r | |
74 | Ia32/WriteMm1.c | MSFT \r | |
75 | Ia32/WriteMm0.c | MSFT \r | |
76 | Ia32/WriteLdtr.c | MSFT \r | |
77 | Ia32/WriteIdtr.c | MSFT \r | |
78 | Ia32/WriteGdtr.c | MSFT \r | |
79 | Ia32/WriteDr7.c | MSFT \r | |
80 | Ia32/WriteDr6.c | MSFT \r | |
81 | Ia32/WriteDr5.c | MSFT \r | |
82 | Ia32/WriteDr4.c | MSFT \r | |
83 | Ia32/WriteDr3.c | MSFT \r | |
84 | Ia32/WriteDr2.c | MSFT \r | |
85 | Ia32/WriteDr1.c | MSFT \r | |
86 | Ia32/WriteDr0.c | MSFT \r | |
87 | Ia32/WriteCr4.c | MSFT \r | |
88 | Ia32/WriteCr3.c | MSFT \r | |
89 | Ia32/WriteCr2.c | MSFT \r | |
90 | Ia32/WriteCr0.c | MSFT \r | |
91 | Ia32/WriteMsr64.c | MSFT \r | |
6b4fe92a | 92 | Ia32/SwapBytes64.c | MSFT \r |
93 | Ia32/SetJump.c | MSFT \r | |
94 | Ia32/RRotU64.c | MSFT \r | |
95 | Ia32/RShiftU64.c | MSFT \r | |
96 | Ia32/ReadPmc.c | MSFT \r | |
97 | Ia32/ReadTsc.c | MSFT \r | |
98 | Ia32/ReadLdtr.c | MSFT \r | |
99 | Ia32/ReadIdtr.c | MSFT \r | |
100 | Ia32/ReadGdtr.c | MSFT \r | |
101 | Ia32/ReadTr.c | MSFT \r | |
102 | Ia32/ReadSs.c | MSFT \r | |
103 | Ia32/ReadGs.c | MSFT \r | |
104 | Ia32/ReadFs.c | MSFT \r | |
105 | Ia32/ReadEs.c | MSFT \r | |
106 | Ia32/ReadDs.c | MSFT \r | |
107 | Ia32/ReadCs.c | MSFT \r | |
108 | Ia32/ReadMsr64.c | MSFT \r | |
109 | Ia32/ReadMm7.c | MSFT \r | |
110 | Ia32/ReadMm6.c | MSFT \r | |
111 | Ia32/ReadMm5.c | MSFT \r | |
112 | Ia32/ReadMm4.c | MSFT \r | |
113 | Ia32/ReadMm3.c | MSFT \r | |
114 | Ia32/ReadMm2.c | MSFT \r | |
115 | Ia32/ReadMm1.c | MSFT \r | |
116 | Ia32/ReadMm0.c | MSFT \r | |
117 | Ia32/ReadEflags.c | MSFT \r | |
118 | Ia32/ReadDr7.c | MSFT \r | |
119 | Ia32/ReadDr6.c | MSFT \r | |
120 | Ia32/ReadDr5.c | MSFT \r | |
121 | Ia32/ReadDr4.c | MSFT \r | |
122 | Ia32/ReadDr3.c | MSFT \r | |
123 | Ia32/ReadDr2.c | MSFT \r | |
124 | Ia32/ReadDr1.c | MSFT \r | |
125 | Ia32/ReadDr0.c | MSFT \r | |
126 | Ia32/ReadCr4.c | MSFT \r | |
127 | Ia32/ReadCr3.c | MSFT \r | |
128 | Ia32/ReadCr2.c | MSFT \r | |
129 | Ia32/ReadCr0.c | MSFT \r | |
130 | Ia32/Mwait.c | MSFT \r | |
131 | Ia32/Monitor.c | MSFT \r | |
132 | Ia32/ModU64x32.c | MSFT \r | |
133 | Ia32/MultU64x64.c | MSFT \r | |
134 | Ia32/MultU64x32.c | MSFT \r | |
135 | Ia32/LShiftU64.c | MSFT \r | |
136 | Ia32/LRotU64.c | MSFT \r | |
137 | Ia32/LongJump.c | MSFT \r | |
138 | Ia32/Invd.c | MSFT \r | |
6b4fe92a | 139 | Ia32/FxRestore.c | MSFT \r |
140 | Ia32/FxSave.c | MSFT \r | |
141 | Ia32/FlushCacheLine.c | MSFT \r | |
6b4fe92a | 142 | Ia32/EnablePaging32.c | MSFT \r |
143 | Ia32/EnableInterrupts.c | MSFT \r | |
144 | Ia32/EnableDisableInterrupts.c | MSFT \r | |
41c7f551 | 145 | Ia32/DivU64x64Remainder.asm | MSFT \r |
6b4fe92a | 146 | Ia32/DivU64x32Remainder.c | MSFT \r |
147 | Ia32/DivU64x32.c | MSFT \r | |
148 | Ia32/DisablePaging32.c | MSFT \r | |
149 | Ia32/DisableInterrupts.c | MSFT \r | |
150 | Ia32/CpuPause.c | MSFT \r | |
151 | Ia32/CpuIdEx.c | MSFT \r | |
152 | Ia32/CpuId.c | MSFT \r | |
6b4fe92a | 153 | Ia32/CpuBreakpoint.c | MSFT \r |
154 | Ia32/ARShiftU64.c | MSFT \r | |
b26978d3 | 155 | Ia32/Thunk16.asm | MSFT\r |
156 | Ia32/EnablePaging64.asm | MSFT\r | |
9f4f2f0e | 157 | Ia32/EnableCache.c | MSFT\r |
158 | Ia32/DisableCache.c | MSFT\r | |
d074a8e1 | 159 | \r |
160 | Ia32/Wbinvd.asm | INTEL \r | |
161 | Ia32/WriteMm7.asm | INTEL \r | |
162 | Ia32/WriteMm6.asm | INTEL \r | |
163 | Ia32/WriteMm5.asm | INTEL \r | |
164 | Ia32/WriteMm4.asm | INTEL \r | |
165 | Ia32/WriteMm3.asm | INTEL \r | |
166 | Ia32/WriteMm2.asm | INTEL \r | |
167 | Ia32/WriteMm1.asm | INTEL \r | |
168 | Ia32/WriteMm0.asm | INTEL \r | |
169 | Ia32/WriteLdtr.asm | INTEL \r | |
170 | Ia32/WriteIdtr.asm | INTEL \r | |
171 | Ia32/WriteGdtr.asm | INTEL \r | |
172 | Ia32/WriteDr7.asm | INTEL \r | |
173 | Ia32/WriteDr6.asm | INTEL \r | |
174 | Ia32/WriteDr5.asm | INTEL \r | |
175 | Ia32/WriteDr4.asm | INTEL \r | |
176 | Ia32/WriteDr3.asm | INTEL \r | |
177 | Ia32/WriteDr2.asm | INTEL \r | |
178 | Ia32/WriteDr1.asm | INTEL \r | |
179 | Ia32/WriteDr0.asm | INTEL \r | |
180 | Ia32/WriteCr4.asm | INTEL \r | |
181 | Ia32/WriteCr3.asm | INTEL \r | |
182 | Ia32/WriteCr2.asm | INTEL \r | |
183 | Ia32/WriteCr0.asm | INTEL \r | |
184 | Ia32/WriteMsr64.asm | INTEL \r | |
185 | Ia32/SwapBytes64.asm | INTEL \r | |
186 | Ia32/SetJump.asm | INTEL \r | |
187 | Ia32/RRotU64.asm | INTEL \r | |
188 | Ia32/RShiftU64.asm | INTEL \r | |
189 | Ia32/ReadPmc.asm | INTEL \r | |
190 | Ia32/ReadTsc.asm | INTEL \r | |
191 | Ia32/ReadLdtr.asm | INTEL \r | |
192 | Ia32/ReadIdtr.asm | INTEL \r | |
193 | Ia32/ReadGdtr.asm | INTEL \r | |
194 | Ia32/ReadTr.asm | INTEL \r | |
195 | Ia32/ReadSs.asm | INTEL \r | |
196 | Ia32/ReadGs.asm | INTEL \r | |
197 | Ia32/ReadFs.asm | INTEL \r | |
198 | Ia32/ReadEs.asm | INTEL \r | |
199 | Ia32/ReadDs.asm | INTEL \r | |
200 | Ia32/ReadCs.asm | INTEL \r | |
201 | Ia32/ReadMsr64.asm | INTEL \r | |
202 | Ia32/ReadMm7.asm | INTEL \r | |
203 | Ia32/ReadMm6.asm | INTEL \r | |
204 | Ia32/ReadMm5.asm | INTEL \r | |
205 | Ia32/ReadMm4.asm | INTEL \r | |
206 | Ia32/ReadMm3.asm | INTEL \r | |
207 | Ia32/ReadMm2.asm | INTEL \r | |
208 | Ia32/ReadMm1.asm | INTEL \r | |
209 | Ia32/ReadMm0.asm | INTEL \r | |
210 | Ia32/ReadEflags.asm | INTEL \r | |
211 | Ia32/ReadDr7.asm | INTEL \r | |
212 | Ia32/ReadDr6.asm | INTEL \r | |
213 | Ia32/ReadDr5.asm | INTEL \r | |
214 | Ia32/ReadDr4.asm | INTEL \r | |
215 | Ia32/ReadDr3.asm | INTEL \r | |
216 | Ia32/ReadDr2.asm | INTEL \r | |
217 | Ia32/ReadDr1.asm | INTEL \r | |
218 | Ia32/ReadDr0.asm | INTEL \r | |
219 | Ia32/ReadCr4.asm | INTEL \r | |
220 | Ia32/ReadCr3.asm | INTEL \r | |
221 | Ia32/ReadCr2.asm | INTEL \r | |
222 | Ia32/ReadCr0.asm | INTEL \r | |
223 | Ia32/Mwait.asm | INTEL \r | |
224 | Ia32/Monitor.asm | INTEL \r | |
225 | Ia32/ModU64x32.asm | INTEL \r | |
226 | Ia32/MultU64x64.asm | INTEL \r | |
227 | Ia32/MultU64x32.asm | INTEL \r | |
228 | Ia32/LShiftU64.asm | INTEL \r | |
229 | Ia32/LRotU64.asm | INTEL \r | |
230 | Ia32/LongJump.asm | INTEL \r | |
231 | Ia32/Invd.asm | INTEL \r | |
d074a8e1 | 232 | Ia32/FxRestore.asm | INTEL \r |
233 | Ia32/FxSave.asm | INTEL \r | |
234 | Ia32/FlushCacheLine.asm | INTEL \r | |
235 | Ia32/EnablePaging32.asm | INTEL \r | |
236 | Ia32/EnableInterrupts.asm | INTEL \r | |
237 | Ia32/EnableDisableInterrupts.asm | INTEL \r | |
238 | Ia32/DivU64x64Remainder.asm | INTEL \r | |
239 | Ia32/DivU64x32Remainder.asm | INTEL \r | |
240 | Ia32/DivU64x32.asm | INTEL \r | |
241 | Ia32/DisablePaging32.asm | INTEL \r | |
242 | Ia32/DisableInterrupts.asm | INTEL \r | |
243 | Ia32/CpuPause.asm | INTEL \r | |
244 | Ia32/CpuIdEx.asm | INTEL \r | |
245 | Ia32/CpuId.asm | INTEL \r | |
d074a8e1 | 246 | Ia32/CpuBreakpoint.asm | INTEL \r |
247 | Ia32/ARShiftU64.asm | INTEL \r | |
b26978d3 | 248 | Ia32/Thunk16.asm | INTEL\r |
249 | Ia32/EnablePaging64.asm | INTEL\r | |
9f4f2f0e | 250 | Ia32/EnableCache.asm | INTEL\r |
251 | Ia32/DisableCache.asm | INTEL\r | |
d074a8e1 | 252 | \r |
cf683fed | 253 | Ia32/GccInline.c | GCC\r |
6b4fe92a | 254 | Ia32/Thunk16.S | GCC \r |
6b4fe92a | 255 | Ia32/EnableDisableInterrupts.S | GCC \r |
6b4fe92a | 256 | Ia32/EnablePaging64.S | GCC \r |
257 | Ia32/DisablePaging32.S | GCC \r | |
258 | Ia32/EnablePaging32.S | GCC \r | |
259 | Ia32/Mwait.S | GCC \r | |
260 | Ia32/Monitor.S | GCC \r | |
6b4fe92a | 261 | Ia32/CpuIdEx.S | GCC \r |
262 | Ia32/CpuId.S | GCC \r | |
263 | Ia32/LongJump.S | GCC \r | |
264 | Ia32/SetJump.S | GCC \r | |
265 | Ia32/SwapBytes64.S | GCC \r | |
266 | Ia32/DivU64x64Remainder.S | GCC \r | |
267 | Ia32/DivU64x32Remainder.S | GCC \r | |
268 | Ia32/ModU64x32.S | GCC \r | |
269 | Ia32/DivU64x32.S | GCC \r | |
270 | Ia32/MultU64x64.S | GCC \r | |
271 | Ia32/MultU64x32.S | GCC \r | |
272 | Ia32/RRotU64.S | GCC \r | |
273 | Ia32/LRotU64.S | GCC \r | |
274 | Ia32/ARShiftU64.S | GCC \r | |
275 | Ia32/RShiftU64.S | GCC \r | |
276 | Ia32/LShiftU64.S | GCC \r | |
9f4f2f0e | 277 | Ia32/EnableCache.S | GCC\r |
278 | Ia32/DisableCache.S | GCC\r | |
d074a8e1 | 279 | \r |
bb40027d | 280 | Ia32/DivS64x64Remainder.c\r |
bab427db | 281 | Ia32/InternalSwitchStack.c | MSFT\r |
282 | Ia32/InternalSwitchStack.c | INTEL\r | |
283 | Ia32/InternalSwitchStack.S | GCC\r | |
e1f414b6 | 284 | Ia32/Non-existing.c\r |
285 | Unaligned.c\r | |
b26978d3 | 286 | X86WriteIdtr.c\r |
287 | X86WriteGdtr.c\r | |
288 | X86Thunk.c\r | |
289 | X86ReadIdtr.c\r | |
290 | X86ReadGdtr.c\r | |
291 | X86Msr.c\r | |
c756ce80 | 292 | X86MemoryFence.c | MSFT\r |
293 | X86MemoryFence.c | INTEL\r | |
b26978d3 | 294 | X86GetInterruptState.c\r |
295 | X86FxSave.c\r | |
296 | X86FxRestore.c\r | |
297 | X86EnablePaging64.c\r | |
298 | X86EnablePaging32.c\r | |
299 | X86DisablePaging64.c\r | |
300 | X86DisablePaging32.c\r | |
e1f414b6 | 301 | \r |
302 | [Sources.X64]\r | |
303 | X64/Thunk16.asm\r | |
e1f414b6 | 304 | X64/CpuPause.asm\r |
e1f414b6 | 305 | X64/EnableDisableInterrupts.asm\r |
306 | X64/DisableInterrupts.asm\r | |
307 | X64/EnableInterrupts.asm\r | |
e1f414b6 | 308 | X64/FlushCacheLine.asm\r |
309 | X64/Invd.asm\r | |
310 | X64/Wbinvd.asm\r | |
311 | X64/DisablePaging64.asm\r | |
e1f414b6 | 312 | X64/Mwait.asm\r |
313 | X64/Monitor.asm\r | |
314 | X64/ReadPmc.asm\r | |
315 | X64/ReadTsc.asm\r | |
316 | X64/WriteMm7.asm\r | |
317 | X64/WriteMm6.asm\r | |
318 | X64/WriteMm5.asm\r | |
319 | X64/WriteMm4.asm\r | |
320 | X64/WriteMm3.asm\r | |
321 | X64/WriteMm2.asm\r | |
322 | X64/WriteMm1.asm\r | |
323 | X64/WriteMm0.asm\r | |
324 | X64/ReadMm7.asm\r | |
325 | X64/ReadMm6.asm\r | |
326 | X64/ReadMm5.asm\r | |
327 | X64/ReadMm4.asm\r | |
328 | X64/ReadMm3.asm\r | |
329 | X64/ReadMm2.asm\r | |
330 | X64/ReadMm1.asm\r | |
331 | X64/ReadMm0.asm\r | |
332 | X64/FxRestore.asm\r | |
333 | X64/FxSave.asm\r | |
334 | X64/WriteLdtr.asm\r | |
335 | X64/ReadLdtr.asm\r | |
336 | X64/WriteIdtr.asm\r | |
337 | X64/ReadIdtr.asm\r | |
338 | X64/WriteGdtr.asm\r | |
339 | X64/ReadGdtr.asm\r | |
340 | X64/ReadTr.asm\r | |
341 | X64/ReadSs.asm\r | |
342 | X64/ReadGs.asm\r | |
343 | X64/ReadFs.asm\r | |
344 | X64/ReadEs.asm\r | |
345 | X64/ReadDs.asm\r | |
346 | X64/ReadCs.asm\r | |
347 | X64/WriteDr7.asm\r | |
348 | X64/WriteDr6.asm\r | |
349 | X64/WriteDr5.asm\r | |
350 | X64/WriteDr4.asm\r | |
351 | X64/WriteDr3.asm\r | |
352 | X64/WriteDr2.asm\r | |
353 | X64/WriteDr1.asm\r | |
354 | X64/WriteDr0.asm\r | |
355 | X64/ReadDr7.asm\r | |
356 | X64/ReadDr6.asm\r | |
357 | X64/ReadDr5.asm\r | |
358 | X64/ReadDr4.asm\r | |
359 | X64/ReadDr3.asm\r | |
360 | X64/ReadDr2.asm\r | |
361 | X64/ReadDr1.asm\r | |
362 | X64/ReadDr0.asm\r | |
363 | X64/WriteCr4.asm\r | |
364 | X64/WriteCr3.asm\r | |
365 | X64/WriteCr2.asm\r | |
366 | X64/WriteCr0.asm\r | |
367 | X64/ReadCr4.asm\r | |
368 | X64/ReadCr3.asm\r | |
369 | X64/ReadCr2.asm\r | |
370 | X64/ReadCr0.asm\r | |
e1f414b6 | 371 | X64/ReadEflags.asm\r |
372 | X64/CpuIdEx.asm\r | |
373 | X64/CpuId.asm\r | |
374 | X64/LongJump.asm\r | |
375 | X64/SetJump.asm\r | |
376 | X64/SwitchStack.asm\r | |
9f4f2f0e | 377 | X64/EnableCache.asm\r |
378 | X64/DisableCache.asm\r | |
d074a8e1 | 379 | \r |
d074a8e1 | 380 | X64/CpuBreakpoint.c | MSFT \r |
381 | X64/WriteMsr64.c | MSFT \r | |
382 | X64/ReadMsr64.c | MSFT \r | |
d074a8e1 | 383 | \r |
d074a8e1 | 384 | X64/CpuBreakpoint.asm | INTEL \r |
385 | X64/WriteMsr64.asm | INTEL \r | |
386 | X64/ReadMsr64.asm | INTEL \r | |
d074a8e1 | 387 | \r |
e1f414b6 | 388 | X64/Non-existing.c\r |
389 | Math64.c\r | |
390 | Unaligned.c\r | |
b26978d3 | 391 | X86WriteIdtr.c\r |
392 | X86WriteGdtr.c\r | |
393 | X86Thunk.c\r | |
394 | X86ReadIdtr.c\r | |
395 | X86ReadGdtr.c\r | |
396 | X86Msr.c\r | |
2653bb43 | 397 | X86MemoryFence.c | MSFT\r |
398 | X86MemoryFence.c | INTEL\r | |
b26978d3 | 399 | X86GetInterruptState.c\r |
400 | X86FxSave.c\r | |
401 | X86FxRestore.c\r | |
402 | X86EnablePaging64.c\r | |
403 | X86EnablePaging32.c\r | |
404 | X86DisablePaging64.c\r | |
405 | X86DisablePaging32.c\r | |
cf683fed | 406 | X64/GccInline.c | GCC\r |
6b4fe92a | 407 | X64/Thunk16.S | GCC \r |
408 | X64/SwitchStack.S | GCC \r | |
409 | X64/SetJump.S | GCC \r | |
6b4fe92a | 410 | X64/LongJump.S | GCC \r |
6b4fe92a | 411 | X64/EnableDisableInterrupts.S | GCC \r |
412 | X64/DisablePaging64.S | GCC \r | |
6b4fe92a | 413 | X64/CpuId.S | GCC \r |
414 | X64/CpuIdEx.S | GCC \r | |
9f4f2f0e | 415 | X64/EnableCache.S | GCC\r |
416 | X64/DisableCache.S | GCC\r | |
a21f46e4 | 417 | ChkStkGcc.c | GCC \r |
e1f414b6 | 418 | \r |
419 | [Sources.IPF]\r | |
420 | Ipf/AccessGp.s\r | |
421 | Ipf/ReadCpuid.s\r | |
422 | Ipf/ExecFc.s\r | |
423 | Ipf/AsmPalCall.s\r | |
424 | Ipf/AccessPsr.s\r | |
425 | Ipf/AccessPmr.s\r | |
426 | Ipf/AccessKr.s\r | |
8facd18f | 427 | Ipf/AccessKr7.s\r |
e1f414b6 | 428 | Ipf/AccessGcr.s\r |
429 | Ipf/AccessEicr.s\r | |
430 | Ipf/AccessDbr.s\r | |
59e0bb0c | 431 | Ipf/AccessMsr.s | INTEL\r |
4e16d2cd | 432 | Ipf/AccessMsr.s | GCC\r |
433 | Ipf/AccessMsrDb.s | MSFT\r | |
287f4f47 | 434 | Ipf/InternalFlushCacheRange.s\r |
435 | Ipf/FlushCacheRange.c\r | |
e1f414b6 | 436 | Ipf/InternalSwitchStack.c\r |
437 | Ipf/GetInterruptState.s\r | |
e1f414b6 | 438 | Ipf/CpuPause.s\r |
878afe6b | 439 | Ipf/CpuBreakpoint.c | INTEL\r |
440 | Ipf/CpuBreakpointMsc.c | MSFT\r | |
59e0bb0c | 441 | Ipf/AsmCpuMisc.s | GCC\r |
e1f414b6 | 442 | Ipf/Unaligned.c\r |
443 | Ipf/SwitchStack.s\r | |
572b6b1a | 444 | Ipf/LongJmp.s\r |
445 | Ipf/SetJmp.s\r | |
aad6137d | 446 | Ipf/ReadCr.s\r |
aad6137d | 447 | Ipf/ReadAr.s\r |
572b6b1a | 448 | Ipf/Ia64gen.h\r |
449 | Ipf/Asm.h\r | |
e1f414b6 | 450 | Math64.c\r |
e1f414b6 | 451 | \r |
452 | [Sources.EBC]\r | |
e1f414b6 | 453 | Ebc/CpuBreakpoint.c\r |
454 | Ebc/SetJumpLongJump.c\r | |
455 | Ebc/SwitchStack.c\r | |
456 | Unaligned.c\r | |
457 | Math64.c\r | |
458 | \r | |
4b5f371b | 459 | [Sources.ARM]\r |
460 | Arm/InternalSwitchStack.c\r | |
461 | Arm/Unaligned.c\r | |
703f1d09 | 462 | Math64.c | RVCT \r |
4b5f371b | 463 | \r |
464 | Arm/SwitchStack.asm | RVCT\r | |
465 | Arm/SetJumpLongJump.asm | RVCT\r | |
466 | Arm/DisableInterrupts.asm | RVCT\r | |
467 | Arm/EnableInterrupts.asm | RVCT\r | |
468 | Arm/GetInterruptsState.asm | RVCT\r | |
469 | Arm/CpuPause.asm | RVCT\r | |
703f1d09 | 470 | Arm/CpuBreakpoint.asm | RVCT\r |
8c1e7951 | 471 | Arm/MemoryFence.asm | RVCT\r |
4b5f371b | 472 | \r |
703f1d09 | 473 | Arm/Math64.S | GCC\r |
08068159 | 474 | Arm/SwitchStack.S | GCC\r |
4b5f371b | 475 | Arm/EnableInterrupts.S | GCC\r |
476 | Arm/DisableInterrupts.S | GCC\r | |
7f22d351 | 477 | Arm/GetInterruptsState.S | GCC\r |
4b5f371b | 478 | Arm/SetJumpLongJump.S | GCC\r |
479 | Arm/CpuBreakpoint.S | GCC\r | |
8c1e7951 | 480 | Arm/MemoryFence.S | GCC\r |
4b5f371b | 481 | \r |
807e2604 HL |
482 | [Sources.AARCH64]\r |
483 | Arm/InternalSwitchStack.c\r | |
484 | Arm/Unaligned.c\r | |
485 | Math64.c\r | |
486 | \r | |
8c1e7951 | 487 | AArch64/MemoryFence.S | GCC\r |
807e2604 HL |
488 | AArch64/SwitchStack.S | GCC\r |
489 | AArch64/EnableInterrupts.S | GCC\r | |
490 | AArch64/DisableInterrupts.S | GCC\r | |
491 | AArch64/GetInterruptsState.S | GCC\r | |
492 | AArch64/SetJumpLongJump.S | GCC\r | |
493 | AArch64/CpuBreakpoint.S | GCC\r | |
494 | \r | |
e1f414b6 | 495 | [Packages]\r |
496 | MdePkg/MdePkg.dec\r | |
497 | \r | |
e1f414b6 | 498 | [LibraryClasses]\r |
499 | PcdLib\r | |
e1f414b6 | 500 | DebugLib\r |
501 | BaseMemoryLib\r | |
502 | \r | |
1081f624 | 503 | [Pcd]\r |
b3af5df6 | 504 | gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength\r |
505 | gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength\r | |
506 | gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength\r | |
da03183c LE |
507 | \r |
508 | [FeaturePcd]\r | |
1081f624 | 509 | gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList\r |