]>
Commit | Line | Data |
---|---|---|
878ddf1f | 1 | /** @file\r |
2 | Base Library CPU Functions for EBC\r | |
3 | \r | |
4 | Copyright (c) 2006, Intel Corporation<BR>\r | |
5 | All rights reserved. This program and the accompanying materials\r | |
6 | are licensed and made available under the terms and conditions of the BSD License\r | |
7 | which accompanies this distribution. The full text of the license may be found at\r | |
8 | http://opensource.org/licenses/bsd-license.php\r | |
9 | \r | |
10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
12 | \r | |
13 | **/\r | |
14 | \r | |
15 | extern\r | |
16 | UINT64\r | |
17 | _break (\r | |
18 | CHAR8 BreakCode\r | |
19 | );\r | |
20 | \r | |
21 | /**\r | |
22 | Generates a breakpoint on the CPU.\r | |
23 | \r | |
24 | Generates a breakpoint on the CPU. The breakpoint must be implemented such\r | |
25 | that code can resume normal execution after the breakpoint.\r | |
26 | \r | |
27 | **/\r | |
28 | VOID\r | |
29 | EFIAPI\r | |
30 | CpuBreakpoint (\r | |
31 | VOID\r | |
32 | )\r | |
33 | {\r | |
34 | _break (3);\r | |
35 | }\r | |
36 | \r | |
37 | /**\r | |
38 | Used to serialize load and store operations.\r | |
39 | \r | |
40 | All loads and stores that proceed calls to this function are guaranteed to be\r | |
41 | globally visible when this function returns.\r | |
42 | \r | |
43 | **/\r | |
44 | VOID\r | |
45 | EFIAPI\r | |
46 | MemoryFence (\r | |
47 | VOID\r | |
48 | )\r | |
49 | {\r | |
50 | }\r | |
51 | \r | |
52 | /**\r | |
53 | Disables CPU interrupts.\r | |
54 | \r | |
55 | Disables CPU interrupts.\r | |
56 | \r | |
57 | **/\r | |
58 | VOID\r | |
59 | EFIAPI\r | |
60 | DisableInterrupts (\r | |
61 | VOID\r | |
62 | )\r | |
63 | {\r | |
64 | ASSERT (FALSE);\r | |
65 | }\r | |
66 | \r | |
67 | /**\r | |
68 | Enables CPU interrupts.\r | |
69 | \r | |
70 | Enables CPU interrupts.\r | |
71 | \r | |
72 | **/\r | |
73 | VOID\r | |
74 | EFIAPI\r | |
75 | EnableInterrupts (\r | |
76 | VOID\r | |
77 | )\r | |
78 | {\r | |
79 | ASSERT (FALSE);\r | |
80 | }\r | |
81 | \r | |
82 | /**\r | |
83 | Retrieves the current CPU interrupt state.\r | |
84 | \r | |
85 | Retrieves the current CPU interrupt state. Returns TRUE is interrupts are\r | |
86 | currently enabled. Otherwise returns FALSE.\r | |
87 | \r | |
88 | @retval TRUE CPU interrupts are enabled.\r | |
89 | @retval FALSE CPU interrupts are disabled.\r | |
90 | \r | |
91 | **/\r | |
92 | BOOLEAN\r | |
93 | EFIAPI\r | |
94 | GetInterruptState (\r | |
95 | VOID\r | |
96 | )\r | |
97 | {\r | |
98 | ASSERT (FALSE);\r | |
99 | return FALSE;\r | |
100 | }\r | |
97d92bda | 101 | \r |
102 | /**\r | |
103 | Enables CPU interrupts for the smallest window required to capture any\r | |
104 | pending interrupts.\r | |
105 | \r | |
106 | Enables CPU interrupts for the smallest window required to capture any\r | |
107 | pending interrupts.\r | |
108 | \r | |
109 | **/\r | |
110 | VOID\r | |
111 | EFIAPI\r | |
112 | EnableDisableInterrupts (\r | |
113 | VOID\r | |
114 | )\r | |
115 | {\r | |
116 | EnableInterrupts ();\r | |
117 | DisableInterrupts ();\r | |
118 | }\r | |
119 | \r | |
120 | /**\r | |
121 | Requests CPU to pause for a short period of time.\r | |
122 | \r | |
123 | Requests CPU to pause for a short period of time. Typically used in MP\r | |
124 | systems to prevent memory starvation while waiting for a spin lock.\r | |
125 | \r | |
126 | **/\r | |
127 | VOID\r | |
128 | EFIAPI\r | |
129 | CpuPause (\r | |
130 | VOID\r | |
131 | )\r | |
132 | {\r | |
133 | }\r | |
134 | \r | |
135 | /**\r | |
136 | Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r | |
137 | \r | |
138 | Flushes all the Translation Lookaside Buffers(TLB) entries in a CPU.\r | |
139 | \r | |
140 | **/\r | |
141 | VOID\r | |
142 | EFIAPI\r | |
143 | CpuFlushTlb (\r | |
144 | VOID\r | |
145 | )\r | |
146 | {\r | |
147 | ASSERT (FALSE);\r | |
148 | }\r | |
149 | \r | |
150 | /**\r | |
151 | Places the CPU in a sleep state until an interrupt is received.\r | |
152 | \r | |
153 | Places the CPU in a sleep state until an interrupt is received. If interrupts\r | |
154 | are disabled prior to calling this function, then the CPU will be placed in a\r | |
155 | sleep state indefinitely.\r | |
156 | \r | |
157 | **/\r | |
158 | VOID\r | |
159 | EFIAPI\r | |
160 | CpuSleep (\r | |
161 | VOID\r | |
162 | )\r | |
163 | {\r | |
164 | }\r |