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UefiCpuPkg: Move AsmRelocateApLoopStart from Mpfuncs.nasm to AmdSev.nasm
[mirror_edk2.git] / MdePkg / Library / BaseLib / Ia32 / FlushCacheLine.c
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e1f414b6 1/** @file\r
2 AsmFlushCacheLine function\r
3\r
9095d37b 4 Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r
9344f092 5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
e1f414b6 6\r
7**/\r
8\r
42eedea9 9/**\r
10 Flushes a cache line from all the instruction and data caches within the\r
11 coherency domain of the CPU.\r
12\r
13 Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
030cd1a2 14 This function is only available on IA-32 and x64.\r
42eedea9 15\r
16 @param LinearAddress The address of the cache line to flush. If the CPU is\r
17 in a physical addressing mode, then LinearAddress is a\r
18 physical address. If the CPU is in a virtual\r
19 addressing mode, then LinearAddress is a virtual\r
20 address.\r
21\r
22 @return LinearAddress\r
23**/\r
e1f414b6 24VOID *\r
25EFIAPI\r
26AsmFlushCacheLine (\r
2f88bd3a 27 IN VOID *LinearAddress\r
e1f414b6 28 )\r
29{\r
881813d7 30 //\r
9095d37b 31 // If the CPU does not support CLFLUSH instruction,\r
881813d7
MK
32 // then promote flush range to flush entire cache.\r
33 //\r
e1f414b6 34 _asm {\r
881813d7
MK
35 mov eax, 1\r
36 cpuid\r
37 test edx, BIT19\r
38 jz NoClflush\r
6f7878a9 39 mov eax, dword ptr [LinearAddress]\r
e1f414b6 40 clflush [eax]\r
881813d7
MK
41 jmp Done\r
42NoClflush:\r
43 wbinvd\r
44Done:\r
e1f414b6 45 }\r
9095d37b 46\r
881813d7 47 return LinearAddress;\r
e1f414b6 48}\r