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11f43dfd | 1 | /** @file\r |
4ca0802e | 2 | I/O Library. The implementations are based on EFI_PEI_SERVICE->CpuIo interface.\r |
11f43dfd | 3 | \r |
9095d37b | 4 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
72bda2ac LD |
5 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r |
6 | \r | |
19388d29 | 7 | This program and the accompanying materials\r |
11f43dfd | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
2fc59a00 | 10 | http://opensource.org/licenses/bsd-license.php.\r |
11f43dfd | 11 | \r |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
11f43dfd | 15 | **/\r |
16 | \r | |
c892d846 | 17 | \r |
11f43dfd | 18 | #include <PiPei.h>\r |
c892d846 | 19 | \r |
11f43dfd | 20 | #include <Library/IoLib.h>\r |
21 | #include <Library/DebugLib.h>\r | |
22 | #include <Library/BaseLib.h>\r | |
23 | #include <Library/PeiServicesTablePointerLib.h>\r | |
24 | \r | |
72bda2ac LD |
25 | \r |
26 | /**\r | |
27 | Reads registers in the EFI CPU I/O space.\r | |
28 | \r | |
29 | Reads the I/O port specified by Port with registers width specified by Width.\r | |
30 | The port is read Count times, and the read data is stored in the provided Buffer.\r | |
31 | \r | |
32 | This function must guarantee that all I/O read and write operations are serialized.\r | |
33 | If such operations are not supported, then ASSERT().\r | |
34 | \r | |
35 | @param Port The base address of the I/O operation.\r | |
36 | The caller is responsible for aligning the Address if required.\r | |
37 | @param Width The width of the I/O operation.\r | |
38 | @param Count The number of times to read I/O port.\r | |
39 | @param Buffer The buffer to store the read data into.\r | |
40 | \r | |
41 | **/\r | |
42 | VOID\r | |
43 | EFIAPI\r | |
44 | IoReadFifoWorker (\r | |
45 | IN UINTN Port,\r | |
46 | IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r | |
47 | IN UINTN Count,\r | |
48 | IN VOID *Buffer\r | |
49 | )\r | |
50 | {\r | |
51 | CONST EFI_PEI_SERVICES **PeiServices;\r | |
52 | EFI_PEI_CPU_IO_PPI *CpuIo;\r | |
53 | EFI_STATUS Status;\r | |
54 | \r | |
55 | PeiServices = GetPeiServicesTablePointer ();\r | |
56 | CpuIo = (*PeiServices)->CpuIo;\r | |
57 | ASSERT (CpuIo != NULL);\r | |
58 | \r | |
59 | Status = CpuIo->Io.Read (PeiServices, CpuIo, Width, Port, Count, Buffer);\r | |
60 | ASSERT_EFI_ERROR (Status);\r | |
61 | }\r | |
62 | \r | |
63 | /**\r | |
64 | Writes registers in the EFI CPU I/O space.\r | |
65 | \r | |
66 | Writes the I/O port specified by Port with registers width specified by Width.\r | |
67 | The port is written Count times, and the write data is retrieved from the provided Buffer.\r | |
68 | \r | |
69 | This function must guarantee that all I/O read and write operations are serialized.\r | |
70 | If such operations are not supported, then ASSERT().\r | |
71 | \r | |
72 | @param Port The base address of the I/O operation.\r | |
73 | The caller is responsible for aligning the Address if required.\r | |
74 | @param Width The width of the I/O operation.\r | |
75 | @param Count The number of times to write I/O port.\r | |
76 | @param Buffer The buffer to store the read data into.\r | |
77 | \r | |
78 | **/\r | |
79 | VOID\r | |
80 | EFIAPI\r | |
81 | IoWriteFifoWorker (\r | |
82 | IN UINTN Port,\r | |
83 | IN EFI_PEI_CPU_IO_PPI_WIDTH Width,\r | |
84 | IN UINTN Count,\r | |
85 | IN VOID *Buffer\r | |
86 | )\r | |
87 | {\r | |
88 | CONST EFI_PEI_SERVICES **PeiServices;\r | |
89 | EFI_PEI_CPU_IO_PPI *CpuIo;\r | |
90 | EFI_STATUS Status;\r | |
91 | \r | |
92 | PeiServices = GetPeiServicesTablePointer ();\r | |
93 | CpuIo = (*PeiServices)->CpuIo;\r | |
94 | ASSERT (CpuIo != NULL);\r | |
95 | \r | |
96 | Status = CpuIo->Io.Write (PeiServices, CpuIo, Width, Port, Count, Buffer);\r | |
97 | ASSERT_EFI_ERROR (Status);\r | |
98 | }\r | |
99 | \r | |
11f43dfd | 100 | /**\r |
101 | Reads an 8-bit I/O port.\r | |
102 | \r | |
103 | Reads the 8-bit I/O port specified by Port. The 8-bit read value is returned.\r | |
104 | This function must guarantee that all I/O read and write operations are\r | |
105 | serialized.\r | |
106 | \r | |
107 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
108 | \r | |
109 | @param Port The I/O port to read.\r | |
110 | \r | |
80f0c0c4 | 111 | @return The value read.\r |
11f43dfd | 112 | \r |
113 | **/\r | |
114 | UINT8\r | |
115 | EFIAPI\r | |
116 | IoRead8 (\r | |
117 | IN UINTN Port\r | |
118 | )\r | |
119 | {\r | |
fe7fd578 | 120 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 121 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
122 | \r | |
5240b97c | 123 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 124 | CpuIo = (*PeiServices)->CpuIo;\r |
125 | ASSERT (CpuIo != NULL);\r | |
126 | \r | |
127 | return CpuIo->IoRead8 (PeiServices, CpuIo, (UINT64) Port);\r | |
128 | }\r | |
129 | \r | |
130 | /**\r | |
131 | Writes an 8-bit I/O port.\r | |
132 | \r | |
133 | Writes the 8-bit I/O port specified by Port with the value specified by Value\r | |
134 | and returns Value. This function must guarantee that all I/O read and write\r | |
135 | operations are serialized.\r | |
136 | \r | |
137 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
138 | \r | |
139 | @param Port The I/O port to write.\r | |
140 | @param Value The value to write to the I/O port.\r | |
141 | \r | |
142 | @return The value written the I/O port.\r | |
143 | \r | |
144 | **/\r | |
145 | UINT8\r | |
146 | EFIAPI\r | |
147 | IoWrite8 (\r | |
148 | IN UINTN Port,\r | |
149 | IN UINT8 Value\r | |
150 | )\r | |
151 | {\r | |
fe7fd578 | 152 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 153 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
154 | \r | |
5240b97c | 155 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 156 | CpuIo = (*PeiServices)->CpuIo;\r |
157 | ASSERT (CpuIo != NULL);\r | |
158 | \r | |
159 | CpuIo->IoWrite8 (PeiServices, CpuIo, (UINT64) Port, Value);\r | |
160 | return Value;\r | |
161 | }\r | |
162 | \r | |
163 | /**\r | |
164 | Reads a 16-bit I/O port.\r | |
165 | \r | |
166 | Reads the 16-bit I/O port specified by Port. The 16-bit read value is returned.\r | |
167 | This function must guarantee that all I/O read and write operations are\r | |
168 | serialized.\r | |
169 | \r | |
170 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
80f0c0c4 | 171 | If Port is not aligned on a 16-bit boundary, then ASSERT().\r |
11f43dfd | 172 | \r |
173 | @param Port The I/O port to read.\r | |
174 | \r | |
80f0c0c4 | 175 | @return The value read.\r |
11f43dfd | 176 | \r |
177 | **/\r | |
178 | UINT16\r | |
179 | EFIAPI\r | |
180 | IoRead16 (\r | |
181 | IN UINTN Port\r | |
182 | )\r | |
183 | {\r | |
fe7fd578 | 184 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 185 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
186 | \r | |
5240b97c | 187 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 188 | CpuIo = (*PeiServices)->CpuIo;\r |
189 | ASSERT (CpuIo != NULL);\r | |
190 | //\r | |
191 | // Make sure Port is aligned on a 16-bit boundary.\r | |
192 | //\r | |
193 | ASSERT ((Port & 1) == 0);\r | |
194 | return CpuIo->IoRead16 (PeiServices, CpuIo, (UINT64) Port);\r | |
195 | }\r | |
196 | \r | |
197 | /**\r | |
198 | Writes a 16-bit I/O port.\r | |
199 | \r | |
200 | Writes the 16-bit I/O port specified by Port with the value specified by Value\r | |
201 | and returns Value. This function must guarantee that all I/O read and write\r | |
202 | operations are serialized.\r | |
203 | \r | |
204 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
80f0c0c4 | 205 | If Port is not aligned on a 16-bit boundary, then ASSERT().\r |
9095d37b | 206 | \r |
11f43dfd | 207 | @param Port The I/O port to write.\r |
208 | @param Value The value to write to the I/O port.\r | |
209 | \r | |
210 | @return The value written the I/O port.\r | |
211 | \r | |
212 | **/\r | |
213 | UINT16\r | |
214 | EFIAPI\r | |
215 | IoWrite16 (\r | |
216 | IN UINTN Port,\r | |
217 | IN UINT16 Value\r | |
218 | )\r | |
219 | {\r | |
fe7fd578 | 220 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 221 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
222 | \r | |
5240b97c | 223 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 224 | CpuIo = (*PeiServices)->CpuIo;\r |
225 | ASSERT (CpuIo != NULL);\r | |
226 | //\r | |
227 | // Make sure Port is aligned on a 16-bit boundary.\r | |
228 | //\r | |
229 | ASSERT ((Port & 1) == 0);\r | |
230 | CpuIo->IoWrite16 (PeiServices, CpuIo, (UINT64) Port, Value);\r | |
231 | return Value;\r | |
232 | }\r | |
233 | \r | |
234 | /**\r | |
235 | Reads a 32-bit I/O port.\r | |
236 | \r | |
237 | Reads the 32-bit I/O port specified by Port. The 32-bit read value is returned.\r | |
238 | This function must guarantee that all I/O read and write operations are\r | |
239 | serialized.\r | |
240 | \r | |
241 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
80f0c0c4 | 242 | If Port is not aligned on a 32-bit boundary, then ASSERT().\r |
9095d37b | 243 | \r |
11f43dfd | 244 | @param Port The I/O port to read.\r |
245 | \r | |
80f0c0c4 | 246 | @return The value read.\r |
11f43dfd | 247 | \r |
248 | **/\r | |
249 | UINT32\r | |
250 | EFIAPI\r | |
251 | IoRead32 (\r | |
252 | IN UINTN Port\r | |
253 | )\r | |
254 | {\r | |
fe7fd578 | 255 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 256 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
257 | \r | |
5240b97c | 258 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 259 | CpuIo = (*PeiServices)->CpuIo;\r |
260 | ASSERT (CpuIo != NULL);\r | |
261 | //\r | |
262 | // Make sure Port is aligned on a 32-bit boundary.\r | |
263 | //\r | |
264 | ASSERT ((Port & 3) == 0);\r | |
265 | return CpuIo->IoRead32 (PeiServices, CpuIo, (UINT64) Port);\r | |
266 | }\r | |
267 | \r | |
268 | /**\r | |
269 | Writes a 32-bit I/O port.\r | |
270 | \r | |
271 | Writes the 32-bit I/O port specified by Port with the value specified by Value\r | |
272 | and returns Value. This function must guarantee that all I/O read and write\r | |
273 | operations are serialized.\r | |
274 | \r | |
275 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
80f0c0c4 | 276 | If Port is not aligned on a 32-bit boundary, then ASSERT().\r |
9095d37b | 277 | \r |
11f43dfd | 278 | @param Port The I/O port to write.\r |
279 | @param Value The value to write to the I/O port.\r | |
280 | \r | |
281 | @return The value written the I/O port.\r | |
282 | \r | |
283 | **/\r | |
284 | UINT32\r | |
285 | EFIAPI\r | |
286 | IoWrite32 (\r | |
287 | IN UINTN Port,\r | |
288 | IN UINT32 Value\r | |
289 | )\r | |
290 | {\r | |
fe7fd578 | 291 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 292 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
293 | \r | |
5240b97c | 294 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 295 | CpuIo = (*PeiServices)->CpuIo;\r |
296 | ASSERT (CpuIo != NULL);\r | |
297 | //\r | |
298 | // Make sure Port is aligned on a 32-bit boundary.\r | |
299 | //\r | |
300 | ASSERT ((Port & 3) == 0);\r | |
301 | CpuIo->IoWrite32 (PeiServices, CpuIo, (UINT64) Port, Value);\r | |
302 | return Value;\r | |
303 | }\r | |
304 | \r | |
305 | /**\r | |
306 | Reads a 64-bit I/O port.\r | |
307 | \r | |
308 | Reads the 64-bit I/O port specified by Port. The 64-bit read value is returned.\r | |
309 | This function must guarantee that all I/O read and write operations are\r | |
310 | serialized.\r | |
311 | \r | |
312 | If 64-bit I/O port operations are not supported, then ASSERT().\r | |
80f0c0c4 | 313 | If Port is not aligned on a 64-bit boundary, then ASSERT().\r |
11f43dfd | 314 | \r |
315 | @param Port The I/O port to read.\r | |
316 | \r | |
80f0c0c4 | 317 | @return The value read.\r |
11f43dfd | 318 | \r |
319 | **/\r | |
320 | UINT64\r | |
321 | EFIAPI\r | |
322 | IoRead64 (\r | |
323 | IN UINTN Port\r | |
324 | )\r | |
325 | {\r | |
fe7fd578 | 326 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 327 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
328 | \r | |
5240b97c | 329 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 330 | CpuIo = (*PeiServices)->CpuIo;\r |
331 | ASSERT (CpuIo != NULL);\r | |
332 | //\r | |
333 | // Make sure Port is aligned on a 64-bit boundary.\r | |
334 | //\r | |
335 | ASSERT ((Port & 7) == 0);\r | |
336 | return CpuIo->IoRead64 (PeiServices, CpuIo, (UINT64) Port);\r | |
337 | }\r | |
338 | \r | |
339 | /**\r | |
340 | Writes a 64-bit I/O port.\r | |
341 | \r | |
342 | Writes the 64-bit I/O port specified by Port with the value specified by Value\r | |
343 | and returns Value. This function must guarantee that all I/O read and write\r | |
344 | operations are serialized.\r | |
345 | \r | |
346 | If 64-bit I/O port operations are not supported, then ASSERT().\r | |
80f0c0c4 | 347 | If Port is not aligned on a 64-bit boundary, then ASSERT().\r |
11f43dfd | 348 | \r |
349 | @param Port The I/O port to write.\r | |
350 | @param Value The value to write to the I/O port.\r | |
351 | \r | |
352 | @return The value written the I/O port.\r | |
353 | \r | |
354 | **/\r | |
355 | UINT64\r | |
356 | EFIAPI\r | |
357 | IoWrite64 (\r | |
358 | IN UINTN Port,\r | |
359 | IN UINT64 Value\r | |
360 | )\r | |
361 | {\r | |
fe7fd578 | 362 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 363 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
364 | \r | |
5240b97c | 365 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 366 | CpuIo = (*PeiServices)->CpuIo;\r |
367 | ASSERT (CpuIo != NULL);\r | |
368 | //\r | |
369 | // Make sure Port is aligned on a 64-bit boundary.\r | |
370 | //\r | |
371 | ASSERT ((Port & 7) == 0);\r | |
372 | CpuIo->IoWrite64 (PeiServices, CpuIo, (UINT64) Port, Value);\r | |
373 | return Value;;\r | |
374 | }\r | |
375 | \r | |
72bda2ac LD |
376 | /**\r |
377 | Reads an 8-bit I/O port fifo into a block of memory.\r | |
378 | \r | |
379 | Reads the 8-bit I/O fifo port specified by Port.\r | |
380 | The port is read Count times, and the read data is\r | |
381 | stored in the provided Buffer.\r | |
382 | \r | |
383 | This function must guarantee that all I/O read and write operations are\r | |
384 | serialized.\r | |
385 | \r | |
386 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
387 | \r | |
388 | @param Port The I/O port to read.\r | |
389 | @param Count The number of times to read I/O port.\r | |
390 | @param Buffer The buffer to store the read data into.\r | |
391 | \r | |
392 | **/\r | |
393 | VOID\r | |
394 | EFIAPI\r | |
395 | IoReadFifo8 (\r | |
396 | IN UINTN Port,\r | |
397 | IN UINTN Count,\r | |
398 | OUT VOID *Buffer\r | |
399 | )\r | |
400 | {\r | |
401 | IoReadFifoWorker (Port, EfiPeiCpuIoWidthFifoUint8, Count, Buffer);\r | |
402 | }\r | |
403 | \r | |
404 | /**\r | |
405 | Writes a block of memory into an 8-bit I/O port fifo.\r | |
406 | \r | |
407 | Writes the 8-bit I/O fifo port specified by Port.\r | |
408 | The port is written Count times, and the write data is\r | |
409 | retrieved from the provided Buffer.\r | |
410 | \r | |
411 | This function must guarantee that all I/O write and write operations are\r | |
412 | serialized.\r | |
413 | \r | |
414 | If 8-bit I/O port operations are not supported, then ASSERT().\r | |
415 | \r | |
416 | @param Port The I/O port to write.\r | |
417 | @param Count The number of times to write I/O port.\r | |
418 | @param Buffer The buffer to retrieve the write data from.\r | |
419 | \r | |
420 | **/\r | |
421 | VOID\r | |
422 | EFIAPI\r | |
423 | IoWriteFifo8 (\r | |
424 | IN UINTN Port,\r | |
425 | IN UINTN Count,\r | |
426 | IN VOID *Buffer\r | |
427 | )\r | |
428 | {\r | |
429 | IoWriteFifoWorker (Port, EfiPeiCpuIoWidthFifoUint8, Count, Buffer);\r | |
430 | }\r | |
431 | \r | |
432 | /**\r | |
433 | Reads a 16-bit I/O port fifo into a block of memory.\r | |
434 | \r | |
435 | Reads the 16-bit I/O fifo port specified by Port.\r | |
436 | The port is read Count times, and the read data is\r | |
437 | stored in the provided Buffer.\r | |
438 | \r | |
439 | This function must guarantee that all I/O read and write operations are\r | |
440 | serialized.\r | |
441 | \r | |
442 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
443 | \r | |
444 | @param Port The I/O port to read.\r | |
445 | @param Count The number of times to read I/O port.\r | |
446 | @param Buffer The buffer to store the read data into.\r | |
447 | \r | |
448 | **/\r | |
449 | VOID\r | |
450 | EFIAPI\r | |
451 | IoReadFifo16 (\r | |
452 | IN UINTN Port,\r | |
453 | IN UINTN Count,\r | |
454 | OUT VOID *Buffer\r | |
455 | )\r | |
456 | {\r | |
457 | //\r | |
458 | // Make sure Port is aligned on a 16-bit boundary.\r | |
459 | //\r | |
460 | ASSERT ((Port & 1) == 0);\r | |
461 | IoReadFifoWorker (Port, EfiPeiCpuIoWidthFifoUint16, Count, Buffer);\r | |
462 | }\r | |
463 | \r | |
464 | /**\r | |
465 | Writes a block of memory into a 16-bit I/O port fifo.\r | |
466 | \r | |
467 | Writes the 16-bit I/O fifo port specified by Port.\r | |
468 | The port is written Count times, and the write data is\r | |
469 | retrieved from the provided Buffer.\r | |
470 | \r | |
471 | This function must guarantee that all I/O write and write operations are\r | |
472 | serialized.\r | |
473 | \r | |
474 | If 16-bit I/O port operations are not supported, then ASSERT().\r | |
475 | \r | |
476 | @param Port The I/O port to write.\r | |
477 | @param Count The number of times to write I/O port.\r | |
478 | @param Buffer The buffer to retrieve the write data from.\r | |
479 | \r | |
480 | **/\r | |
481 | VOID\r | |
482 | EFIAPI\r | |
483 | IoWriteFifo16 (\r | |
484 | IN UINTN Port,\r | |
485 | IN UINTN Count,\r | |
486 | IN VOID *Buffer\r | |
487 | )\r | |
488 | {\r | |
489 | //\r | |
490 | // Make sure Port is aligned on a 16-bit boundary.\r | |
491 | //\r | |
492 | ASSERT ((Port & 1) == 0);\r | |
493 | IoWriteFifoWorker (Port, EfiPeiCpuIoWidthFifoUint16, Count, Buffer);\r | |
494 | }\r | |
495 | \r | |
496 | /**\r | |
497 | Reads a 32-bit I/O port fifo into a block of memory.\r | |
498 | \r | |
499 | Reads the 32-bit I/O fifo port specified by Port.\r | |
500 | The port is read Count times, and the read data is\r | |
501 | stored in the provided Buffer.\r | |
502 | \r | |
503 | This function must guarantee that all I/O read and write operations are\r | |
504 | serialized.\r | |
505 | \r | |
506 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
507 | \r | |
508 | @param Port The I/O port to read.\r | |
509 | @param Count The number of times to read I/O port.\r | |
510 | @param Buffer The buffer to store the read data into.\r | |
511 | \r | |
512 | **/\r | |
513 | VOID\r | |
514 | EFIAPI\r | |
515 | IoReadFifo32 (\r | |
516 | IN UINTN Port,\r | |
517 | IN UINTN Count,\r | |
518 | OUT VOID *Buffer\r | |
519 | )\r | |
520 | {\r | |
521 | //\r | |
522 | // Make sure Port is aligned on a 32-bit boundary.\r | |
523 | //\r | |
524 | ASSERT ((Port & 3) == 0);\r | |
525 | IoReadFifoWorker (Port, EfiPeiCpuIoWidthFifoUint32, Count, Buffer);\r | |
526 | }\r | |
527 | \r | |
528 | /**\r | |
529 | Writes a block of memory into a 32-bit I/O port fifo.\r | |
530 | \r | |
531 | Writes the 32-bit I/O fifo port specified by Port.\r | |
532 | The port is written Count times, and the write data is\r | |
533 | retrieved from the provided Buffer.\r | |
534 | \r | |
535 | This function must guarantee that all I/O write and write operations are\r | |
536 | serialized.\r | |
537 | \r | |
538 | If 32-bit I/O port operations are not supported, then ASSERT().\r | |
539 | \r | |
540 | @param Port The I/O port to write.\r | |
541 | @param Count The number of times to write I/O port.\r | |
542 | @param Buffer The buffer to retrieve the write data from.\r | |
543 | \r | |
544 | **/\r | |
545 | VOID\r | |
546 | EFIAPI\r | |
547 | IoWriteFifo32 (\r | |
548 | IN UINTN Port,\r | |
549 | IN UINTN Count,\r | |
550 | IN VOID *Buffer\r | |
551 | )\r | |
552 | {\r | |
553 | //\r | |
554 | // Make sure Port is aligned on a 32-bit boundary.\r | |
555 | //\r | |
556 | ASSERT ((Port & 3) == 0);\r | |
557 | IoWriteFifoWorker (Port, EfiPeiCpuIoWidthFifoUint32, Count, Buffer);\r | |
558 | }\r | |
559 | \r | |
11f43dfd | 560 | /**\r |
561 | Reads an 8-bit MMIO register.\r | |
562 | \r | |
563 | Reads the 8-bit MMIO register specified by Address. The 8-bit read value is\r | |
564 | returned. This function must guarantee that all MMIO read and write\r | |
565 | operations are serialized.\r | |
566 | \r | |
567 | If 8-bit MMIO register operations are not supported, then ASSERT().\r | |
568 | \r | |
569 | @param Address The MMIO register to read.\r | |
570 | \r | |
80f0c0c4 | 571 | @return The value read.\r |
11f43dfd | 572 | \r |
573 | **/\r | |
574 | UINT8\r | |
575 | EFIAPI\r | |
576 | MmioRead8 (\r | |
577 | IN UINTN Address\r | |
578 | )\r | |
579 | {\r | |
fe7fd578 | 580 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 581 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
582 | \r | |
5240b97c | 583 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 584 | CpuIo = (*PeiServices)->CpuIo;\r |
585 | ASSERT (CpuIo != NULL);\r | |
586 | \r | |
587 | return CpuIo->MemRead8 (PeiServices, CpuIo, (UINT64) Address);\r | |
588 | }\r | |
589 | \r | |
590 | /**\r | |
591 | Writes an 8-bit MMIO register.\r | |
592 | \r | |
593 | Writes the 8-bit MMIO register specified by Address with the value specified\r | |
594 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
595 | and write operations are serialized.\r | |
596 | \r | |
597 | If 8-bit MMIO register operations are not supported, then ASSERT().\r | |
598 | \r | |
599 | @param Address The MMIO register to write.\r | |
600 | @param Value The value to write to the MMIO register.\r | |
9095d37b | 601 | \r |
4ef55dfc | 602 | @return Value.\r |
80f0c0c4 | 603 | \r |
11f43dfd | 604 | **/\r |
605 | UINT8\r | |
606 | EFIAPI\r | |
607 | MmioWrite8 (\r | |
608 | IN UINTN Address,\r | |
609 | IN UINT8 Value\r | |
610 | )\r | |
611 | {\r | |
fe7fd578 | 612 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 613 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
614 | \r | |
5240b97c | 615 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 616 | CpuIo = (*PeiServices)->CpuIo;\r |
617 | ASSERT (CpuIo != NULL);\r | |
618 | \r | |
619 | CpuIo->MemWrite8 (PeiServices, CpuIo, (UINT64) Address, Value);\r | |
620 | return Value;\r | |
621 | }\r | |
622 | \r | |
623 | /**\r | |
624 | Reads a 16-bit MMIO register.\r | |
625 | \r | |
626 | Reads the 16-bit MMIO register specified by Address. The 16-bit read value is\r | |
627 | returned. This function must guarantee that all MMIO read and write\r | |
628 | operations are serialized.\r | |
629 | \r | |
630 | If 16-bit MMIO register operations are not supported, then ASSERT().\r | |
80f0c0c4 | 631 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
11f43dfd | 632 | \r |
633 | @param Address The MMIO register to read.\r | |
634 | \r | |
80f0c0c4 | 635 | @return The value read.\r |
11f43dfd | 636 | \r |
637 | **/\r | |
638 | UINT16\r | |
639 | EFIAPI\r | |
640 | MmioRead16 (\r | |
641 | IN UINTN Address\r | |
642 | )\r | |
643 | {\r | |
fe7fd578 | 644 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 645 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
646 | \r | |
5240b97c | 647 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 648 | CpuIo = (*PeiServices)->CpuIo;\r |
649 | ASSERT (CpuIo != NULL);\r | |
650 | //\r | |
651 | // Make sure Address is aligned on a 16-bit boundary.\r | |
652 | //\r | |
653 | ASSERT ((Address & 1) == 0);\r | |
654 | return CpuIo->MemRead16 (PeiServices, CpuIo, (UINT64) Address);\r | |
655 | \r | |
656 | }\r | |
657 | \r | |
658 | /**\r | |
659 | Writes a 16-bit MMIO register.\r | |
660 | \r | |
661 | Writes the 16-bit MMIO register specified by Address with the value specified\r | |
662 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
663 | and write operations are serialized.\r | |
664 | \r | |
665 | If 16-bit MMIO register operations are not supported, then ASSERT().\r | |
80f0c0c4 | 666 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
11f43dfd | 667 | \r |
668 | @param Address The MMIO register to write.\r | |
669 | @param Value The value to write to the MMIO register.\r | |
9095d37b | 670 | \r |
4ef55dfc | 671 | @return Value.\r |
11f43dfd | 672 | \r |
673 | **/\r | |
674 | UINT16\r | |
675 | EFIAPI\r | |
676 | MmioWrite16 (\r | |
677 | IN UINTN Address,\r | |
678 | IN UINT16 Value\r | |
679 | )\r | |
680 | {\r | |
fe7fd578 | 681 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 682 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
683 | \r | |
5240b97c | 684 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 685 | CpuIo = (*PeiServices)->CpuIo;\r |
686 | ASSERT (CpuIo != NULL);\r | |
687 | //\r | |
688 | // Make sure Address is aligned on a 16-bit boundary.\r | |
689 | //\r | |
690 | ASSERT ((Address & 1) == 0);\r | |
691 | CpuIo->MemWrite16 (PeiServices, CpuIo, (UINT64) Address, Value);\r | |
692 | return Value;\r | |
693 | }\r | |
694 | \r | |
695 | /**\r | |
696 | Reads a 32-bit MMIO register.\r | |
697 | \r | |
698 | Reads the 32-bit MMIO register specified by Address. The 32-bit read value is\r | |
699 | returned. This function must guarantee that all MMIO read and write\r | |
700 | operations are serialized.\r | |
701 | \r | |
702 | If 32-bit MMIO register operations are not supported, then ASSERT().\r | |
80f0c0c4 | 703 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
11f43dfd | 704 | \r |
705 | @param Address The MMIO register to read.\r | |
706 | \r | |
80f0c0c4 | 707 | @return The value read.\r |
11f43dfd | 708 | \r |
709 | **/\r | |
710 | UINT32\r | |
711 | EFIAPI\r | |
712 | MmioRead32 (\r | |
713 | IN UINTN Address\r | |
714 | )\r | |
715 | {\r | |
fe7fd578 | 716 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 717 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
718 | \r | |
5240b97c | 719 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 720 | CpuIo = (*PeiServices)->CpuIo;\r |
721 | ASSERT (CpuIo != NULL);\r | |
722 | //\r | |
723 | // Make sure Address is aligned on a 32-bit boundary.\r | |
724 | //\r | |
725 | ASSERT ((Address & 3) == 0);\r | |
726 | return CpuIo->MemRead32 (PeiServices, CpuIo, (UINT64) Address);\r | |
727 | \r | |
728 | }\r | |
729 | \r | |
730 | /**\r | |
731 | Writes a 32-bit MMIO register.\r | |
732 | \r | |
733 | Writes the 32-bit MMIO register specified by Address with the value specified\r | |
734 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
735 | and write operations are serialized.\r | |
736 | \r | |
737 | If 32-bit MMIO register operations are not supported, then ASSERT().\r | |
80f0c0c4 | 738 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
11f43dfd | 739 | \r |
740 | @param Address The MMIO register to write.\r | |
741 | @param Value The value to write to the MMIO register.\r | |
9095d37b | 742 | \r |
4ef55dfc | 743 | @return Value.\r |
11f43dfd | 744 | \r |
745 | **/\r | |
746 | UINT32\r | |
747 | EFIAPI\r | |
748 | MmioWrite32 (\r | |
749 | IN UINTN Address,\r | |
750 | IN UINT32 Value\r | |
751 | )\r | |
752 | {\r | |
fe7fd578 | 753 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 754 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
755 | \r | |
5240b97c | 756 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 757 | CpuIo = (*PeiServices)->CpuIo;\r |
758 | ASSERT (CpuIo != NULL);\r | |
759 | //\r | |
760 | // Make sure Address is aligned on a 32-bit boundary.\r | |
761 | //\r | |
762 | ASSERT ((Address & 3) == 0);\r | |
763 | CpuIo->MemWrite32 (PeiServices, CpuIo, (UINT64) Address, Value);\r | |
764 | return Value;\r | |
765 | }\r | |
766 | \r | |
767 | /**\r | |
768 | Reads a 64-bit MMIO register.\r | |
769 | \r | |
770 | Reads the 64-bit MMIO register specified by Address. The 64-bit read value is\r | |
771 | returned. This function must guarantee that all MMIO read and write\r | |
772 | operations are serialized.\r | |
773 | \r | |
774 | If 64-bit MMIO register operations are not supported, then ASSERT().\r | |
80f0c0c4 | 775 | If Address is not aligned on a 64-bit boundary, then ASSERT().\r |
11f43dfd | 776 | \r |
777 | @param Address The MMIO register to read.\r | |
778 | \r | |
80f0c0c4 | 779 | @return The value read.\r |
11f43dfd | 780 | \r |
781 | **/\r | |
782 | UINT64\r | |
783 | EFIAPI\r | |
784 | MmioRead64 (\r | |
785 | IN UINTN Address\r | |
786 | )\r | |
787 | {\r | |
fe7fd578 | 788 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 789 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
790 | \r | |
5240b97c | 791 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 792 | CpuIo = (*PeiServices)->CpuIo;\r |
793 | ASSERT (CpuIo != NULL);\r | |
794 | //\r | |
795 | // Make sure Address is aligned on a 64-bit boundary.\r | |
796 | //\r | |
4efb2b4d | 797 | ASSERT ((Address & (sizeof (UINT64) - 1)) == 0);\r |
11f43dfd | 798 | return CpuIo->MemRead64 (PeiServices, CpuIo, (UINT64) Address);\r |
799 | \r | |
800 | }\r | |
801 | \r | |
802 | /**\r | |
803 | Writes a 64-bit MMIO register.\r | |
804 | \r | |
805 | Writes the 64-bit MMIO register specified by Address with the value specified\r | |
806 | by Value and returns Value. This function must guarantee that all MMIO read\r | |
807 | and write operations are serialized.\r | |
808 | \r | |
809 | If 64-bit MMIO register operations are not supported, then ASSERT().\r | |
80f0c0c4 | 810 | If Address is not aligned on a 64-bit boundary, then ASSERT().\r |
11f43dfd | 811 | \r |
812 | @param Address The MMIO register to write.\r | |
813 | @param Value The value to write to the MMIO register.\r | |
814 | \r | |
815 | **/\r | |
816 | UINT64\r | |
817 | EFIAPI\r | |
818 | MmioWrite64 (\r | |
819 | IN UINTN Address,\r | |
820 | IN UINT64 Value\r | |
821 | )\r | |
822 | {\r | |
fe7fd578 | 823 | CONST EFI_PEI_SERVICES **PeiServices;\r |
11f43dfd | 824 | EFI_PEI_CPU_IO_PPI *CpuIo;\r |
825 | \r | |
5240b97c | 826 | PeiServices = GetPeiServicesTablePointer ();\r |
11f43dfd | 827 | CpuIo = (*PeiServices)->CpuIo;\r |
828 | ASSERT (CpuIo != NULL);\r | |
829 | //\r | |
830 | // Make sure Address is aligned on a 64-bit boundary.\r | |
831 | //\r | |
832 | ASSERT ((Address & 7) == 0);\r | |
833 | CpuIo->MemWrite64 (PeiServices, CpuIo, (UINT64) Address, Value);\r | |
834 | return Value;\r | |
835 | }\r |