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43263288 | 1 | /** @file\r |
2 | Debug Agent timer lib for OMAP 35xx.\r | |
3 | \r | |
3d70643b | 4 | Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>\r |
3402aac7 | 5 | \r |
3d70643b | 6 | This program and the accompanying materials\r |
43263288 | 7 | are licensed and made available under the terms and conditions of the BSD License\r |
8 | which accompanies this distribution. The full text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | #include <Base.h>\r | |
1e57a462 | 16 | #include <Library/BaseLib.h>\r |
17 | #include <Library/IoLib.h>\r | |
18 | #include <Library/OmapLib.h>\r | |
43263288 | 19 | #include <Library/ArmLib.h>\r |
1e57a462 | 20 | #include <Library/PcdLib.h>\r |
43263288 | 21 | \r |
1e57a462 | 22 | #include <Omap3530/Omap3530.h>\r |
43263288 | 23 | \r |
24 | \r | |
25 | volatile UINT32 gVector;\r | |
1e57a462 | 26 | \r |
27 | // Cached registers\r | |
28 | volatile UINT32 gTISR;\r | |
29 | volatile UINT32 gTCLR;\r | |
30 | volatile UINT32 gTLDR;\r | |
31 | volatile UINT32 gTCRR;\r | |
32 | volatile UINT32 gTIER;\r | |
43263288 | 33 | \r |
34 | VOID\r | |
35 | EnableInterruptSource (\r | |
36 | VOID\r | |
37 | )\r | |
38 | {\r | |
39 | UINTN Bank;\r | |
40 | UINTN Bit;\r | |
41 | \r | |
42 | // Map vector to FIQ, IRQ is default\r | |
43 | MmioWrite32 (INTCPS_ILR (gVector), 1);\r | |
44 | \r | |
45 | Bank = gVector / 32;\r | |
46 | Bit = 1UL << (gVector % 32);\r | |
3402aac7 | 47 | \r |
43263288 | 48 | MmioWrite32 (INTCPS_MIR_CLEAR(Bank), Bit);\r |
49 | }\r | |
50 | \r | |
51 | VOID\r | |
52 | DisableInterruptSource (\r | |
53 | VOID\r | |
54 | )\r | |
55 | {\r | |
56 | UINTN Bank;\r | |
57 | UINTN Bit;\r | |
3402aac7 | 58 | \r |
43263288 | 59 | Bank = gVector / 32;\r |
3402aac7 | 60 | Bit = 1UL << (gVector % 32);\r |
43263288 | 61 | \r |
62 | MmioWrite32 (INTCPS_MIR_SET(Bank), Bit);\r | |
63 | }\r | |
64 | \r | |
65 | \r | |
66 | \r | |
67 | /**\r | |
68 | Setup all the hardware needed for the debug agents timer.\r | |
69 | \r | |
70 | This function is used to set up debug enviroment. It may enable interrupts.\r | |
71 | \r | |
72 | **/\r | |
73 | VOID\r | |
74 | EFIAPI\r | |
75 | DebugAgentTimerIntialize (\r | |
76 | VOID\r | |
77 | )\r | |
78 | {\r | |
79 | UINT32 TimerBaseAddress;\r | |
9e4f210c | 80 | UINT32 TimerNumber;\r |
43263288 | 81 | \r |
9e4f210c | 82 | TimerNumber = PcdGet32(PcdOmap35xxDebugAgentTimer);\r |
1e57a462 | 83 | gVector = InterruptVectorForTimer (TimerNumber);\r |
43263288 | 84 | \r |
1e57a462 | 85 | // Set up the timer registers\r |
86 | TimerBaseAddress = TimerBase (TimerNumber);\r | |
87 | gTISR = TimerBaseAddress + GPTIMER_TISR;\r | |
88 | gTCLR = TimerBaseAddress + GPTIMER_TCLR;\r | |
89 | gTLDR = TimerBaseAddress + GPTIMER_TLDR;\r | |
90 | gTCRR = TimerBaseAddress + GPTIMER_TCRR;\r | |
91 | gTIER = TimerBaseAddress + GPTIMER_TIER;\r | |
43263288 | 92 | \r |
9e4f210c | 93 | if ((TimerNumber < 2) || (TimerNumber > 9)) {\r |
94 | // This code assumes one the General Purpose timers is used\r | |
95 | // GPT2 - GPT9\r | |
96 | CpuDeadLoop ();\r | |
97 | }\r | |
98 | // Set source clock for GPT2 - GPT9 to SYS_CLK\r | |
3402aac7 | 99 | MmioOr32 (CM_CLKSEL_PER, 1 << (TimerNumber - 2));\r |
9e4f210c | 100 | \r |
43263288 | 101 | }\r |
3402aac7 RC |
102 | \r |
103 | \r | |
43263288 | 104 | /**\r |
105 | Set the period for the debug agent timer. Zero means disable the timer.\r | |
106 | \r | |
107 | @param[in] TimerPeriodMilliseconds Frequency of the debug agent timer.\r | |
108 | \r | |
3402aac7 | 109 | **/\r |
43263288 | 110 | VOID\r |
111 | EFIAPI\r | |
112 | DebugAgentTimerSetPeriod (\r | |
113 | IN UINT32 TimerPeriodMilliseconds\r | |
114 | )\r | |
115 | {\r | |
1e57a462 | 116 | UINT64 TimerCount;\r |
117 | INT32 LoadValue;\r | |
3402aac7 | 118 | \r |
1e57a462 | 119 | if (TimerPeriodMilliseconds == 0) {\r |
120 | // Turn off GPTIMER3\r | |
121 | MmioWrite32 (gTCLR, TCLR_ST_OFF);\r | |
3402aac7 | 122 | \r |
1e57a462 | 123 | DisableInterruptSource ();\r |
3402aac7 | 124 | } else {\r |
1e57a462 | 125 | // Calculate required timer count\r |
126 | TimerCount = DivU64x32(TimerPeriodMilliseconds * 1000000, PcdGet32(PcdDebugAgentTimerFreqNanoSeconds));\r | |
127 | \r | |
128 | // Set GPTIMER5 Load register\r | |
129 | LoadValue = (INT32) -TimerCount;\r | |
130 | MmioWrite32 (gTLDR, LoadValue);\r | |
131 | MmioWrite32 (gTCRR, LoadValue);\r | |
132 | \r | |
133 | // Enable Overflow interrupt\r | |
134 | MmioWrite32 (gTIER, TIER_TCAR_IT_DISABLE | TIER_OVF_IT_ENABLE | TIER_MAT_IT_DISABLE);\r | |
135 | \r | |
136 | // Turn on GPTIMER3, it will reload at overflow\r | |
137 | MmioWrite32 (gTCLR, TCLR_AR_AUTORELOAD | TCLR_ST_ON);\r | |
138 | \r | |
139 | EnableInterruptSource ();\r | |
140 | }\r | |
43263288 | 141 | }\r |
3402aac7 | 142 | \r |
43263288 | 143 | \r |
144 | /**\r | |
3402aac7 RC |
145 | Perform End Of Interrupt for the debug agent timer. This is called in the\r |
146 | interrupt handler after the interrupt has been processed.\r | |
43263288 | 147 | \r |
3402aac7 | 148 | **/\r |
43263288 | 149 | VOID\r |
150 | EFIAPI\r | |
151 | DebugAgentTimerEndOfInterrupt (\r | |
152 | VOID\r | |
153 | )\r | |
154 | {\r | |
1e57a462 | 155 | // Clear all timer interrupts\r |
3402aac7 | 156 | MmioWrite32 (gTISR, TISR_CLEAR_ALL);\r |
1e57a462 | 157 | \r |
158 | // Poll interrupt status bits to ensure clearing\r | |
43263288 | 159 | while ((MmioRead32 (gTISR) & TISR_ALL_INTERRUPT_MASK) != TISR_NO_INTERRUPTS_PENDING);\r |
160 | \r | |
161 | MmioWrite32 (INTCPS_CONTROL, INTCPS_CONTROL_NEWFIQAGR);\r | |
cf93a378 | 162 | ArmDataSynchronizationBarrier ();\r |
43263288 | 163 | \r |
164 | }\r | |
9e4f210c | 165 | \r |