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ad3359eb LE |
1 | /** @file\r |
2 | Functions in this library instance make use of MMIO functions in IoLib to\r | |
3 | access memory mapped PCI configuration space.\r | |
4 | \r | |
5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
6 | Library.\r | |
7 | \r | |
8 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r | |
9792fb0e | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
ad3359eb LE |
10 | \r |
11 | **/\r | |
12 | \r | |
ad3359eb LE |
13 | #include <Base.h>\r |
14 | \r | |
15 | #include <Library/BaseLib.h>\r | |
16 | #include <Library/PciExpressLib.h>\r | |
17 | #include <Library/IoLib.h>\r | |
18 | #include <Library/DebugLib.h>\r | |
19 | #include <Library/PcdLib.h>\r | |
20 | \r | |
ad3359eb LE |
21 | /**\r |
22 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
23 | only in the low 28 bits.\r | |
24 | \r | |
25 | @param A The address to validate.\r | |
26 | \r | |
27 | **/\r | |
28 | #define ASSERT_INVALID_PCI_ADDRESS(A) \\r | |
29 | ASSERT (((A) & ~0xfffffff) == 0)\r | |
30 | \r | |
31 | /**\r | |
d1c561f9 | 32 | Registers a PCI device so PCI configuration registers may be accessed after\r |
ad3359eb | 33 | SetVirtualAddressMap().\r |
d1c561f9 OM |
34 | \r |
35 | Registers the PCI device specified by Address so all the PCI configuration\r | |
36 | registers associated with that PCI device may be accessed after SetVirtualAddressMap()\r | |
ad3359eb | 37 | is called.\r |
d1c561f9 | 38 | \r |
ad3359eb LE |
39 | If Address > 0x0FFFFFFF, then ASSERT().\r |
40 | \r | |
41 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
42 | Register.\r | |
d1c561f9 | 43 | \r |
ad3359eb | 44 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
d1c561f9 | 45 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
ad3359eb LE |
46 | after ExitBootServices().\r |
47 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
48 | at runtime could not be mapped.\r | |
49 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
50 | complete the registration.\r | |
51 | \r | |
52 | **/\r | |
53 | RETURN_STATUS\r | |
54 | EFIAPI\r | |
55 | PciExpressRegisterForRuntimeAccess (\r | |
56 | IN UINTN Address\r | |
57 | )\r | |
58 | {\r | |
59 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
60 | return RETURN_UNSUPPORTED;\r | |
61 | }\r | |
62 | \r | |
2b16a4fb | 63 | STATIC UINT64 mPciExpressBaseAddress;\r |
ad3359eb LE |
64 | \r |
65 | RETURN_STATUS\r | |
66 | EFIAPI\r | |
67 | PciExpressLibInitialize (\r | |
68 | VOID\r | |
69 | )\r | |
70 | {\r | |
71 | mPciExpressBaseAddress = PcdGet64 (PcdPciExpressBaseAddress);\r | |
72 | return RETURN_SUCCESS;\r | |
73 | }\r | |
74 | \r | |
ad3359eb LE |
75 | /**\r |
76 | Gets the base address of PCI Express.\r | |
d1c561f9 | 77 | \r |
ad3359eb LE |
78 | @return The base address of PCI Express.\r |
79 | \r | |
80 | **/\r | |
2b16a4fb | 81 | VOID *\r |
ad3359eb LE |
82 | GetPciExpressBaseAddress (\r |
83 | VOID\r | |
84 | )\r | |
85 | {\r | |
2b16a4fb | 86 | return (VOID *)(UINTN)mPciExpressBaseAddress;\r |
ad3359eb LE |
87 | }\r |
88 | \r | |
89 | /**\r | |
90 | Reads an 8-bit PCI configuration register.\r | |
91 | \r | |
92 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
93 | This function must guarantee that all PCI read and write operations are\r | |
94 | serialized.\r | |
95 | \r | |
96 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
97 | \r | |
98 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
99 | Register.\r | |
100 | \r | |
101 | @return The read value from the PCI configuration register.\r | |
102 | \r | |
103 | **/\r | |
104 | UINT8\r | |
105 | EFIAPI\r | |
106 | PciExpressRead8 (\r | |
2b16a4fb | 107 | IN UINTN Address\r |
ad3359eb LE |
108 | )\r |
109 | {\r | |
110 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 111 | return MmioRead8 ((UINTN)GetPciExpressBaseAddress () + Address);\r |
ad3359eb LE |
112 | }\r |
113 | \r | |
114 | /**\r | |
115 | Writes an 8-bit PCI configuration register.\r | |
116 | \r | |
117 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
118 | value specified by Value. Value is returned. This function must guarantee\r | |
119 | that all PCI read and write operations are serialized.\r | |
120 | \r | |
121 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
122 | \r | |
123 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
124 | Register.\r | |
125 | @param Value The value to write.\r | |
126 | \r | |
127 | @return The value written to the PCI configuration register.\r | |
128 | \r | |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | PciExpressWrite8 (\r | |
2b16a4fb MK |
133 | IN UINTN Address,\r |
134 | IN UINT8 Value\r | |
ad3359eb LE |
135 | )\r |
136 | {\r | |
137 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 138 | return MmioWrite8 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r |
ad3359eb LE |
139 | }\r |
140 | \r | |
141 | /**\r | |
142 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
143 | an 8-bit value.\r | |
144 | \r | |
145 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
146 | bitwise OR between the read result and the value specified by\r | |
147 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
148 | specified by Address. The value written to the PCI configuration register is\r | |
149 | returned. This function must guarantee that all PCI read and write operations\r | |
150 | are serialized.\r | |
151 | \r | |
152 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
153 | \r | |
154 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
155 | Register.\r | |
156 | @param OrData The value to OR with the PCI configuration register.\r | |
157 | \r | |
158 | @return The value written back to the PCI configuration register.\r | |
159 | \r | |
160 | **/\r | |
161 | UINT8\r | |
162 | EFIAPI\r | |
163 | PciExpressOr8 (\r | |
2b16a4fb MK |
164 | IN UINTN Address,\r |
165 | IN UINT8 OrData\r | |
ad3359eb LE |
166 | )\r |
167 | {\r | |
168 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 169 | return MmioOr8 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r |
ad3359eb LE |
170 | }\r |
171 | \r | |
172 | /**\r | |
173 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
174 | value.\r | |
175 | \r | |
176 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
177 | bitwise AND between the read result and the value specified by AndData, and\r | |
178 | writes the result to the 8-bit PCI configuration register specified by\r | |
179 | Address. The value written to the PCI configuration register is returned.\r | |
180 | This function must guarantee that all PCI read and write operations are\r | |
181 | serialized.\r | |
182 | \r | |
183 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
184 | \r | |
185 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
186 | Register.\r | |
187 | @param AndData The value to AND with the PCI configuration register.\r | |
188 | \r | |
189 | @return The value written back to the PCI configuration register.\r | |
190 | \r | |
191 | **/\r | |
192 | UINT8\r | |
193 | EFIAPI\r | |
194 | PciExpressAnd8 (\r | |
2b16a4fb MK |
195 | IN UINTN Address,\r |
196 | IN UINT8 AndData\r | |
ad3359eb LE |
197 | )\r |
198 | {\r | |
199 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 200 | return MmioAnd8 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r |
ad3359eb LE |
201 | }\r |
202 | \r | |
203 | /**\r | |
204 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
205 | value, followed a bitwise OR with another 8-bit value.\r | |
206 | \r | |
207 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
208 | bitwise AND between the read result and the value specified by AndData,\r | |
209 | performs a bitwise OR between the result of the AND operation and\r | |
210 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
211 | configuration register specified by Address. The value written to the PCI\r | |
212 | configuration register is returned. This function must guarantee that all PCI\r | |
213 | read and write operations are serialized.\r | |
214 | \r | |
215 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
216 | \r | |
217 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
218 | Register.\r | |
219 | @param AndData The value to AND with the PCI configuration register.\r | |
220 | @param OrData The value to OR with the result of the AND operation.\r | |
221 | \r | |
222 | @return The value written back to the PCI configuration register.\r | |
223 | \r | |
224 | **/\r | |
225 | UINT8\r | |
226 | EFIAPI\r | |
227 | PciExpressAndThenOr8 (\r | |
2b16a4fb MK |
228 | IN UINTN Address,\r |
229 | IN UINT8 AndData,\r | |
230 | IN UINT8 OrData\r | |
ad3359eb LE |
231 | )\r |
232 | {\r | |
233 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
234 | return MmioAndThenOr8 (\r | |
2b16a4fb | 235 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
236 | AndData,\r |
237 | OrData\r | |
238 | );\r | |
239 | }\r | |
240 | \r | |
241 | /**\r | |
242 | Reads a bit field of a PCI configuration register.\r | |
243 | \r | |
244 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
245 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
246 | returned.\r | |
247 | \r | |
248 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
249 | If StartBit is greater than 7, then ASSERT().\r | |
250 | If EndBit is greater than 7, then ASSERT().\r | |
251 | If EndBit is less than StartBit, then ASSERT().\r | |
252 | \r | |
253 | @param Address The PCI configuration register to read.\r | |
254 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
255 | Range 0..7.\r | |
256 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
257 | Range 0..7.\r | |
258 | \r | |
259 | @return The value of the bit field read from the PCI configuration register.\r | |
260 | \r | |
261 | **/\r | |
262 | UINT8\r | |
263 | EFIAPI\r | |
264 | PciExpressBitFieldRead8 (\r | |
2b16a4fb MK |
265 | IN UINTN Address,\r |
266 | IN UINTN StartBit,\r | |
267 | IN UINTN EndBit\r | |
ad3359eb LE |
268 | )\r |
269 | {\r | |
270 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
271 | return MmioBitFieldRead8 (\r | |
2b16a4fb | 272 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
273 | StartBit,\r |
274 | EndBit\r | |
275 | );\r | |
276 | }\r | |
277 | \r | |
278 | /**\r | |
279 | Writes a bit field to a PCI configuration register.\r | |
280 | \r | |
281 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
282 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
283 | destination PCI configuration register are preserved. The new value of the\r | |
284 | 8-bit register is returned.\r | |
285 | \r | |
286 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
287 | If StartBit is greater than 7, then ASSERT().\r | |
288 | If EndBit is greater than 7, then ASSERT().\r | |
289 | If EndBit is less than StartBit, then ASSERT().\r | |
290 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
291 | \r | |
292 | @param Address The PCI configuration register to write.\r | |
293 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
294 | Range 0..7.\r | |
295 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
296 | Range 0..7.\r | |
297 | @param Value The new value of the bit field.\r | |
298 | \r | |
299 | @return The value written back to the PCI configuration register.\r | |
300 | \r | |
301 | **/\r | |
302 | UINT8\r | |
303 | EFIAPI\r | |
304 | PciExpressBitFieldWrite8 (\r | |
2b16a4fb MK |
305 | IN UINTN Address,\r |
306 | IN UINTN StartBit,\r | |
307 | IN UINTN EndBit,\r | |
308 | IN UINT8 Value\r | |
ad3359eb LE |
309 | )\r |
310 | {\r | |
311 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
312 | return MmioBitFieldWrite8 (\r | |
2b16a4fb | 313 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
314 | StartBit,\r |
315 | EndBit,\r | |
316 | Value\r | |
317 | );\r | |
318 | }\r | |
319 | \r | |
320 | /**\r | |
321 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
322 | writes the result back to the bit field in the 8-bit port.\r | |
323 | \r | |
324 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
325 | bitwise OR between the read result and the value specified by\r | |
326 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
327 | specified by Address. The value written to the PCI configuration register is\r | |
328 | returned. This function must guarantee that all PCI read and write operations\r | |
329 | are serialized. Extra left bits in OrData are stripped.\r | |
330 | \r | |
331 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
332 | If StartBit is greater than 7, then ASSERT().\r | |
333 | If EndBit is greater than 7, then ASSERT().\r | |
334 | If EndBit is less than StartBit, then ASSERT().\r | |
335 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
336 | \r | |
337 | @param Address The PCI configuration register to write.\r | |
338 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
339 | Range 0..7.\r | |
340 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
341 | Range 0..7.\r | |
342 | @param OrData The value to OR with the PCI configuration register.\r | |
343 | \r | |
344 | @return The value written back to the PCI configuration register.\r | |
345 | \r | |
346 | **/\r | |
347 | UINT8\r | |
348 | EFIAPI\r | |
349 | PciExpressBitFieldOr8 (\r | |
2b16a4fb MK |
350 | IN UINTN Address,\r |
351 | IN UINTN StartBit,\r | |
352 | IN UINTN EndBit,\r | |
353 | IN UINT8 OrData\r | |
ad3359eb LE |
354 | )\r |
355 | {\r | |
356 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
357 | return MmioBitFieldOr8 (\r | |
2b16a4fb | 358 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
359 | StartBit,\r |
360 | EndBit,\r | |
361 | OrData\r | |
362 | );\r | |
363 | }\r | |
364 | \r | |
365 | /**\r | |
366 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
367 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
368 | \r | |
369 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
370 | bitwise AND between the read result and the value specified by AndData, and\r | |
371 | writes the result to the 8-bit PCI configuration register specified by\r | |
372 | Address. The value written to the PCI configuration register is returned.\r | |
373 | This function must guarantee that all PCI read and write operations are\r | |
374 | serialized. Extra left bits in AndData are stripped.\r | |
375 | \r | |
376 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
377 | If StartBit is greater than 7, then ASSERT().\r | |
378 | If EndBit is greater than 7, then ASSERT().\r | |
379 | If EndBit is less than StartBit, then ASSERT().\r | |
380 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
381 | \r | |
382 | @param Address The PCI configuration register to write.\r | |
383 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
384 | Range 0..7.\r | |
385 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
386 | Range 0..7.\r | |
387 | @param AndData The value to AND with the PCI configuration register.\r | |
388 | \r | |
389 | @return The value written back to the PCI configuration register.\r | |
390 | \r | |
391 | **/\r | |
392 | UINT8\r | |
393 | EFIAPI\r | |
394 | PciExpressBitFieldAnd8 (\r | |
2b16a4fb MK |
395 | IN UINTN Address,\r |
396 | IN UINTN StartBit,\r | |
397 | IN UINTN EndBit,\r | |
398 | IN UINT8 AndData\r | |
ad3359eb LE |
399 | )\r |
400 | {\r | |
401 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
402 | return MmioBitFieldAnd8 (\r | |
2b16a4fb | 403 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
404 | StartBit,\r |
405 | EndBit,\r | |
406 | AndData\r | |
407 | );\r | |
408 | }\r | |
409 | \r | |
410 | /**\r | |
411 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
412 | bitwise OR, and writes the result back to the bit field in the\r | |
413 | 8-bit port.\r | |
414 | \r | |
415 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
416 | bitwise AND followed by a bitwise OR between the read result and\r | |
417 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
418 | configuration register specified by Address. The value written to the PCI\r | |
419 | configuration register is returned. This function must guarantee that all PCI\r | |
420 | read and write operations are serialized. Extra left bits in both AndData and\r | |
421 | OrData are stripped.\r | |
422 | \r | |
423 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
424 | If StartBit is greater than 7, then ASSERT().\r | |
425 | If EndBit is greater than 7, then ASSERT().\r | |
426 | If EndBit is less than StartBit, then ASSERT().\r | |
427 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
428 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
429 | \r | |
430 | @param Address The PCI configuration register to write.\r | |
431 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
432 | Range 0..7.\r | |
433 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
434 | Range 0..7.\r | |
435 | @param AndData The value to AND with the PCI configuration register.\r | |
436 | @param OrData The value to OR with the result of the AND operation.\r | |
437 | \r | |
438 | @return The value written back to the PCI configuration register.\r | |
439 | \r | |
440 | **/\r | |
441 | UINT8\r | |
442 | EFIAPI\r | |
443 | PciExpressBitFieldAndThenOr8 (\r | |
2b16a4fb MK |
444 | IN UINTN Address,\r |
445 | IN UINTN StartBit,\r | |
446 | IN UINTN EndBit,\r | |
447 | IN UINT8 AndData,\r | |
448 | IN UINT8 OrData\r | |
ad3359eb LE |
449 | )\r |
450 | {\r | |
451 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
452 | return MmioBitFieldAndThenOr8 (\r | |
2b16a4fb | 453 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
454 | StartBit,\r |
455 | EndBit,\r | |
456 | AndData,\r | |
457 | OrData\r | |
458 | );\r | |
459 | }\r | |
460 | \r | |
461 | /**\r | |
462 | Reads a 16-bit PCI configuration register.\r | |
463 | \r | |
464 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
465 | This function must guarantee that all PCI read and write operations are\r | |
466 | serialized.\r | |
467 | \r | |
468 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
469 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
470 | \r | |
471 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
472 | Register.\r | |
473 | \r | |
474 | @return The read value from the PCI configuration register.\r | |
475 | \r | |
476 | **/\r | |
477 | UINT16\r | |
478 | EFIAPI\r | |
479 | PciExpressRead16 (\r | |
2b16a4fb | 480 | IN UINTN Address\r |
ad3359eb LE |
481 | )\r |
482 | {\r | |
483 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 484 | return MmioRead16 ((UINTN)GetPciExpressBaseAddress () + Address);\r |
ad3359eb LE |
485 | }\r |
486 | \r | |
487 | /**\r | |
488 | Writes a 16-bit PCI configuration register.\r | |
489 | \r | |
490 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
491 | value specified by Value. Value is returned. This function must guarantee\r | |
492 | that all PCI read and write operations are serialized.\r | |
493 | \r | |
494 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
495 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
496 | \r | |
497 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
498 | Register.\r | |
499 | @param Value The value to write.\r | |
500 | \r | |
501 | @return The value written to the PCI configuration register.\r | |
502 | \r | |
503 | **/\r | |
504 | UINT16\r | |
505 | EFIAPI\r | |
506 | PciExpressWrite16 (\r | |
2b16a4fb MK |
507 | IN UINTN Address,\r |
508 | IN UINT16 Value\r | |
ad3359eb LE |
509 | )\r |
510 | {\r | |
511 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 512 | return MmioWrite16 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r |
ad3359eb LE |
513 | }\r |
514 | \r | |
515 | /**\r | |
516 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
517 | a 16-bit value.\r | |
518 | \r | |
519 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
520 | bitwise OR between the read result and the value specified by\r | |
521 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
522 | specified by Address. The value written to the PCI configuration register is\r | |
523 | returned. This function must guarantee that all PCI read and write operations\r | |
524 | are serialized.\r | |
525 | \r | |
526 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
527 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
528 | \r | |
529 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
530 | Register.\r | |
531 | @param OrData The value to OR with the PCI configuration register.\r | |
532 | \r | |
533 | @return The value written back to the PCI configuration register.\r | |
534 | \r | |
535 | **/\r | |
536 | UINT16\r | |
537 | EFIAPI\r | |
538 | PciExpressOr16 (\r | |
2b16a4fb MK |
539 | IN UINTN Address,\r |
540 | IN UINT16 OrData\r | |
ad3359eb LE |
541 | )\r |
542 | {\r | |
543 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 544 | return MmioOr16 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r |
ad3359eb LE |
545 | }\r |
546 | \r | |
547 | /**\r | |
548 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
549 | value.\r | |
550 | \r | |
551 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
552 | bitwise AND between the read result and the value specified by AndData, and\r | |
553 | writes the result to the 16-bit PCI configuration register specified by\r | |
554 | Address. The value written to the PCI configuration register is returned.\r | |
555 | This function must guarantee that all PCI read and write operations are\r | |
556 | serialized.\r | |
557 | \r | |
558 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
559 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
560 | \r | |
561 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
562 | Register.\r | |
563 | @param AndData The value to AND with the PCI configuration register.\r | |
564 | \r | |
565 | @return The value written back to the PCI configuration register.\r | |
566 | \r | |
567 | **/\r | |
568 | UINT16\r | |
569 | EFIAPI\r | |
570 | PciExpressAnd16 (\r | |
2b16a4fb MK |
571 | IN UINTN Address,\r |
572 | IN UINT16 AndData\r | |
ad3359eb LE |
573 | )\r |
574 | {\r | |
575 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 576 | return MmioAnd16 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r |
ad3359eb LE |
577 | }\r |
578 | \r | |
579 | /**\r | |
580 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
581 | value, followed a bitwise OR with another 16-bit value.\r | |
582 | \r | |
583 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
584 | bitwise AND between the read result and the value specified by AndData,\r | |
585 | performs a bitwise OR between the result of the AND operation and\r | |
586 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
587 | configuration register specified by Address. The value written to the PCI\r | |
588 | configuration register is returned. This function must guarantee that all PCI\r | |
589 | read and write operations are serialized.\r | |
590 | \r | |
591 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
592 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
593 | \r | |
594 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
595 | Register.\r | |
596 | @param AndData The value to AND with the PCI configuration register.\r | |
597 | @param OrData The value to OR with the result of the AND operation.\r | |
598 | \r | |
599 | @return The value written back to the PCI configuration register.\r | |
600 | \r | |
601 | **/\r | |
602 | UINT16\r | |
603 | EFIAPI\r | |
604 | PciExpressAndThenOr16 (\r | |
2b16a4fb MK |
605 | IN UINTN Address,\r |
606 | IN UINT16 AndData,\r | |
607 | IN UINT16 OrData\r | |
ad3359eb LE |
608 | )\r |
609 | {\r | |
610 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
611 | return MmioAndThenOr16 (\r | |
2b16a4fb | 612 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
613 | AndData,\r |
614 | OrData\r | |
615 | );\r | |
616 | }\r | |
617 | \r | |
618 | /**\r | |
619 | Reads a bit field of a PCI configuration register.\r | |
620 | \r | |
621 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
622 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
623 | returned.\r | |
624 | \r | |
625 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
626 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
627 | If StartBit is greater than 15, then ASSERT().\r | |
628 | If EndBit is greater than 15, then ASSERT().\r | |
629 | If EndBit is less than StartBit, then ASSERT().\r | |
630 | \r | |
631 | @param Address The PCI configuration register to read.\r | |
632 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
633 | Range 0..15.\r | |
634 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
635 | Range 0..15.\r | |
636 | \r | |
637 | @return The value of the bit field read from the PCI configuration register.\r | |
638 | \r | |
639 | **/\r | |
640 | UINT16\r | |
641 | EFIAPI\r | |
642 | PciExpressBitFieldRead16 (\r | |
2b16a4fb MK |
643 | IN UINTN Address,\r |
644 | IN UINTN StartBit,\r | |
645 | IN UINTN EndBit\r | |
ad3359eb LE |
646 | )\r |
647 | {\r | |
648 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
649 | return MmioBitFieldRead16 (\r | |
2b16a4fb | 650 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
651 | StartBit,\r |
652 | EndBit\r | |
653 | );\r | |
654 | }\r | |
655 | \r | |
656 | /**\r | |
657 | Writes a bit field to a PCI configuration register.\r | |
658 | \r | |
659 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
660 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
661 | destination PCI configuration register are preserved. The new value of the\r | |
662 | 16-bit register is returned.\r | |
663 | \r | |
664 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
665 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
666 | If StartBit is greater than 15, then ASSERT().\r | |
667 | If EndBit is greater than 15, then ASSERT().\r | |
668 | If EndBit is less than StartBit, then ASSERT().\r | |
669 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
670 | \r | |
671 | @param Address The PCI configuration register to write.\r | |
672 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
673 | Range 0..15.\r | |
674 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
675 | Range 0..15.\r | |
676 | @param Value The new value of the bit field.\r | |
677 | \r | |
678 | @return The value written back to the PCI configuration register.\r | |
679 | \r | |
680 | **/\r | |
681 | UINT16\r | |
682 | EFIAPI\r | |
683 | PciExpressBitFieldWrite16 (\r | |
2b16a4fb MK |
684 | IN UINTN Address,\r |
685 | IN UINTN StartBit,\r | |
686 | IN UINTN EndBit,\r | |
687 | IN UINT16 Value\r | |
ad3359eb LE |
688 | )\r |
689 | {\r | |
690 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
691 | return MmioBitFieldWrite16 (\r | |
2b16a4fb | 692 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
693 | StartBit,\r |
694 | EndBit,\r | |
695 | Value\r | |
696 | );\r | |
697 | }\r | |
698 | \r | |
699 | /**\r | |
700 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
701 | writes the result back to the bit field in the 16-bit port.\r | |
702 | \r | |
703 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
704 | bitwise OR between the read result and the value specified by\r | |
705 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
706 | specified by Address. The value written to the PCI configuration register is\r | |
707 | returned. This function must guarantee that all PCI read and write operations\r | |
708 | are serialized. Extra left bits in OrData are stripped.\r | |
709 | \r | |
710 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
711 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
712 | If StartBit is greater than 15, then ASSERT().\r | |
713 | If EndBit is greater than 15, then ASSERT().\r | |
714 | If EndBit is less than StartBit, then ASSERT().\r | |
715 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
716 | \r | |
717 | @param Address The PCI configuration register to write.\r | |
718 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
719 | Range 0..15.\r | |
720 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
721 | Range 0..15.\r | |
722 | @param OrData The value to OR with the PCI configuration register.\r | |
723 | \r | |
724 | @return The value written back to the PCI configuration register.\r | |
725 | \r | |
726 | **/\r | |
727 | UINT16\r | |
728 | EFIAPI\r | |
729 | PciExpressBitFieldOr16 (\r | |
2b16a4fb MK |
730 | IN UINTN Address,\r |
731 | IN UINTN StartBit,\r | |
732 | IN UINTN EndBit,\r | |
733 | IN UINT16 OrData\r | |
ad3359eb LE |
734 | )\r |
735 | {\r | |
736 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
737 | return MmioBitFieldOr16 (\r | |
2b16a4fb | 738 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
739 | StartBit,\r |
740 | EndBit,\r | |
741 | OrData\r | |
742 | );\r | |
743 | }\r | |
744 | \r | |
745 | /**\r | |
746 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
747 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
748 | \r | |
749 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
750 | bitwise AND between the read result and the value specified by AndData, and\r | |
751 | writes the result to the 16-bit PCI configuration register specified by\r | |
752 | Address. The value written to the PCI configuration register is returned.\r | |
753 | This function must guarantee that all PCI read and write operations are\r | |
754 | serialized. Extra left bits in AndData are stripped.\r | |
755 | \r | |
756 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
757 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
758 | If StartBit is greater than 15, then ASSERT().\r | |
759 | If EndBit is greater than 15, then ASSERT().\r | |
760 | If EndBit is less than StartBit, then ASSERT().\r | |
761 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
762 | \r | |
763 | @param Address The PCI configuration register to write.\r | |
764 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
765 | Range 0..15.\r | |
766 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
767 | Range 0..15.\r | |
768 | @param AndData The value to AND with the PCI configuration register.\r | |
769 | \r | |
770 | @return The value written back to the PCI configuration register.\r | |
771 | \r | |
772 | **/\r | |
773 | UINT16\r | |
774 | EFIAPI\r | |
775 | PciExpressBitFieldAnd16 (\r | |
2b16a4fb MK |
776 | IN UINTN Address,\r |
777 | IN UINTN StartBit,\r | |
778 | IN UINTN EndBit,\r | |
779 | IN UINT16 AndData\r | |
ad3359eb LE |
780 | )\r |
781 | {\r | |
782 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
783 | return MmioBitFieldAnd16 (\r | |
2b16a4fb | 784 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
785 | StartBit,\r |
786 | EndBit,\r | |
787 | AndData\r | |
788 | );\r | |
789 | }\r | |
790 | \r | |
791 | /**\r | |
792 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
793 | bitwise OR, and writes the result back to the bit field in the\r | |
794 | 16-bit port.\r | |
795 | \r | |
796 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
797 | bitwise AND followed by a bitwise OR between the read result and\r | |
798 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
799 | configuration register specified by Address. The value written to the PCI\r | |
800 | configuration register is returned. This function must guarantee that all PCI\r | |
801 | read and write operations are serialized. Extra left bits in both AndData and\r | |
802 | OrData are stripped.\r | |
803 | \r | |
804 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
805 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
806 | If StartBit is greater than 15, then ASSERT().\r | |
807 | If EndBit is greater than 15, then ASSERT().\r | |
808 | If EndBit is less than StartBit, then ASSERT().\r | |
809 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
810 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
811 | \r | |
812 | @param Address The PCI configuration register to write.\r | |
813 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
814 | Range 0..15.\r | |
815 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
816 | Range 0..15.\r | |
817 | @param AndData The value to AND with the PCI configuration register.\r | |
818 | @param OrData The value to OR with the result of the AND operation.\r | |
819 | \r | |
820 | @return The value written back to the PCI configuration register.\r | |
821 | \r | |
822 | **/\r | |
823 | UINT16\r | |
824 | EFIAPI\r | |
825 | PciExpressBitFieldAndThenOr16 (\r | |
2b16a4fb MK |
826 | IN UINTN Address,\r |
827 | IN UINTN StartBit,\r | |
828 | IN UINTN EndBit,\r | |
829 | IN UINT16 AndData,\r | |
830 | IN UINT16 OrData\r | |
ad3359eb LE |
831 | )\r |
832 | {\r | |
833 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
834 | return MmioBitFieldAndThenOr16 (\r | |
2b16a4fb | 835 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
836 | StartBit,\r |
837 | EndBit,\r | |
838 | AndData,\r | |
839 | OrData\r | |
840 | );\r | |
841 | }\r | |
842 | \r | |
843 | /**\r | |
844 | Reads a 32-bit PCI configuration register.\r | |
845 | \r | |
846 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
847 | This function must guarantee that all PCI read and write operations are\r | |
848 | serialized.\r | |
849 | \r | |
850 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
851 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
852 | \r | |
853 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
854 | Register.\r | |
855 | \r | |
856 | @return The read value from the PCI configuration register.\r | |
857 | \r | |
858 | **/\r | |
859 | UINT32\r | |
860 | EFIAPI\r | |
861 | PciExpressRead32 (\r | |
2b16a4fb | 862 | IN UINTN Address\r |
ad3359eb LE |
863 | )\r |
864 | {\r | |
865 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 866 | return MmioRead32 ((UINTN)GetPciExpressBaseAddress () + Address);\r |
ad3359eb LE |
867 | }\r |
868 | \r | |
869 | /**\r | |
870 | Writes a 32-bit PCI configuration register.\r | |
871 | \r | |
872 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
873 | value specified by Value. Value is returned. This function must guarantee\r | |
874 | that all PCI read and write operations are serialized.\r | |
875 | \r | |
876 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
877 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
878 | \r | |
879 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
880 | Register.\r | |
881 | @param Value The value to write.\r | |
882 | \r | |
883 | @return The value written to the PCI configuration register.\r | |
884 | \r | |
885 | **/\r | |
886 | UINT32\r | |
887 | EFIAPI\r | |
888 | PciExpressWrite32 (\r | |
2b16a4fb MK |
889 | IN UINTN Address,\r |
890 | IN UINT32 Value\r | |
ad3359eb LE |
891 | )\r |
892 | {\r | |
893 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 894 | return MmioWrite32 ((UINTN)GetPciExpressBaseAddress () + Address, Value);\r |
ad3359eb LE |
895 | }\r |
896 | \r | |
897 | /**\r | |
898 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
899 | a 32-bit value.\r | |
900 | \r | |
901 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
902 | bitwise OR between the read result and the value specified by\r | |
903 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
904 | specified by Address. The value written to the PCI configuration register is\r | |
905 | returned. This function must guarantee that all PCI read and write operations\r | |
906 | are serialized.\r | |
907 | \r | |
908 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
909 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
910 | \r | |
911 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
912 | Register.\r | |
913 | @param OrData The value to OR with the PCI configuration register.\r | |
914 | \r | |
915 | @return The value written back to the PCI configuration register.\r | |
916 | \r | |
917 | **/\r | |
918 | UINT32\r | |
919 | EFIAPI\r | |
920 | PciExpressOr32 (\r | |
2b16a4fb MK |
921 | IN UINTN Address,\r |
922 | IN UINT32 OrData\r | |
ad3359eb LE |
923 | )\r |
924 | {\r | |
925 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 926 | return MmioOr32 ((UINTN)GetPciExpressBaseAddress () + Address, OrData);\r |
ad3359eb LE |
927 | }\r |
928 | \r | |
929 | /**\r | |
930 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
931 | value.\r | |
932 | \r | |
933 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
934 | bitwise AND between the read result and the value specified by AndData, and\r | |
935 | writes the result to the 32-bit PCI configuration register specified by\r | |
936 | Address. The value written to the PCI configuration register is returned.\r | |
937 | This function must guarantee that all PCI read and write operations are\r | |
938 | serialized.\r | |
939 | \r | |
940 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
941 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
942 | \r | |
943 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
944 | Register.\r | |
945 | @param AndData The value to AND with the PCI configuration register.\r | |
946 | \r | |
947 | @return The value written back to the PCI configuration register.\r | |
948 | \r | |
949 | **/\r | |
950 | UINT32\r | |
951 | EFIAPI\r | |
952 | PciExpressAnd32 (\r | |
2b16a4fb MK |
953 | IN UINTN Address,\r |
954 | IN UINT32 AndData\r | |
ad3359eb LE |
955 | )\r |
956 | {\r | |
957 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
2b16a4fb | 958 | return MmioAnd32 ((UINTN)GetPciExpressBaseAddress () + Address, AndData);\r |
ad3359eb LE |
959 | }\r |
960 | \r | |
961 | /**\r | |
962 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
963 | value, followed a bitwise OR with another 32-bit value.\r | |
964 | \r | |
965 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
966 | bitwise AND between the read result and the value specified by AndData,\r | |
967 | performs a bitwise OR between the result of the AND operation and\r | |
968 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
969 | configuration register specified by Address. The value written to the PCI\r | |
970 | configuration register is returned. This function must guarantee that all PCI\r | |
971 | read and write operations are serialized.\r | |
972 | \r | |
973 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
974 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
975 | \r | |
976 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
977 | Register.\r | |
978 | @param AndData The value to AND with the PCI configuration register.\r | |
979 | @param OrData The value to OR with the result of the AND operation.\r | |
980 | \r | |
981 | @return The value written back to the PCI configuration register.\r | |
982 | \r | |
983 | **/\r | |
984 | UINT32\r | |
985 | EFIAPI\r | |
986 | PciExpressAndThenOr32 (\r | |
2b16a4fb MK |
987 | IN UINTN Address,\r |
988 | IN UINT32 AndData,\r | |
989 | IN UINT32 OrData\r | |
ad3359eb LE |
990 | )\r |
991 | {\r | |
992 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
993 | return MmioAndThenOr32 (\r | |
2b16a4fb | 994 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
995 | AndData,\r |
996 | OrData\r | |
997 | );\r | |
998 | }\r | |
999 | \r | |
1000 | /**\r | |
1001 | Reads a bit field of a PCI configuration register.\r | |
1002 | \r | |
1003 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1004 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1005 | returned.\r | |
1006 | \r | |
1007 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1008 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1009 | If StartBit is greater than 31, then ASSERT().\r | |
1010 | If EndBit is greater than 31, then ASSERT().\r | |
1011 | If EndBit is less than StartBit, then ASSERT().\r | |
1012 | \r | |
1013 | @param Address The PCI configuration register to read.\r | |
1014 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1015 | Range 0..31.\r | |
1016 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1017 | Range 0..31.\r | |
1018 | \r | |
1019 | @return The value of the bit field read from the PCI configuration register.\r | |
1020 | \r | |
1021 | **/\r | |
1022 | UINT32\r | |
1023 | EFIAPI\r | |
1024 | PciExpressBitFieldRead32 (\r | |
2b16a4fb MK |
1025 | IN UINTN Address,\r |
1026 | IN UINTN StartBit,\r | |
1027 | IN UINTN EndBit\r | |
ad3359eb LE |
1028 | )\r |
1029 | {\r | |
1030 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1031 | return MmioBitFieldRead32 (\r | |
2b16a4fb | 1032 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
1033 | StartBit,\r |
1034 | EndBit\r | |
1035 | );\r | |
1036 | }\r | |
1037 | \r | |
1038 | /**\r | |
1039 | Writes a bit field to a PCI configuration register.\r | |
1040 | \r | |
1041 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1042 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1043 | destination PCI configuration register are preserved. The new value of the\r | |
1044 | 32-bit register is returned.\r | |
1045 | \r | |
1046 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1047 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1048 | If StartBit is greater than 31, then ASSERT().\r | |
1049 | If EndBit is greater than 31, then ASSERT().\r | |
1050 | If EndBit is less than StartBit, then ASSERT().\r | |
1051 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1052 | \r | |
1053 | @param Address The PCI configuration register to write.\r | |
1054 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1055 | Range 0..31.\r | |
1056 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1057 | Range 0..31.\r | |
1058 | @param Value The new value of the bit field.\r | |
1059 | \r | |
1060 | @return The value written back to the PCI configuration register.\r | |
1061 | \r | |
1062 | **/\r | |
1063 | UINT32\r | |
1064 | EFIAPI\r | |
1065 | PciExpressBitFieldWrite32 (\r | |
2b16a4fb MK |
1066 | IN UINTN Address,\r |
1067 | IN UINTN StartBit,\r | |
1068 | IN UINTN EndBit,\r | |
1069 | IN UINT32 Value\r | |
ad3359eb LE |
1070 | )\r |
1071 | {\r | |
1072 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1073 | return MmioBitFieldWrite32 (\r | |
2b16a4fb | 1074 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
1075 | StartBit,\r |
1076 | EndBit,\r | |
1077 | Value\r | |
1078 | );\r | |
1079 | }\r | |
1080 | \r | |
1081 | /**\r | |
1082 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1083 | writes the result back to the bit field in the 32-bit port.\r | |
1084 | \r | |
1085 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1086 | bitwise OR between the read result and the value specified by\r | |
1087 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1088 | specified by Address. The value written to the PCI configuration register is\r | |
1089 | returned. This function must guarantee that all PCI read and write operations\r | |
1090 | are serialized. Extra left bits in OrData are stripped.\r | |
1091 | \r | |
1092 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1093 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1094 | If StartBit is greater than 31, then ASSERT().\r | |
1095 | If EndBit is greater than 31, then ASSERT().\r | |
1096 | If EndBit is less than StartBit, then ASSERT().\r | |
1097 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1098 | \r | |
1099 | @param Address The PCI configuration register to write.\r | |
1100 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1101 | Range 0..31.\r | |
1102 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1103 | Range 0..31.\r | |
1104 | @param OrData The value to OR with the PCI configuration register.\r | |
1105 | \r | |
1106 | @return The value written back to the PCI configuration register.\r | |
1107 | \r | |
1108 | **/\r | |
1109 | UINT32\r | |
1110 | EFIAPI\r | |
1111 | PciExpressBitFieldOr32 (\r | |
2b16a4fb MK |
1112 | IN UINTN Address,\r |
1113 | IN UINTN StartBit,\r | |
1114 | IN UINTN EndBit,\r | |
1115 | IN UINT32 OrData\r | |
ad3359eb LE |
1116 | )\r |
1117 | {\r | |
1118 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1119 | return MmioBitFieldOr32 (\r | |
2b16a4fb | 1120 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
1121 | StartBit,\r |
1122 | EndBit,\r | |
1123 | OrData\r | |
1124 | );\r | |
1125 | }\r | |
1126 | \r | |
1127 | /**\r | |
1128 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1129 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1130 | \r | |
1131 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1132 | bitwise AND between the read result and the value specified by AndData, and\r | |
1133 | writes the result to the 32-bit PCI configuration register specified by\r | |
1134 | Address. The value written to the PCI configuration register is returned.\r | |
1135 | This function must guarantee that all PCI read and write operations are\r | |
1136 | serialized. Extra left bits in AndData are stripped.\r | |
1137 | \r | |
1138 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1139 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1140 | If StartBit is greater than 31, then ASSERT().\r | |
1141 | If EndBit is greater than 31, then ASSERT().\r | |
1142 | If EndBit is less than StartBit, then ASSERT().\r | |
1143 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1144 | \r | |
1145 | @param Address The PCI configuration register to write.\r | |
1146 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1147 | Range 0..31.\r | |
1148 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1149 | Range 0..31.\r | |
1150 | @param AndData The value to AND with the PCI configuration register.\r | |
1151 | \r | |
1152 | @return The value written back to the PCI configuration register.\r | |
1153 | \r | |
1154 | **/\r | |
1155 | UINT32\r | |
1156 | EFIAPI\r | |
1157 | PciExpressBitFieldAnd32 (\r | |
2b16a4fb MK |
1158 | IN UINTN Address,\r |
1159 | IN UINTN StartBit,\r | |
1160 | IN UINTN EndBit,\r | |
1161 | IN UINT32 AndData\r | |
ad3359eb LE |
1162 | )\r |
1163 | {\r | |
1164 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1165 | return MmioBitFieldAnd32 (\r | |
2b16a4fb | 1166 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
1167 | StartBit,\r |
1168 | EndBit,\r | |
1169 | AndData\r | |
1170 | );\r | |
1171 | }\r | |
1172 | \r | |
1173 | /**\r | |
1174 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1175 | bitwise OR, and writes the result back to the bit field in the\r | |
1176 | 32-bit port.\r | |
1177 | \r | |
1178 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1179 | bitwise AND followed by a bitwise OR between the read result and\r | |
1180 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1181 | configuration register specified by Address. The value written to the PCI\r | |
1182 | configuration register is returned. This function must guarantee that all PCI\r | |
1183 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1184 | OrData are stripped.\r | |
1185 | \r | |
1186 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1187 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1188 | If StartBit is greater than 31, then ASSERT().\r | |
1189 | If EndBit is greater than 31, then ASSERT().\r | |
1190 | If EndBit is less than StartBit, then ASSERT().\r | |
1191 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1192 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1193 | \r | |
1194 | @param Address The PCI configuration register to write.\r | |
1195 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1196 | Range 0..31.\r | |
1197 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1198 | Range 0..31.\r | |
1199 | @param AndData The value to AND with the PCI configuration register.\r | |
1200 | @param OrData The value to OR with the result of the AND operation.\r | |
1201 | \r | |
1202 | @return The value written back to the PCI configuration register.\r | |
1203 | \r | |
1204 | **/\r | |
1205 | UINT32\r | |
1206 | EFIAPI\r | |
1207 | PciExpressBitFieldAndThenOr32 (\r | |
2b16a4fb MK |
1208 | IN UINTN Address,\r |
1209 | IN UINTN StartBit,\r | |
1210 | IN UINTN EndBit,\r | |
1211 | IN UINT32 AndData,\r | |
1212 | IN UINT32 OrData\r | |
ad3359eb LE |
1213 | )\r |
1214 | {\r | |
1215 | ASSERT_INVALID_PCI_ADDRESS (Address);\r | |
1216 | return MmioBitFieldAndThenOr32 (\r | |
2b16a4fb | 1217 | (UINTN)GetPciExpressBaseAddress () + Address,\r |
ad3359eb LE |
1218 | StartBit,\r |
1219 | EndBit,\r | |
1220 | AndData,\r | |
1221 | OrData\r | |
1222 | );\r | |
1223 | }\r | |
1224 | \r | |
1225 | /**\r | |
1226 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1227 | \r | |
1228 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1229 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1230 | configuration registers from a single PCI function to be read. Size is\r | |
1231 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
7a908953 | 1232 | from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
ad3359eb LE |
1233 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
1234 | end of the range.\r | |
1235 | \r | |
1236 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1237 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1238 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1239 | \r | |
1240 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1241 | Function and Register.\r | |
1242 | @param Size The size in bytes of the transfer.\r | |
1243 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1244 | \r | |
1245 | @return Size read data from StartAddress.\r | |
1246 | \r | |
1247 | **/\r | |
1248 | UINTN\r | |
1249 | EFIAPI\r | |
1250 | PciExpressReadBuffer (\r | |
2b16a4fb MK |
1251 | IN UINTN StartAddress,\r |
1252 | IN UINTN Size,\r | |
1253 | OUT VOID *Buffer\r | |
ad3359eb LE |
1254 | )\r |
1255 | {\r | |
2b16a4fb | 1256 | UINTN ReturnValue;\r |
ad3359eb LE |
1257 | \r |
1258 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1259 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1260 | \r | |
1261 | if (Size == 0) {\r | |
1262 | return Size;\r | |
1263 | }\r | |
1264 | \r | |
1265 | ASSERT (Buffer != NULL);\r | |
1266 | \r | |
1267 | //\r | |
1268 | // Save Size for return\r | |
1269 | //\r | |
1270 | ReturnValue = Size;\r | |
1271 | \r | |
1272 | if ((StartAddress & 1) != 0) {\r | |
1273 | //\r | |
1274 | // Read a byte if StartAddress is byte aligned\r | |
1275 | //\r | |
1276 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
2b16a4fb MK |
1277 | StartAddress += sizeof (UINT8);\r |
1278 | Size -= sizeof (UINT8);\r | |
1279 | Buffer = (UINT8 *)Buffer + 1;\r | |
ad3359eb LE |
1280 | }\r |
1281 | \r | |
2b16a4fb | 1282 | if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r |
ad3359eb LE |
1283 | //\r |
1284 | // Read a word if StartAddress is word aligned\r | |
1285 | //\r | |
2b16a4fb | 1286 | WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r |
ad3359eb LE |
1287 | \r |
1288 | StartAddress += sizeof (UINT16);\r | |
2b16a4fb MK |
1289 | Size -= sizeof (UINT16);\r |
1290 | Buffer = (UINT16 *)Buffer + 1;\r | |
ad3359eb LE |
1291 | }\r |
1292 | \r | |
1293 | while (Size >= sizeof (UINT32)) {\r | |
1294 | //\r | |
1295 | // Read as many double words as possible\r | |
1296 | //\r | |
2b16a4fb | 1297 | WriteUnaligned32 ((UINT32 *)Buffer, (UINT32)PciExpressRead32 (StartAddress));\r |
ad3359eb LE |
1298 | \r |
1299 | StartAddress += sizeof (UINT32);\r | |
2b16a4fb MK |
1300 | Size -= sizeof (UINT32);\r |
1301 | Buffer = (UINT32 *)Buffer + 1;\r | |
ad3359eb LE |
1302 | }\r |
1303 | \r | |
1304 | if (Size >= sizeof (UINT16)) {\r | |
1305 | //\r | |
1306 | // Read the last remaining word if exist\r | |
1307 | //\r | |
2b16a4fb | 1308 | WriteUnaligned16 ((UINT16 *)Buffer, (UINT16)PciExpressRead16 (StartAddress));\r |
ad3359eb | 1309 | StartAddress += sizeof (UINT16);\r |
2b16a4fb MK |
1310 | Size -= sizeof (UINT16);\r |
1311 | Buffer = (UINT16 *)Buffer + 1;\r | |
ad3359eb LE |
1312 | }\r |
1313 | \r | |
1314 | if (Size >= sizeof (UINT8)) {\r | |
1315 | //\r | |
1316 | // Read the last remaining byte if exist\r | |
1317 | //\r | |
1318 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1319 | }\r | |
1320 | \r | |
1321 | return ReturnValue;\r | |
1322 | }\r | |
1323 | \r | |
1324 | /**\r | |
1325 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1326 | configuration space.\r | |
1327 | \r | |
1328 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1329 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1330 | configuration registers from a single PCI function to be written. Size is\r | |
1331 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
7a908953 | 1332 | write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r |
ad3359eb LE |
1333 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
1334 | and the end of the range.\r | |
1335 | \r | |
1336 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1337 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1338 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1339 | \r | |
1340 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
1341 | Function and Register.\r | |
1342 | @param Size The size in bytes of the transfer.\r | |
1343 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1344 | \r | |
1345 | @return Size written to StartAddress.\r | |
1346 | \r | |
1347 | **/\r | |
1348 | UINTN\r | |
1349 | EFIAPI\r | |
1350 | PciExpressWriteBuffer (\r | |
2b16a4fb MK |
1351 | IN UINTN StartAddress,\r |
1352 | IN UINTN Size,\r | |
1353 | IN VOID *Buffer\r | |
ad3359eb LE |
1354 | )\r |
1355 | {\r | |
2b16a4fb | 1356 | UINTN ReturnValue;\r |
ad3359eb LE |
1357 | \r |
1358 | ASSERT_INVALID_PCI_ADDRESS (StartAddress);\r | |
1359 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1360 | \r | |
1361 | if (Size == 0) {\r | |
1362 | return 0;\r | |
1363 | }\r | |
1364 | \r | |
1365 | ASSERT (Buffer != NULL);\r | |
1366 | \r | |
1367 | //\r | |
1368 | // Save Size for return\r | |
1369 | //\r | |
1370 | ReturnValue = Size;\r | |
1371 | \r | |
1372 | if ((StartAddress & 1) != 0) {\r | |
1373 | //\r | |
1374 | // Write a byte if StartAddress is byte aligned\r | |
1375 | //\r | |
2b16a4fb | 1376 | PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r |
ad3359eb | 1377 | StartAddress += sizeof (UINT8);\r |
2b16a4fb MK |
1378 | Size -= sizeof (UINT8);\r |
1379 | Buffer = (UINT8 *)Buffer + 1;\r | |
ad3359eb LE |
1380 | }\r |
1381 | \r | |
2b16a4fb | 1382 | if ((Size >= sizeof (UINT16)) && ((StartAddress & 2) != 0)) {\r |
ad3359eb LE |
1383 | //\r |
1384 | // Write a word if StartAddress is word aligned\r | |
1385 | //\r | |
2b16a4fb | 1386 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r |
ad3359eb | 1387 | StartAddress += sizeof (UINT16);\r |
2b16a4fb MK |
1388 | Size -= sizeof (UINT16);\r |
1389 | Buffer = (UINT16 *)Buffer + 1;\r | |
ad3359eb LE |
1390 | }\r |
1391 | \r | |
1392 | while (Size >= sizeof (UINT32)) {\r | |
1393 | //\r | |
1394 | // Write as many double words as possible\r | |
1395 | //\r | |
2b16a4fb | 1396 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32 *)Buffer));\r |
ad3359eb | 1397 | StartAddress += sizeof (UINT32);\r |
2b16a4fb MK |
1398 | Size -= sizeof (UINT32);\r |
1399 | Buffer = (UINT32 *)Buffer + 1;\r | |
ad3359eb LE |
1400 | }\r |
1401 | \r | |
1402 | if (Size >= sizeof (UINT16)) {\r | |
1403 | //\r | |
1404 | // Write the last remaining word if exist\r | |
1405 | //\r | |
2b16a4fb | 1406 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16 *)Buffer));\r |
ad3359eb | 1407 | StartAddress += sizeof (UINT16);\r |
2b16a4fb MK |
1408 | Size -= sizeof (UINT16);\r |
1409 | Buffer = (UINT16 *)Buffer + 1;\r | |
ad3359eb LE |
1410 | }\r |
1411 | \r | |
1412 | if (Size >= sizeof (UINT8)) {\r | |
1413 | //\r | |
1414 | // Write the last remaining byte if exist\r | |
1415 | //\r | |
2b16a4fb | 1416 | PciExpressWrite8 (StartAddress, *(UINT8 *)Buffer);\r |
ad3359eb LE |
1417 | }\r |
1418 | \r | |
1419 | return ReturnValue;\r | |
1420 | }\r |