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1 | /** @file\r |
2 | \r | |
3 | Virtual Memory Management Services to set or clear the memory encryption bit\r | |
4 | \r | |
4bd6bf31 LE |
5 | Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r |
6 | Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>\r | |
a1f22614 | 7 | \r |
4bd6bf31 LE |
8 | This program and the accompanying materials are licensed and made available\r |
9 | under the terms and conditions of the BSD License which accompanies this\r | |
10 | distribution. The full text of the license may be found at\r | |
11 | http://opensource.org/licenses/bsd-license.php\r | |
a1f22614 | 12 | \r |
4bd6bf31 LE |
13 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r |
14 | WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
a1f22614 | 15 | \r |
4bd6bf31 | 16 | Code is derived from MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.h\r |
a1f22614 BS |
17 | \r |
18 | **/\r | |
19 | \r | |
20 | #ifndef __VIRTUAL_MEMORY__\r | |
21 | #define __VIRTUAL_MEMORY__\r | |
22 | \r | |
23 | #include <Uefi.h>\r | |
24 | #include <Library/BaseLib.h>\r | |
25 | #include <Library/BaseMemoryLib.h>\r | |
26 | #include <Library/DebugLib.h>\r | |
27 | #include <Library/MemoryAllocationLib.h>\r | |
28 | \r | |
29 | #include <Library/CacheMaintenanceLib.h>\r | |
30 | #define SYS_CODE64_SEL 0x38\r | |
31 | \r | |
32 | #pragma pack(1)\r | |
33 | \r | |
34 | //\r | |
35 | // Page-Map Level-4 Offset (PML4) and\r | |
36 | // Page-Directory-Pointer Offset (PDPE) entries 4K & 2MB\r | |
37 | //\r | |
38 | \r | |
39 | typedef union {\r | |
40 | struct {\r | |
4bd6bf31 LE |
41 | UINT64 Present:1; // 0 = Not present in memory,\r |
42 | // 1 = Present in memory\r | |
a1f22614 BS |
43 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r |
44 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
4bd6bf31 LE |
45 | UINT64 WriteThrough:1; // 0 = Write-Back caching,\r |
46 | // 1 = Write-Through caching\r | |
a1f22614 | 47 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r |
4bd6bf31 LE |
48 | UINT64 Accessed:1; // 0 = Not accessed,\r |
49 | // 1 = Accessed (set by CPU)\r | |
a1f22614 BS |
50 | UINT64 Reserved:1; // Reserved\r |
51 | UINT64 MustBeZero:2; // Must Be Zero\r | |
52 | UINT64 Available:3; // Available for use by system software\r | |
53 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
54 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
55 | UINT64 Nx:1; // No Execute bit\r | |
56 | } Bits;\r | |
57 | UINT64 Uint64;\r | |
58 | } PAGE_MAP_AND_DIRECTORY_POINTER;\r | |
59 | \r | |
60 | //\r | |
61 | // Page Table Entry 4KB\r | |
62 | //\r | |
63 | typedef union {\r | |
64 | struct {\r | |
4bd6bf31 LE |
65 | UINT64 Present:1; // 0 = Not present in memory,\r |
66 | // 1 = Present in memory\r | |
a1f22614 BS |
67 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r |
68 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
4bd6bf31 LE |
69 | UINT64 WriteThrough:1; // 0 = Write-Back caching,\r |
70 | // 1 = Write-Through caching\r | |
a1f22614 | 71 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r |
4bd6bf31 LE |
72 | UINT64 Accessed:1; // 0 = Not accessed,\r |
73 | // 1 = Accessed (set by CPU)\r | |
74 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r | |
75 | // processor on access to page\r | |
a1f22614 | 76 | UINT64 PAT:1; //\r |
4bd6bf31 LE |
77 | UINT64 Global:1; // 0 = Not global page, 1 = global page\r |
78 | // TLB not cleared on CR3 write\r | |
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79 | UINT64 Available:3; // Available for use by system software\r |
80 | UINT64 PageTableBaseAddress:40; // Page Table Base Address\r | |
81 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
4bd6bf31 LE |
82 | UINT64 Nx:1; // 0 = Execute Code,\r |
83 | // 1 = No Code Execution\r | |
a1f22614 BS |
84 | } Bits;\r |
85 | UINT64 Uint64;\r | |
86 | } PAGE_TABLE_4K_ENTRY;\r | |
87 | \r | |
88 | //\r | |
89 | // Page Table Entry 2MB\r | |
90 | //\r | |
91 | typedef union {\r | |
92 | struct {\r | |
4bd6bf31 LE |
93 | UINT64 Present:1; // 0 = Not present in memory,\r |
94 | // 1 = Present in memory\r | |
a1f22614 BS |
95 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r |
96 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
4bd6bf31 LE |
97 | UINT64 WriteThrough:1; // 0 = Write-Back caching,\r |
98 | // 1=Write-Through caching\r | |
a1f22614 | 99 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r |
4bd6bf31 LE |
100 | UINT64 Accessed:1; // 0 = Not accessed,\r |
101 | // 1 = Accessed (set by CPU)\r | |
102 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r | |
103 | // processor on access to page\r | |
a1f22614 | 104 | UINT64 MustBe1:1; // Must be 1\r |
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105 | UINT64 Global:1; // 0 = Not global page, 1 = global page\r |
106 | // TLB not cleared on CR3 write\r | |
a1f22614 BS |
107 | UINT64 Available:3; // Available for use by system software\r |
108 | UINT64 PAT:1; //\r | |
109 | UINT64 MustBeZero:8; // Must be zero;\r | |
110 | UINT64 PageTableBaseAddress:31; // Page Table Base Address\r | |
111 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
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112 | UINT64 Nx:1; // 0 = Execute Code,\r |
113 | // 1 = No Code Execution\r | |
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114 | } Bits;\r |
115 | UINT64 Uint64;\r | |
116 | } PAGE_TABLE_ENTRY;\r | |
117 | \r | |
118 | //\r | |
119 | // Page Table Entry 1GB\r | |
120 | //\r | |
121 | typedef union {\r | |
122 | struct {\r | |
4bd6bf31 LE |
123 | UINT64 Present:1; // 0 = Not present in memory,\r |
124 | // 1 = Present in memory\r | |
a1f22614 BS |
125 | UINT64 ReadWrite:1; // 0 = Read-Only, 1= Read/Write\r |
126 | UINT64 UserSupervisor:1; // 0 = Supervisor, 1=User\r | |
4bd6bf31 LE |
127 | UINT64 WriteThrough:1; // 0 = Write-Back caching,\r |
128 | // 1 = Write-Through caching\r | |
a1f22614 | 129 | UINT64 CacheDisabled:1; // 0 = Cached, 1=Non-Cached\r |
4bd6bf31 LE |
130 | UINT64 Accessed:1; // 0 = Not accessed,\r |
131 | // 1 = Accessed (set by CPU)\r | |
132 | UINT64 Dirty:1; // 0 = Not Dirty, 1 = written by\r | |
133 | // processor on access to page\r | |
a1f22614 | 134 | UINT64 MustBe1:1; // Must be 1\r |
4bd6bf31 LE |
135 | UINT64 Global:1; // 0 = Not global page, 1 = global page\r |
136 | // TLB not cleared on CR3 write\r | |
a1f22614 BS |
137 | UINT64 Available:3; // Available for use by system software\r |
138 | UINT64 PAT:1; //\r | |
139 | UINT64 MustBeZero:17; // Must be zero;\r | |
140 | UINT64 PageTableBaseAddress:22; // Page Table Base Address\r | |
141 | UINT64 AvabilableHigh:11; // Available for use by system software\r | |
4bd6bf31 LE |
142 | UINT64 Nx:1; // 0 = Execute Code,\r |
143 | // 1 = No Code Execution\r | |
a1f22614 BS |
144 | } Bits;\r |
145 | UINT64 Uint64;\r | |
146 | } PAGE_TABLE_1G_ENTRY;\r | |
147 | \r | |
148 | #pragma pack()\r | |
149 | \r | |
150 | #define IA32_PG_P BIT0\r | |
151 | #define IA32_PG_RW BIT1\r | |
b721aa74 BS |
152 | #define IA32_PG_PS BIT7\r |
153 | \r | |
154 | #define PAGING_PAE_INDEX_MASK 0x1FF\r | |
155 | \r | |
156 | #define PAGING_4K_ADDRESS_MASK_64 0x000FFFFFFFFFF000ull\r | |
157 | #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull\r | |
158 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r | |
159 | \r | |
160 | #define PAGING_L1_ADDRESS_SHIFT 12\r | |
161 | #define PAGING_L2_ADDRESS_SHIFT 21\r | |
162 | #define PAGING_L3_ADDRESS_SHIFT 30\r | |
163 | #define PAGING_L4_ADDRESS_SHIFT 39\r | |
164 | \r | |
165 | #define PAGING_PML4E_NUMBER 4\r | |
a1f22614 BS |
166 | \r |
167 | #define PAGETABLE_ENTRY_MASK ((1UL << 9) - 1)\r | |
168 | #define PML4_OFFSET(x) ( (x >> 39) & PAGETABLE_ENTRY_MASK)\r | |
169 | #define PDP_OFFSET(x) ( (x >> 30) & PAGETABLE_ENTRY_MASK)\r | |
170 | #define PDE_OFFSET(x) ( (x >> 21) & PAGETABLE_ENTRY_MASK)\r | |
171 | #define PTE_OFFSET(x) ( (x >> 12) & PAGETABLE_ENTRY_MASK)\r | |
172 | #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull\r | |
173 | \r | |
b721aa74 BS |
174 | #define PAGE_TABLE_POOL_ALIGNMENT BASE_2MB\r |
175 | #define PAGE_TABLE_POOL_UNIT_SIZE SIZE_2MB\r | |
4bd6bf31 LE |
176 | #define PAGE_TABLE_POOL_UNIT_PAGES \\r |
177 | EFI_SIZE_TO_PAGES (PAGE_TABLE_POOL_UNIT_SIZE)\r | |
b721aa74 BS |
178 | #define PAGE_TABLE_POOL_ALIGN_MASK \\r |
179 | (~(EFI_PHYSICAL_ADDRESS)(PAGE_TABLE_POOL_ALIGNMENT - 1))\r | |
180 | \r | |
181 | typedef struct {\r | |
182 | VOID *NextPool;\r | |
183 | UINTN Offset;\r | |
184 | UINTN FreePages;\r | |
185 | } PAGE_TABLE_POOL;\r | |
186 | \r | |
187 | \r | |
188 | \r | |
a1f22614 | 189 | /**\r |
4bd6bf31 LE |
190 | This function clears memory encryption bit for the memory region specified by\r |
191 | PhysicalAddress and length from the current page table context.\r | |
a1f22614 | 192 | \r |
4bd6bf31 LE |
193 | @param[in] PhysicalAddress The physical address that is the start\r |
194 | address of a memory region.\r | |
a1f22614 | 195 | @param[in] Length The length of memory region\r |
4bd6bf31 LE |
196 | @param[in] Flush Flush the caches before applying the\r |
197 | encryption mask\r | |
a1f22614 | 198 | \r |
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199 | @retval RETURN_SUCCESS The attributes were cleared for the\r |
200 | memory region.\r | |
a1f22614 | 201 | @retval RETURN_INVALID_PARAMETER Number of pages is zero.\r |
4bd6bf31 LE |
202 | @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r |
203 | is not supported\r | |
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204 | **/\r |
205 | RETURN_STATUS\r | |
206 | EFIAPI\r | |
207 | InternalMemEncryptSevSetMemoryDecrypted (\r | |
208 | IN PHYSICAL_ADDRESS Cr3BaseAddress,\r | |
209 | IN PHYSICAL_ADDRESS PhysicalAddress,\r | |
210 | IN UINT64 Length,\r | |
211 | IN BOOLEAN CacheFlush\r | |
212 | );\r | |
213 | \r | |
214 | /**\r | |
215 | This function sets memory encryption bit for the memory region specified by\r | |
216 | PhysicalAddress and length from the current page table context.\r | |
217 | \r | |
4bd6bf31 LE |
218 | @param[in] PhysicalAddress The physical address that is the start\r |
219 | address of a memory region.\r | |
a1f22614 BS |
220 | @param[in] Length The length of memory region\r |
221 | @param[in] Flush Flush the caches before applying the\r | |
222 | encryption mask\r | |
223 | \r | |
4bd6bf31 LE |
224 | @retval RETURN_SUCCESS The attributes were cleared for the\r |
225 | memory region.\r | |
a1f22614 | 226 | @retval RETURN_INVALID_PARAMETER Number of pages is zero.\r |
4bd6bf31 LE |
227 | @retval RETURN_UNSUPPORTED Setting the memory encyrption attribute\r |
228 | is not supported\r | |
a1f22614 BS |
229 | **/\r |
230 | RETURN_STATUS\r | |
231 | EFIAPI\r | |
232 | InternalMemEncryptSevSetMemoryEncrypted (\r | |
233 | IN PHYSICAL_ADDRESS Cr3BaseAddress,\r | |
234 | IN PHYSICAL_ADDRESS PhysicalAddress,\r | |
235 | IN UINT64 Length,\r | |
236 | IN BOOLEAN CacheFlush\r | |
237 | );\r | |
238 | \r | |
239 | #endif\r |